/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_fb_h__ #define __ga102_dev_fb_h__ /* This file is autogenerated. Do not edit */ #define NV_PFB 0x00100FFF:0x00100000 /* RW--D */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK 0x00100784 /* RW-4R */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PFB_FBIO_CAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG 0x00100700 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_CFG__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_CFG_PERIOD 15:0 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG_PERIOD_100MS 0x000000A5 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG_PERIOD_15K 0x00003A98 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG_INTERVAL 23:16 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG_INTERVAL_10 0x0000000A /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG_INTERVAL_48 0x00000030 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG_DRVDLY 26:24 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG_DRVDLY_5 0x00000005 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG_MAXDRIVE 27:27 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG_MAXDRIVE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG_MAXDRIVE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG_LIMIT_BW 28:28 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_CFG_LIMIT_BW_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG_LIMIT_BW_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MIN 29:29 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MAX 30:30 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MAX_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG_CLAMP_MAX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG_AUTOCOMP 31:31 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_CFG_AUTOCOMP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG_AUTOCOMP_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MIN 0x00100704 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MIN__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_RISE 6:0 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_RISE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_FALL 14:8 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_FALL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_TERM 22:16 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MIN_TERM_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MAX 0x00100708 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MAX__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_RISE 6:0 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_RISE_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_FALL 14:8 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_FALL_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_TERM 22:16 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CLAMP_MAX_TERM_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL 0x0010070C /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_TEST_VAL 6:0 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_TEST_VAL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_EN 7:7 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_EN 8:8 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_TERM_EN 9:9 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_TERM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_TERM_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN 16:10 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN_INIT 0x0000004D /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_LOCK 24:24 /* R-XVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_LOCK 25:25 /* R-XVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_TERM_LOCK 26:26 /* R-XVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_RISE_SLEW_LOCK 27:27 /* R-XVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_FALL_SLEW_LOCK 28:28 /* R-XVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_DQS_DLY 29:29 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_DQS_DLY_THERMO 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_DQS_DLY_DIRECT 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_MODE 30:30 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_MODE_DRIVE 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_MODE_SLEW 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_SELECT 31:31 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_SELECT_HW 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SW_CTRL_SELECT_SW 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_RB 0x00100710 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_RB__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_RB_RISE 6:0 /* R--VF */ #define NV_PFB_FBIO_CALMASTER_RB_FALL 14:8 /* R--VF */ #define NV_PFB_FBIO_CALMASTER_RB_TERM 22:16 /* R--VF */ #define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE 31:31 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE_DONE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE_PENDING 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE_RESET 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_RB_CAL_CYCLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB2 0x00100714 /* R--4R */ #define NV_PFB_FBIO_CALMASTER_RB2__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_RB2_RISE 6:0 /* R--VF */ #define NV_PFB_FBIO_CALMASTER_RB2_FALL 14:8 /* R--VF */ #define NV_PFB_FBIO_CALMASTER_RB3 0x00100760 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_RB3__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_RB3_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB3_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB3_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB3_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB3_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB3_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB3_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB3_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB4 0x00100764 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_RB4__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_RB4_TERM_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB4_TERM_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB4_TERM_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB4_TERM_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB5 0x00100768 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_RB5__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_RB5_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB5_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB5_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB5_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB5_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB5_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_RB5_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_RB5_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG 0x00100770 /* RW-4R */ #define NV_PFB_FBIO_CALGROUP_CFG__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALGROUP_CFG_VDDP_MODE 1:0 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG_VDDP_MODE_V1P5 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG_VDDP_MODE_V1P35 0x00000002 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_CFG_VDDP_MODE_V1P25 0x00000003 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_CFG_PU40_MODE 2:2 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG_PU40_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_CFG_PU40_MODE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_PU_CAL_SEL 15:15 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_PU_CAL_SEL_50PVREF 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_PU_CAL_SEL_VREFSEL 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_PD_CAL_SEL 23:23 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_PD_CAL_SEL_50PVREF 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_PD_CAL_SEL_VREFSEL 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_TERM_CAL_SEL 31:31 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_TERM_CAL_SEL_50PVREF 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG_COMP_TERM_CAL_SEL_VREFSEL 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_CFG2 0x00100774 /* RW-4R */ #define NV_PFB_FBIO_CALGROUP_CFG2__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_EN 0:0 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_EN_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_EN_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_MUX_UGA_ENABLE 1:1 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_MUX_UGA_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_MUX_UGA_SWAP 2:2 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_MUX_UGA_SWAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_OUT_SEL 8:4 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_OUT_SEL_F 0x0000000F /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_CONFIG_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_PWRD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_CFG2_TEST_PWRD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN 0x00100778 /* RW-4R */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXP 2:0 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXP_0 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VCLAMP 6:4 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VCLAMP_0 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VCLAMP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXC 10:8 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXC_0 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXP_LOAD 14:12 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXP_LOAD_0 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXP_LOAD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VCLAMP_LOAD 16:15 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VCLAMP_LOAD_0 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VCLAMP_LOAD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VCLAMP_SRBOOST 19:17 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VCLAMP_SRBOOST_0 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VCLAMP_SRBOOST_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXC_LOAD 22:20 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXC_LOAD_0 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VAUXC_LOAD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VCLAMP_BW 29:26 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VCLAMP_BW_0 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTT_VCLAMP_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTTGEN_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_VTTGEN_VAUXGEN_VTTGEN_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR 0x00100718 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2 0x0010071C /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVR2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF 0x00100720 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2 0x00100724 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVF2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT 0x00100728 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT_DQS 3:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT_DAT 11:8 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR 0x0010072C /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR_DQS 27:24 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWR_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF 0x00100730 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF_DQS 27:24 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_SLOPE_SLWF_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR 0x00100734 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR 6:0 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2 0x00100738 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2_DQS 6:0 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2_DAT 14:8 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVR2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF 0x0010073C /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR 6:0 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2 0x00100740 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2_DQS 6:0 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2_DAT 14:8 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVF2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT 0x00100744 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT_DQS 6:0 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT_DAT 14:8 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR 0x00100748 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR_ADR 6:0 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR_DQS 30:24 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWR_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF 0x0010074C /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF_ADR 6:0 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF_DQS 30:24 /* RWISF */ #define NV_PFB_FBIO_CALMASTER_OFFSET_SLWF_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2 0x00100750 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_CFG2__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_CFG2_TERM 0:0 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG2_TERM_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG2_TERM_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_TRIGGER_CAL_CYCLE 3:3 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_INACTIVE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_ENABLED 0x00000001 /* -W--T */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_AUTO 4:4 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_AUTO_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_AUTO_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_MODE 5:5 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_CYCLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_STEP 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_RX_PWRD 1:1 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_RX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_RX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_INT_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_INT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_EXT_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_EXT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_ENABLE 6:6 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG2_SAMPLE_COUNT 11:8 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG2_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_SAMPLE_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG2_LOCK_COUNT 15:12 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG2_LOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG2_LOCK_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_DLY 31:16 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG2_COMP_POWERUP_DLY_1024 0x00000400 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG3 0x00100754 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_CFG3__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_COMP 0:0 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_COMP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_COMP_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWR_EN 1:1 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWR_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWR_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWF_EN 2:2 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWF_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_SLWF_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL 4:3 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_1 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_2 0x00000002 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_3 0x00000003 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG3_TERM_MODE 5:5 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG3_TERM_MODE_UP 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG3_TERM_MODE_DN 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG3_RISE_START_VAL 14:8 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG3_RISE_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG3_FALL_START_VAL 22:16 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG3_FALL_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG3_TERM_START_VAL 30:24 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG3_TERM_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3 0x00100758 /* RW-4R */ #define NV_PFB_FBIO_CALGROUP_CFG3__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALGROUP_CFG3_IREF_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_IREF_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALGROUP_CFG3_IREF_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3_ISOURCE_CTRL 3:2 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3_ISOURCE_CTRL_IMIX 5:4 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3_ISOURCE_CTRL_IBG 7:6 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_LIMITER 10:8 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_LIMITER 14:12 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_BW 19:16 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_BW 23:20 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_SRBOOST 26:24 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXP_SRBOOST_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_SRBOOST 30:28 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG3_VTT_VAUXC_SRBOOST_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG4 0x0010075C /* RW-4R */ #define NV_PFB_FBIO_CALGROUP_CFG4__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALGROUP_CFG4_COMP_PU_VREFP_CODE 7:0 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG4_COMP_PU_VREFP_CODE_50PVREF 0x00000040 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG4_COMP_PD_VREFP_CODE 15:8 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG4_COMP_PD_VREFP_CODE_50PVREF 0x00000040 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG4_COMP_TERM_VREFP_CODE 23:16 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG4_COMP_TERM_VREFP_CODE_50PVREF 0x00000040 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG4_TEST_VREFP_CODE 31:24 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG4_TEST_VREFP_CODE_50PVREF 0x00000040 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG5 0x0010077C /* RW-4R */ #define NV_PFB_FBIO_CALGROUP_CFG5__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALGROUP_CFG5_COMP_PU_VREFN_CODE 5:0 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG5_COMP_PU_VREFN_CODE_50PVREF 0x00000020 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG5_COMP_PD_VREFN_CODE 13:8 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG5_COMP_PD_VREFN_CODE_50PVREF 0x00000020 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG5_COMP_TERM_VREFN_CODE 21:16 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG5_COMP_TERM_VREFN_CODE_50PVREF 0x00000020 /* RWI-V */ #define NV_PFB_FBIO_CALGROUP_CFG5_TEST_VREFN_CODE 30:24 /* RWIVF */ #define NV_PFB_FBIO_CALGROUP_CFG5_TEST_VREFN_CODE_50PVREF 0x00000020 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG4 0x00100780 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_CFG4__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_CFG4_RES_CAL 0:0 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG4_RES_CAL_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG4_RES_CAL_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG4_RES_CAL_CNTL 4:1 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG4_RES_CAL_CNTL_0 0x00000009 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG4_HSDAC_EN 5:5 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG4_HSDAC_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG4_HSDAC_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBIO_CALMASTER_CFG4_DAC_GAIN 7:6 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG4_DAC_GAIN_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG4_RES_CAL_OVRRD 8:8 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG4_RES_CAL_OVRRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG4_RES_CAL_OVRRD_CODE 13:9 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG4_RES_CAL_OVRRD_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG5 0x00100788 /* RW-4R */ #define NV_PFB_FBIO_CALMASTER_CFG5__PRIV_LEVEL_MASK 0x00100784 /* */ #define NV_PFB_FBIO_CALMASTER_CFG5_DPD 0:0 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG5_DPD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG5_COMP0_CAL_SWAP 1:1 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG5_COMP0_CAL_SWAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG5_COMP1_CAL_SWAP 2:2 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG5_COMP1_CAL_SWAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG5_COMP2_CAL_SWAP 3:3 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG5_COMP2_CAL_SWAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBIO_CALMASTER_CFG5_RES_CAL_SWAP 5:4 /* RWIUF */ #define NV_PFB_FBIO_CALMASTER_CFG5_RES_CAL_SWAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK 0x00100B30 /* RW-4R */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pfb_amap" /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PFB_NISO_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK 0x00100B34 /* RW-4R */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PFB_NISO_BLCG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK 0x00100B38 /* RW-4R */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pfb_cya" /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PFB_NISO_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK 0x00100B3C /* RW-4R */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PFB_NISO_OPEN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS 0x00100800 /* RW-4R */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS__PRIV_LEVEL_MASK 0x00100B30 /* */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_V_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_COUNT 4:0 /* RW-VF */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_USE_NVLINK 23:16 /* RWIVF */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_USE_NVLINK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i) ((i)+16):((i)+16) /* */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1 8 /* */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED 0x00000001 /* */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED 0x00000000 /* */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWIVF */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE 25:25 /* RWIVF */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE_USE_READ 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE_USE_RMW 0x00000001 /* RW--V */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE 26:26 /* RWIVF */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE_USE_READ 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE_FOLLOW_COH 0x00000001 /* RW--V */ #define NV_PFB_NISO_DISPLAY_UPPER_ADDR(i) (0x00100B00+(i)*4) /* RW-4A */ #define NV_PFB_NISO_DISPLAY_UPPER_ADDR__SIZE_1 4 /* */ #define NV_PFB_NISO_DISPLAY_UPPER_ADDR_B46_37_0 9:0 /* RWIVF */ #define NV_PFB_NISO_DISPLAY_UPPER_ADDR_B46_37_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_DISPLAY_UPPER_ADDR_B46_37_1 25:16 /* RWIVF */ #define NV_PFB_NISO_DISPLAY_UPPER_ADDR_B46_37_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG2 0x00100B40 /* RW-4R */ #define NV_PFB_NISO_PRI_DEBUG2__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_PRI_DEBUG2_READ_PACKING 0:0 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG2_READ_PACKING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG2_READ_PACKING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG2_WRITE_CONCAT 1:1 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG2_WRITE_CONCAT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG2_WRITE_CONCAT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG2_VIDEO_VIDMEM_USE_BLOCKING_VC 2:2 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG2_VIDEO_VIDMEM_USE_BLOCKING_VC_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG2_VIDEO_VIDMEM_USE_BLOCKING_VC_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG2_SYSMEMBAR_PUSHES_READS 3:3 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG2_SYSMEMBAR_PUSHES_READS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG2_SYSMEMBAR_PUSHES_READS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG2_MMU_MISSES_ON_VC_LL 4:4 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG2_MMU_MISSES_ON_VC_LL_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG2_MMU_MISSES_ON_VC_LL_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG2_RARB_CTRL 15:8 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG2_RARB_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG2_DISP_HEADS_RDAT_OOO 16:16 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG2_DISP_HEADS_RDAT_OOO_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG2_DISP_HEADS_RDAT_OOO_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3 0x00100B44 /* RW-4R */ #define NV_PFB_NISO_PRI_DEBUG3__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_MMU_FILL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_MMU_FILL_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_MMU_FILL_ENABLE_ON 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_HOST_ENABLE 1:1 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_HOST_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_HOST_ENABLE_ON 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_CE_ENABLE 2:2 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_CE_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_CE_ENABLE_ON 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_PERF_ENABLE 3:3 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_PERF_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_PERF_ENABLE_ON 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_PMU_ENABLE 4:4 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_PMU_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_PMU_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_SEC_ENABLE 5:5 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_SEC_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_SEC_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_GSP_ENABLE 6:6 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_GSP_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_GSP_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_CE_SHIM_ENABLE 7:7 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_CE_SHIM_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_CE_SHIM_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_ACTRS_ENABLE 8:8 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_ACTRS_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_ACTRS_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_NVDEC_ENABLE 9:9 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_NVDEC_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_NVDEC_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_NVENC_ENABLE 10:10 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_NVENC_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_NVENC_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_NVJPG_ENABLE 11:11 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_NVJPG_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_NVJPG_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_OFA_ENABLE 12:12 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_OFA_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_OFA_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_ESC_ENABLE 13:13 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_ESC_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG3_L2B_ESC_ENABLE_ON 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_ERROR_STATUS 0x00100B48 /* RW-4R */ #define NV_PFB_NISO_PRI_ERROR_STATUS_KIND_NONGMK_PEER_CACHING_OFF 0:0 /* RWIVF */ #define NV_PFB_NISO_PRI_ERROR_STATUS_KIND_NONGMK_PEER_CACHING_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_ERROR_STATUS_KIND_NONGMK_PEER_CACHING_OFF_SET 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_ERROR_STATUS_KIND_NONGMK_PEER_CACHING_OFF_CLR 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0 0x00100C00 /* RW-4R */ #define NV_PFB_NISO_CFG0__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_CFG0_SPARE 8:0 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE_INIT 0x0000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPLIT_COMPRESSIBLE_SYSMEM_WRITES 9:9 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPLIT_COMPRESSIBLE_SYSMEM_WRITES_INIT 0x0 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPLIT_COMPRESSIBLE_SYSMEM_WRITES_ENABLED 0x01 /* RW--V */ #define NV_PFB_NISO_CFG0_SPLIT_COMPRESSIBLE_SYSMEM_WRITES_DISABLED 0x0 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_IGNORE 12:12 /* RWIVF */ #define NV_PFB_NISO_CFG0_FLUSH_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_FLUSH_IGNORE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_IGNORE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_FBXV0 13:13 /* RWIVF */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_FBXV0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_FBXV0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_FBXV0_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_FBXV1 14:14 /* RWIVF */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_FBXV1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_FBXV1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_FBXV1_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE_15 15:15 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE_15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_FORCE_SYSMEM_FLUSH 16:16 /* RWIVF */ #define NV_PFB_NISO_CFG0_FORCE_SYSMEM_FLUSH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_FORCE_SYSMEM_FLUSH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_FORCE_SYSMEM_FLUSH_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_FORCE_PEER_FLUSH 17:17 /* RWIVF */ #define NV_PFB_NISO_CFG0_FORCE_PEER_FLUSH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_FORCE_PEER_FLUSH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_FORCE_PEER_FLUSH_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_PEERS 19:19 /* RWIVF */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_PEERS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_PEERS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_SKIP_PEERS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE20 20:20 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPARE20_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE20_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_OPT_SYS 21:21 /* RWIVF */ #define NV_PFB_NISO_CFG0_FLUSH_OPT_SYS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_FLUSH_OPT_SYS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_OPT_SYS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_OPT_PEER 22:22 /* RWIVF */ #define NV_PFB_NISO_CFG0_FLUSH_OPT_PEER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG0_FLUSH_OPT_PEER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_FLUSH_OPT_PEER_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE23 23:23 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPARE23_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE23_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE24 24:24 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE24_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPARE24_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE24_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE25 25:25 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE25_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPARE25_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE25_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE26 26:26 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE26_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPARE26_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE26_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE27 27:27 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE27_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPARE27_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE27_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_FBH2HSH_DBI 28:28 /* RWIVF */ #define NV_PFB_NISO_CFG0_FBH2HSH_DBI_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG0_FBH2HSH_DBI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_FBH2HSH_DBI_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE29 29:29 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE29_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPARE29_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE29_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE30 30:30 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE30_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPARE30_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE30_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE31 31:31 /* RWIVF */ #define NV_PFB_NISO_CFG0_SPARE31_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG0_SPARE31_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG0_SPARE31_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG1 0x00100C14 /* RW-4R */ #define NV_PFB_NISO_CFG1_SYSMEM_NVLINK 17:17 /* RWIVF */ #define NV_PFB_NISO_CFG1_SYSMEM_NVLINK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG1_SYSMEM_NVLINK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG1_DISPLAY_ADDR_REMAPPER 18:18 /* RWIVF */ #define NV_PFB_NISO_CFG1_DISPLAY_ADDR_REMAPPER_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_CFG1_DISPLAY_ADDR_REMAPPER_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_CONFIG 30:28 /* RWIVF */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_CONFIG_0 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_CONFIG_1 0x00000001 /* RW--V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_CONFIG_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_CONFIG_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_CONFIG_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_CONFIG_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_CONFIG_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_CONFIG_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_EN 31:31 /* RWIVF */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_EN_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_CFG1_DEBUG_BUS_EN_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_ARB0 0x00100C04 /* RW-4R */ #define NV_PFB_NISO_ARB0__PRIV_LEVEL_MASK 0x00100B3C /* */ #define NV_PFB_NISO_ARB0_PRIO_PD 3:0 /* RWIVF */ #define NV_PFB_NISO_ARB0_PRIO_PD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB0_PRIO_DNISO 7:4 /* RWIVF */ #define NV_PFB_NISO_ARB0_PRIO_DNISO_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB0_PRIO_NVENC1 11:8 /* RWIVF */ #define NV_PFB_NISO_ARB0_PRIO_NVENC1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_NISO_ARB0_PRIO_FE 15:12 /* RWIVF */ #define NV_PFB_NISO_ARB0_PRIO_FE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB0_PRIO_FECS 19:16 /* RWIVF */ #define NV_PFB_NISO_ARB0_PRIO_FECS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB0_PRIO_HOST 23:20 /* RWIVF */ #define NV_PFB_NISO_ARB0_PRIO_HOST_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB0_PRIO_HOST_NB 27:24 /* RWIVF */ #define NV_PFB_NISO_ARB0_PRIO_HOST_NB_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB0_PRIO_SCC 31:28 /* RWIVF */ #define NV_PFB_NISO_ARB0_PRIO_SCC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB1 0x00100C08 /* RW-4R */ #define NV_PFB_NISO_ARB1__PRIV_LEVEL_MASK 0x00100B3C /* */ #define NV_PFB_NISO_ARB1_PRIO_NVENC2 3:0 /* RWIVF */ #define NV_PFB_NISO_ARB1_PRIO_NVENC2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB1_PRIO_SEC 7:4 /* RWIVF */ #define NV_PFB_NISO_ARB1_PRIO_SEC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB1_PRIO_NVDEC0 11:8 /* RWIVF */ #define NV_PFB_NISO_ARB1_PRIO_NVDEC0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB1_PRIO_CE0 15:12 /* RWIVF */ #define NV_PFB_NISO_ARB1_PRIO_CE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB1_PRIO_CE1 19:16 /* RWIVF */ #define NV_PFB_NISO_ARB1_PRIO_CE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB1_PRIO_PTP 27:24 /* RWIVF */ #define NV_PFB_NISO_ARB1_PRIO_PTP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB1_PRIO_FILL 31:28 /* RWIVF */ #define NV_PFB_NISO_ARB1_PRIO_FILL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB2 0x00100C0C /* RW-4R */ #define NV_PFB_NISO_ARB2__PRIV_LEVEL_MASK 0x00100B3C /* */ #define NV_PFB_NISO_ARB2_PRIO_SKED 3:0 /* RWIVF */ #define NV_PFB_NISO_ARB2_PRIO_SKED_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB2_PRIO_PMU 7:4 /* RWIVF */ #define NV_PFB_NISO_ARB2_PRIO_PMU_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB2_PRIO_CE2 11:8 /* RWIVF */ #define NV_PFB_NISO_ARB2_PRIO_CE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB2_PRIO_PERF 15:12 /* RWIVF */ #define NV_PFB_NISO_ARB2_PRIO_PERF_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB2_PRIO_NVENC0 23:20 /* RWIVF */ #define NV_PFB_NISO_ARB2_PRIO_NVENC0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB2_PRIO_HOST_NONCPU 27:24 /* RWIVF */ #define NV_PFB_NISO_ARB2_PRIO_HOST_NONCPU_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB2_PRIO_SCC_NB 31:28 /* RWIVF */ #define NV_PFB_NISO_ARB2_PRIO_SCC_NB_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB3 0x00100C24 /* RW-4R */ #define NV_PFB_NISO_ARB3__PRIV_LEVEL_MASK 0x00100B3C /* */ #define NV_PFB_NISO_ARB3_PRIO_FBFALCON 7:4 /* RWIVF */ #define NV_PFB_NISO_ARB3_PRIO_FBFALCON_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB3_PRIO_DISPNISO 11:8 /* RWIVF */ #define NV_PFB_NISO_ARB3_PRIO_DISPNISO_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB3_PRIO_GSP 15:12 /* RWIVF */ #define NV_PFB_NISO_ARB3_PRIO_GSP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB3_PRIO_CE_SHIM 19:16 /* RWIVF */ #define NV_PFB_NISO_ARB3_PRIO_CE_SHIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB3_PRIO_ACTRS 23:20 /* RWIVF */ #define NV_PFB_NISO_ARB3_PRIO_ACTRS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB3_PRIO_NVDEC1 27:24 /* RWIVF */ #define NV_PFB_NISO_ARB3_PRIO_NVDEC1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB4 0x00100C2C /* RW-4R */ #define NV_PFB_NISO_ARB4__PRIV_LEVEL_MASK 0x00100B3C /* */ #define NV_PFB_NISO_ARB4_PRIO_NVJPG0 3:0 /* RWIVF */ #define NV_PFB_NISO_ARB4_PRIO_NVJPG0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ARB4_PRIO_OFA0 23:20 /* RWIVF */ #define NV_PFB_NISO_ARB4_PRIO_OFA0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR 0x00100C10 /* RW-4R */ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_SHIFT 8 /* */ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08 31:0 /* RWIVF */ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_ADR_39_08_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI 0x00100C40 /* RW-4R */ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI_MASK 0x7F /* */ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI_ADR_63_40 23:0 /* RWIVF */ #define NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI_ADR_63_40_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_CLIENT 0x00100C18 /* RW-4R */ #define NV_PFB_NISO_PM_CLIENT_SEL0 10:0 /* RWIVF */ #define NV_PFB_NISO_PM_CLIENT_SEL0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_STATIC_PATTERN_0_1_GROUP 0x000007FE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_STATIC_PATTERN_1_1_GROUP 0x000007FF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST 0x00000001 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU 0x00000002 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB 0x00000003 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0 0x00000004 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1 0x00000005 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2 0x00000006 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3 0x00000007 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4 0x00000008 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5 0x00000009 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6 0x0000000A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7 0x0000000B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8 0x0000000C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9 0x0000000D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10 0x0000000E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11 0x0000000F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P 0x00000010 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU 0x00000011 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB 0x00000012 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0 0x00000013 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1 0x00000014 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2 0x00000015 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM 0x00000016 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE 0x00000017 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0 0x00000018 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1 0x00000019 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2 0x0000001A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3 0x0000001B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4 0x0000001C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5 0x0000001D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6 0x0000001E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7 0x0000001F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED 0x00000020 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0 0x00000021 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1 0x00000022 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2 0x00000023 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3 0x00000024 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4 0x00000025 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5 0x00000026 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6 0x00000027 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7 0x00000028 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC 0x00000029 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB 0x0000002A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD 0x0000002B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC 0x0000002C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP 0x0000002D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU 0x0000002E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF 0x0000002F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON 0x00000030 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO 0x00000031 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF 0x00000032 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0 0x00000033 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1 0x00000034 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2 0x00000035 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3 0x00000036 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4 0x00000037 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5 0x00000038 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0 0x00000039 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1 0x0000003A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2 0x0000003B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0 0x0000003C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1 0x0000003D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2 0x0000003E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0 0x0000003F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS 0x00000040 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_BAR 0x00000041 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XBAR 0x00000042 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CACHE_REQ 0x00000043 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_NCACHE_REQ 0x00000044 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_VIDMEM_REQ 0x00000045 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_L2BYPASS_REQ 0x00000046 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_REQ_NO_CL 0x00000047 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_REQ_CL_NO_GNT 0x00000048 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_REQ_HOL_BLOCKED 0x00000049 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_REQ_RT_BLOCKED 0x0000004A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_REQ_FAM_BLOCKED 0x0000004B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_REQ_CACHEOP_BLOCKED 0x0000004C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_RBUF_FULL 0x0000004D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_MMU_PENDING 0x0000004E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_WDAT_BUFFER_FULL 0x0000004F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_REQ_GNT 0x00000050 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_WR_GRANT 0x00000051 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_RD_GRANT 0x00000052 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_FL_GRANT 0x00000053 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_RD_OUTSTANDING 0x00000054 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_SYSMEM_RD_OUTSTANDING 0x00000055 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_CACHE_REQ 0x00000056 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NCACHE_REQ 0x00000057 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_VIDMEM_REQ 0x00000058 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_L2BYPASS_REQ 0x00000059 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_REQ_NO_CL 0x0000005A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_REQ_CL_NO_GNT 0x0000005B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_REQ_HOL_BLOCKED 0x0000005C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_REQ_RT_BLOCKED 0x0000005D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_REQ_FAM_BLOCKED 0x0000005E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_REQ_CACHEOP_BLOCKED 0x0000005F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_RBUF_FULL 0x00000060 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_MMU_PENDING 0x00000061 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_WDAT_BUFFER_FULL 0x00000062 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_REQ_GNT 0x00000063 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_WR_GRANT 0x00000064 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_RD_GRANT 0x00000065 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_FL_GRANT 0x00000066 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_RD_OUTSTANDING 0x00000067 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_SYSMEM_RD_OUTSTANDING 0x00000068 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_CACHE_REQ 0x00000069 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_NCACHE_REQ 0x0000006A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_VIDMEM_REQ 0x0000006B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_L2BYPASS_REQ 0x0000006C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_REQ_NO_CL 0x0000006D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_REQ_CL_NO_GNT 0x0000006E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_REQ_HOL_BLOCKED 0x0000006F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_REQ_RT_BLOCKED 0x00000070 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_REQ_FAM_BLOCKED 0x00000071 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_REQ_CACHEOP_BLOCKED 0x00000072 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_RBUF_FULL 0x00000073 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_MMU_PENDING 0x00000074 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_WDAT_BUFFER_FULL 0x00000075 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_REQ_GNT 0x00000076 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_WR_GRANT 0x00000077 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_RD_GRANT 0x00000078 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_FL_GRANT 0x00000079 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_RD_OUTSTANDING 0x0000007A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_CPU_NB_SYSMEM_RD_OUTSTANDING 0x0000007B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_CACHE_REQ 0x0000007C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_NCACHE_REQ 0x0000007D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_VIDMEM_REQ 0x0000007E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_L2BYPASS_REQ 0x0000007F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_REQ_NO_CL 0x00000080 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_REQ_CL_NO_GNT 0x00000081 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_REQ_HOL_BLOCKED 0x00000082 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_REQ_RT_BLOCKED 0x00000083 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_REQ_FAM_BLOCKED 0x00000084 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_REQ_CACHEOP_BLOCKED 0x00000085 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_RBUF_FULL 0x00000086 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_MMU_PENDING 0x00000087 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_WDAT_BUFFER_FULL 0x00000088 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_REQ_GNT 0x00000089 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_WR_GRANT 0x0000008A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_RD_GRANT 0x0000008B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_FL_GRANT 0x0000008C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_RD_OUTSTANDING 0x0000008D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC0_SYSMEM_RD_OUTSTANDING 0x0000008E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_CACHE_REQ 0x0000008F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_NCACHE_REQ 0x00000090 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_VIDMEM_REQ 0x00000091 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_L2BYPASS_REQ 0x00000092 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_REQ_NO_CL 0x00000093 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_REQ_CL_NO_GNT 0x00000094 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_REQ_HOL_BLOCKED 0x00000095 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_REQ_RT_BLOCKED 0x00000096 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_REQ_FAM_BLOCKED 0x00000097 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_REQ_CACHEOP_BLOCKED 0x00000098 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_RBUF_FULL 0x00000099 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_MMU_PENDING 0x0000009A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_WDAT_BUFFER_FULL 0x0000009B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_REQ_GNT 0x0000009C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_WR_GRANT 0x0000009D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_RD_GRANT 0x0000009E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_FL_GRANT 0x0000009F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_RD_OUTSTANDING 0x000000A0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC1_SYSMEM_RD_OUTSTANDING 0x000000A1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_CACHE_REQ 0x000000A2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_NCACHE_REQ 0x000000A3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_VIDMEM_REQ 0x000000A4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_L2BYPASS_REQ 0x000000A5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_REQ_NO_CL 0x000000A6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_REQ_CL_NO_GNT 0x000000A7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_REQ_HOL_BLOCKED 0x000000A8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_REQ_RT_BLOCKED 0x000000A9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_REQ_FAM_BLOCKED 0x000000AA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_REQ_CACHEOP_BLOCKED 0x000000AB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_RBUF_FULL 0x000000AC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_MMU_PENDING 0x000000AD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_WDAT_BUFFER_FULL 0x000000AE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_REQ_GNT 0x000000AF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_WR_GRANT 0x000000B0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_RD_GRANT 0x000000B1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_FL_GRANT 0x000000B2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_RD_OUTSTANDING 0x000000B3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC2_SYSMEM_RD_OUTSTANDING 0x000000B4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_CACHE_REQ 0x000000B5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_NCACHE_REQ 0x000000B6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_VIDMEM_REQ 0x000000B7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_L2BYPASS_REQ 0x000000B8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_REQ_NO_CL 0x000000B9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_REQ_CL_NO_GNT 0x000000BA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_REQ_HOL_BLOCKED 0x000000BB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_REQ_RT_BLOCKED 0x000000BC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_REQ_FAM_BLOCKED 0x000000BD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_REQ_CACHEOP_BLOCKED 0x000000BE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_RBUF_FULL 0x000000BF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_MMU_PENDING 0x000000C0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_WDAT_BUFFER_FULL 0x000000C1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_REQ_GNT 0x000000C2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_WR_GRANT 0x000000C3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_RD_GRANT 0x000000C4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_FL_GRANT 0x000000C5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_RD_OUTSTANDING 0x000000C6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC3_SYSMEM_RD_OUTSTANDING 0x000000C7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_CACHE_REQ 0x000000C8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_NCACHE_REQ 0x000000C9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_VIDMEM_REQ 0x000000CA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_L2BYPASS_REQ 0x000000CB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_REQ_NO_CL 0x000000CC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_REQ_CL_NO_GNT 0x000000CD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_REQ_HOL_BLOCKED 0x000000CE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_REQ_RT_BLOCKED 0x000000CF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_REQ_FAM_BLOCKED 0x000000D0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_REQ_CACHEOP_BLOCKED 0x000000D1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_RBUF_FULL 0x000000D2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_MMU_PENDING 0x000000D3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_WDAT_BUFFER_FULL 0x000000D4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_REQ_GNT 0x000000D5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_WR_GRANT 0x000000D6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_RD_GRANT 0x000000D7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_FL_GRANT 0x000000D8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_RD_OUTSTANDING 0x000000D9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC4_SYSMEM_RD_OUTSTANDING 0x000000DA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_CACHE_REQ 0x000000DB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_NCACHE_REQ 0x000000DC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_VIDMEM_REQ 0x000000DD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_L2BYPASS_REQ 0x000000DE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_REQ_NO_CL 0x000000DF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_REQ_CL_NO_GNT 0x000000E0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_REQ_HOL_BLOCKED 0x000000E1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_REQ_RT_BLOCKED 0x000000E2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_REQ_FAM_BLOCKED 0x000000E3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_REQ_CACHEOP_BLOCKED 0x000000E4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_RBUF_FULL 0x000000E5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_MMU_PENDING 0x000000E6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_WDAT_BUFFER_FULL 0x000000E7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_REQ_GNT 0x000000E8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_WR_GRANT 0x000000E9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_RD_GRANT 0x000000EA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_FL_GRANT 0x000000EB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_RD_OUTSTANDING 0x000000EC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC5_SYSMEM_RD_OUTSTANDING 0x000000ED /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_CACHE_REQ 0x000000EE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_NCACHE_REQ 0x000000EF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_VIDMEM_REQ 0x000000F0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_L2BYPASS_REQ 0x000000F1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_REQ_NO_CL 0x000000F2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_REQ_CL_NO_GNT 0x000000F3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_REQ_HOL_BLOCKED 0x000000F4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_REQ_RT_BLOCKED 0x000000F5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_REQ_FAM_BLOCKED 0x000000F6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_REQ_CACHEOP_BLOCKED 0x000000F7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_RBUF_FULL 0x000000F8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_MMU_PENDING 0x000000F9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_WDAT_BUFFER_FULL 0x000000FA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_REQ_GNT 0x000000FB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_WR_GRANT 0x000000FC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_RD_GRANT 0x000000FD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_FL_GRANT 0x000000FE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_RD_OUTSTANDING 0x000000FF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC6_SYSMEM_RD_OUTSTANDING 0x00000100 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_CACHE_REQ 0x00000101 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_NCACHE_REQ 0x00000102 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_VIDMEM_REQ 0x00000103 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_L2BYPASS_REQ 0x00000104 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_REQ_NO_CL 0x00000105 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_REQ_CL_NO_GNT 0x00000106 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_REQ_HOL_BLOCKED 0x00000107 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_REQ_RT_BLOCKED 0x00000108 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_REQ_FAM_BLOCKED 0x00000109 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_REQ_CACHEOP_BLOCKED 0x0000010A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_RBUF_FULL 0x0000010B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_MMU_PENDING 0x0000010C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_WDAT_BUFFER_FULL 0x0000010D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_REQ_GNT 0x0000010E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_WR_GRANT 0x0000010F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_RD_GRANT 0x00000110 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_FL_GRANT 0x00000111 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_RD_OUTSTANDING 0x00000112 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC7_SYSMEM_RD_OUTSTANDING 0x00000113 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_CACHE_REQ 0x00000114 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_NCACHE_REQ 0x00000115 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_VIDMEM_REQ 0x00000116 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_L2BYPASS_REQ 0x00000117 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_REQ_NO_CL 0x00000118 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_REQ_CL_NO_GNT 0x00000119 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_REQ_HOL_BLOCKED 0x0000011A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_REQ_RT_BLOCKED 0x0000011B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_REQ_FAM_BLOCKED 0x0000011C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_REQ_CACHEOP_BLOCKED 0x0000011D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_RBUF_FULL 0x0000011E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_MMU_PENDING 0x0000011F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_WDAT_BUFFER_FULL 0x00000120 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_REQ_GNT 0x00000121 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_WR_GRANT 0x00000122 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_RD_GRANT 0x00000123 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_FL_GRANT 0x00000124 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_RD_OUTSTANDING 0x00000125 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC8_SYSMEM_RD_OUTSTANDING 0x00000126 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_CACHE_REQ 0x00000127 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_NCACHE_REQ 0x00000128 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_VIDMEM_REQ 0x00000129 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_L2BYPASS_REQ 0x0000012A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_REQ_NO_CL 0x0000012B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_REQ_CL_NO_GNT 0x0000012C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_REQ_HOL_BLOCKED 0x0000012D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_REQ_RT_BLOCKED 0x0000012E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_REQ_FAM_BLOCKED 0x0000012F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_REQ_CACHEOP_BLOCKED 0x00000130 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_RBUF_FULL 0x00000131 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_MMU_PENDING 0x00000132 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_WDAT_BUFFER_FULL 0x00000133 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_REQ_GNT 0x00000134 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_WR_GRANT 0x00000135 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_RD_GRANT 0x00000136 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_FL_GRANT 0x00000137 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_RD_OUTSTANDING 0x00000138 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC9_SYSMEM_RD_OUTSTANDING 0x00000139 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_CACHE_REQ 0x0000013A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_NCACHE_REQ 0x0000013B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_VIDMEM_REQ 0x0000013C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_L2BYPASS_REQ 0x0000013D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_REQ_NO_CL 0x0000013E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_REQ_CL_NO_GNT 0x0000013F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_REQ_HOL_BLOCKED 0x00000140 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_REQ_RT_BLOCKED 0x00000141 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_REQ_FAM_BLOCKED 0x00000142 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_REQ_CACHEOP_BLOCKED 0x00000143 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_RBUF_FULL 0x00000144 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_MMU_PENDING 0x00000145 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_WDAT_BUFFER_FULL 0x00000146 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_REQ_GNT 0x00000147 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_WR_GRANT 0x00000148 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_RD_GRANT 0x00000149 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_FL_GRANT 0x0000014A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_RD_OUTSTANDING 0x0000014B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC10_SYSMEM_RD_OUTSTANDING 0x0000014C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_CACHE_REQ 0x0000014D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_NCACHE_REQ 0x0000014E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_VIDMEM_REQ 0x0000014F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_L2BYPASS_REQ 0x00000150 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_REQ_NO_CL 0x00000151 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_REQ_CL_NO_GNT 0x00000152 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_REQ_HOL_BLOCKED 0x00000153 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_REQ_RT_BLOCKED 0x00000154 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_REQ_FAM_BLOCKED 0x00000155 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_REQ_CACHEOP_BLOCKED 0x00000156 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_RBUF_FULL 0x00000157 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_MMU_PENDING 0x00000158 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_WDAT_BUFFER_FULL 0x00000159 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_REQ_GNT 0x0000015A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_WR_GRANT 0x0000015B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_RD_GRANT 0x0000015C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_FL_GRANT 0x0000015D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_RD_OUTSTANDING 0x0000015E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ESC11_SYSMEM_RD_OUTSTANDING 0x0000015F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_CACHE_REQ 0x00000160 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_NCACHE_REQ 0x00000161 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_VIDMEM_REQ 0x00000162 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_L2BYPASS_REQ 0x00000163 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_REQ_NO_CL 0x00000164 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_REQ_CL_NO_GNT 0x00000165 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_REQ_HOL_BLOCKED 0x00000166 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_REQ_RT_BLOCKED 0x00000167 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_REQ_FAM_BLOCKED 0x00000168 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_REQ_CACHEOP_BLOCKED 0x00000169 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_RBUF_FULL 0x0000016A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_MMU_PENDING 0x0000016B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_WDAT_BUFFER_FULL 0x0000016C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_REQ_GNT 0x0000016D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_WR_GRANT 0x0000016E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_RD_GRANT 0x0000016F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_FL_GRANT 0x00000170 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_RD_OUTSTANDING 0x00000171 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_P2P_SYSMEM_RD_OUTSTANDING 0x00000172 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_CACHE_REQ 0x00000173 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NCACHE_REQ 0x00000174 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_VIDMEM_REQ 0x00000175 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_L2BYPASS_REQ 0x00000176 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_REQ_NO_CL 0x00000177 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_REQ_CL_NO_GNT 0x00000178 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_REQ_HOL_BLOCKED 0x00000179 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_REQ_RT_BLOCKED 0x0000017A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_REQ_FAM_BLOCKED 0x0000017B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_REQ_CACHEOP_BLOCKED 0x0000017C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_RBUF_FULL 0x0000017D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_MMU_PENDING 0x0000017E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_WDAT_BUFFER_FULL 0x0000017F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_REQ_GNT 0x00000180 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_WR_GRANT 0x00000181 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_RD_GRANT 0x00000182 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_FL_GRANT 0x00000183 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_RD_OUTSTANDING 0x00000184 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_SYSMEM_RD_OUTSTANDING 0x00000185 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_CACHE_REQ 0x00000186 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_NCACHE_REQ 0x00000187 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_VIDMEM_REQ 0x00000188 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_L2BYPASS_REQ 0x00000189 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_REQ_NO_CL 0x0000018A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_REQ_CL_NO_GNT 0x0000018B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_REQ_HOL_BLOCKED 0x0000018C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_REQ_RT_BLOCKED 0x0000018D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_REQ_FAM_BLOCKED 0x0000018E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_REQ_CACHEOP_BLOCKED 0x0000018F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_RBUF_FULL 0x00000190 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_MMU_PENDING 0x00000191 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_WDAT_BUFFER_FULL 0x00000192 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_REQ_GNT 0x00000193 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_WR_GRANT 0x00000194 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_RD_GRANT 0x00000195 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_FL_GRANT 0x00000196 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_RD_OUTSTANDING 0x00000197 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_MMU_NB_SYSMEM_RD_OUTSTANDING 0x00000198 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_CACHE_REQ 0x00000199 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_NCACHE_REQ 0x0000019A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_VIDMEM_REQ 0x0000019B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_L2BYPASS_REQ 0x0000019C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_NO_CL 0x0000019D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_CL_NO_GNT 0x0000019E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_HOL_BLOCKED 0x0000019F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_RT_BLOCKED 0x000001A0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_FAM_BLOCKED 0x000001A1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_CACHEOP_BLOCKED 0x000001A2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_RBUF_FULL 0x000001A3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_MMU_PENDING 0x000001A4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_WDAT_BUFFER_FULL 0x000001A5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_GNT 0x000001A6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_WR_GRANT 0x000001A7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_RD_GRANT 0x000001A8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_FL_GRANT 0x000001A9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_RD_OUTSTANDING 0x000001AA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_SYSMEM_RD_OUTSTANDING 0x000001AB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_CACHE_REQ 0x000001AC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_NCACHE_REQ 0x000001AD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_VIDMEM_REQ 0x000001AE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_L2BYPASS_REQ 0x000001AF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_NO_CL 0x000001B0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_CL_NO_GNT 0x000001B1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_HOL_BLOCKED 0x000001B2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_RT_BLOCKED 0x000001B3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_FAM_BLOCKED 0x000001B4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_CACHEOP_BLOCKED 0x000001B5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_RBUF_FULL 0x000001B6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_MMU_PENDING 0x000001B7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_WDAT_BUFFER_FULL 0x000001B8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_GNT 0x000001B9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_WR_GRANT 0x000001BA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_RD_GRANT 0x000001BB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_FL_GRANT 0x000001BC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_RD_OUTSTANDING 0x000001BD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_SYSMEM_RD_OUTSTANDING 0x000001BE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_CACHE_REQ 0x000001BF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_NCACHE_REQ 0x000001C0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_VIDMEM_REQ 0x000001C1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_L2BYPASS_REQ 0x000001C2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_NO_CL 0x000001C3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_CL_NO_GNT 0x000001C4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_HOL_BLOCKED 0x000001C5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_RT_BLOCKED 0x000001C6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_FAM_BLOCKED 0x000001C7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_CACHEOP_BLOCKED 0x000001C8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_RBUF_FULL 0x000001C9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_MMU_PENDING 0x000001CA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_WDAT_BUFFER_FULL 0x000001CB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_GNT 0x000001CC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_WR_GRANT 0x000001CD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_RD_GRANT 0x000001CE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_FL_GRANT 0x000001CF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_RD_OUTSTANDING 0x000001D0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_SYSMEM_RD_OUTSTANDING 0x000001D1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_CACHE_REQ 0x000001D2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_NCACHE_REQ 0x000001D3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_VIDMEM_REQ 0x000001D4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_L2BYPASS_REQ 0x000001D5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_REQ_NO_CL 0x000001D6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_REQ_CL_NO_GNT 0x000001D7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_REQ_HOL_BLOCKED 0x000001D8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_REQ_RT_BLOCKED 0x000001D9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_REQ_FAM_BLOCKED 0x000001DA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_REQ_CACHEOP_BLOCKED 0x000001DB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_RBUF_FULL 0x000001DC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_MMU_PENDING 0x000001DD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_WDAT_BUFFER_FULL 0x000001DE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_REQ_GNT 0x000001DF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_WR_GRANT 0x000001E0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_RD_GRANT 0x000001E1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_FL_GRANT 0x000001E2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_RD_OUTSTANDING 0x000001E3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE_SHIM_SYSMEM_RD_OUTSTANDING 0x000001E4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_CACHE_REQ 0x000001E5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_NCACHE_REQ 0x000001E6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_VIDMEM_REQ 0x000001E7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_L2BYPASS_REQ 0x000001E8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_NO_CL 0x000001E9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_CL_NO_GNT 0x000001EA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_HOL_BLOCKED 0x000001EB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_RT_BLOCKED 0x000001EC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_FAM_BLOCKED 0x000001ED /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_CACHEOP_BLOCKED 0x000001EE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_RBUF_FULL 0x000001EF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_MMU_PENDING 0x000001F0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_WDAT_BUFFER_FULL 0x000001F1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_GNT 0x000001F2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_WR_GRANT 0x000001F3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_RD_GRANT 0x000001F4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_FL_GRANT 0x000001F5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_RD_OUTSTANDING 0x000001F6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_SYSMEM_RD_OUTSTANDING 0x000001F7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_CACHE_REQ 0x000001F8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_NCACHE_REQ 0x000001F9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_VIDMEM_REQ 0x000001FA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_L2BYPASS_REQ 0x000001FB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_NO_CL 0x000001FC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_CL_NO_GNT 0x000001FD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_HOL_BLOCKED 0x000001FE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_RT_BLOCKED 0x000001FF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_FAM_BLOCKED 0x00000200 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_CACHEOP_BLOCKED 0x00000201 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_RBUF_FULL 0x00000202 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_MMU_PENDING 0x00000203 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_WDAT_BUFFER_FULL 0x00000204 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_GNT 0x00000205 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_WR_GRANT 0x00000206 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_RD_GRANT 0x00000207 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_FL_GRANT 0x00000208 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_RD_OUTSTANDING 0x00000209 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_SYSMEM_RD_OUTSTANDING 0x0000020A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_CACHE_REQ 0x0000020B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_NCACHE_REQ 0x0000020C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_VIDMEM_REQ 0x0000020D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_L2BYPASS_REQ 0x0000020E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_NO_CL 0x0000020F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_CL_NO_GNT 0x00000210 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_HOL_BLOCKED 0x00000211 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_RT_BLOCKED 0x00000212 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_FAM_BLOCKED 0x00000213 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_CACHEOP_BLOCKED 0x00000214 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_RBUF_FULL 0x00000215 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_MMU_PENDING 0x00000216 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_WDAT_BUFFER_FULL 0x00000217 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_GNT 0x00000218 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_WR_GRANT 0x00000219 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_RD_GRANT 0x0000021A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_FL_GRANT 0x0000021B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_RD_OUTSTANDING 0x0000021C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_SYSMEM_RD_OUTSTANDING 0x0000021D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_CACHE_REQ 0x0000021E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_NCACHE_REQ 0x0000021F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_VIDMEM_REQ 0x00000220 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_L2BYPASS_REQ 0x00000221 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_NO_CL 0x00000222 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_CL_NO_GNT 0x00000223 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_HOL_BLOCKED 0x00000224 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_RT_BLOCKED 0x00000225 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_FAM_BLOCKED 0x00000226 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_CACHEOP_BLOCKED 0x00000227 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_RBUF_FULL 0x00000228 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_MMU_PENDING 0x00000229 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_WDAT_BUFFER_FULL 0x0000022A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_GNT 0x0000022B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_WR_GRANT 0x0000022C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_RD_GRANT 0x0000022D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_FL_GRANT 0x0000022E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_RD_OUTSTANDING 0x0000022F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_SYSMEM_RD_OUTSTANDING 0x00000230 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_CACHE_REQ 0x00000231 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_NCACHE_REQ 0x00000232 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_VIDMEM_REQ 0x00000233 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_L2BYPASS_REQ 0x00000234 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_NO_CL 0x00000235 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_CL_NO_GNT 0x00000236 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_HOL_BLOCKED 0x00000237 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_RT_BLOCKED 0x00000238 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_FAM_BLOCKED 0x00000239 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_CACHEOP_BLOCKED 0x0000023A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_RBUF_FULL 0x0000023B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_MMU_PENDING 0x0000023C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_WDAT_BUFFER_FULL 0x0000023D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_GNT 0x0000023E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_WR_GRANT 0x0000023F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_RD_GRANT 0x00000240 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_FL_GRANT 0x00000241 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_RD_OUTSTANDING 0x00000242 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_SYSMEM_RD_OUTSTANDING 0x00000243 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_CACHE_REQ 0x00000244 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_NCACHE_REQ 0x00000245 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_VIDMEM_REQ 0x00000246 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_L2BYPASS_REQ 0x00000247 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_NO_CL 0x00000248 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_CL_NO_GNT 0x00000249 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_HOL_BLOCKED 0x0000024A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_RT_BLOCKED 0x0000024B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_FAM_BLOCKED 0x0000024C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_CACHEOP_BLOCKED 0x0000024D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_RBUF_FULL 0x0000024E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_MMU_PENDING 0x0000024F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_WDAT_BUFFER_FULL 0x00000250 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_GNT 0x00000251 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_WR_GRANT 0x00000252 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_RD_GRANT 0x00000253 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_FL_GRANT 0x00000254 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_RD_OUTSTANDING 0x00000255 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_SYSMEM_RD_OUTSTANDING 0x00000256 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_CACHE_REQ 0x00000257 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_NCACHE_REQ 0x00000258 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_VIDMEM_REQ 0x00000259 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_L2BYPASS_REQ 0x0000025A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_NO_CL 0x0000025B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_CL_NO_GNT 0x0000025C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_HOL_BLOCKED 0x0000025D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_RT_BLOCKED 0x0000025E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_FAM_BLOCKED 0x0000025F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_CACHEOP_BLOCKED 0x00000260 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_RBUF_FULL 0x00000261 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_MMU_PENDING 0x00000262 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_WDAT_BUFFER_FULL 0x00000263 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_GNT 0x00000264 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_WR_GRANT 0x00000265 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_RD_GRANT 0x00000266 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_FL_GRANT 0x00000267 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_RD_OUTSTANDING 0x00000268 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_SYSMEM_RD_OUTSTANDING 0x00000269 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_CACHE_REQ 0x0000026A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_NCACHE_REQ 0x0000026B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_VIDMEM_REQ 0x0000026C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_L2BYPASS_REQ 0x0000026D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_NO_CL 0x0000026E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_CL_NO_GNT 0x0000026F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_HOL_BLOCKED 0x00000270 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_RT_BLOCKED 0x00000271 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_FAM_BLOCKED 0x00000272 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_CACHEOP_BLOCKED 0x00000273 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_RBUF_FULL 0x00000274 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_MMU_PENDING 0x00000275 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_WDAT_BUFFER_FULL 0x00000276 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_GNT 0x00000277 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_WR_GRANT 0x00000278 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_RD_GRANT 0x00000279 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_FL_GRANT 0x0000027A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_RD_OUTSTANDING 0x0000027B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_SYSMEM_RD_OUTSTANDING 0x0000027C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_CACHE_REQ 0x0000027D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_NCACHE_REQ 0x0000027E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_VIDMEM_REQ 0x0000027F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_L2BYPASS_REQ 0x00000280 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_NO_CL 0x00000281 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_CL_NO_GNT 0x00000282 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_HOL_BLOCKED 0x00000283 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_RT_BLOCKED 0x00000284 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_FAM_BLOCKED 0x00000285 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_CACHEOP_BLOCKED 0x00000286 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_RBUF_FULL 0x00000287 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_MMU_PENDING 0x00000288 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_WDAT_BUFFER_FULL 0x00000289 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_GNT 0x0000028A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_WR_GRANT 0x0000028B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_RD_GRANT 0x0000028C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_FL_GRANT 0x0000028D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_RD_OUTSTANDING 0x0000028E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_SYSMEM_RD_OUTSTANDING 0x0000028F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_CACHE_REQ 0x00000290 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_NCACHE_REQ 0x00000291 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_VIDMEM_REQ 0x00000292 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_L2BYPASS_REQ 0x00000293 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_REQ_NO_CL 0x00000294 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_REQ_CL_NO_GNT 0x00000295 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_REQ_HOL_BLOCKED 0x00000296 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_REQ_RT_BLOCKED 0x00000297 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_REQ_FAM_BLOCKED 0x00000298 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_REQ_CACHEOP_BLOCKED 0x00000299 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_RBUF_FULL 0x0000029A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_MMU_PENDING 0x0000029B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_WDAT_BUFFER_FULL 0x0000029C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_REQ_GNT 0x0000029D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_WR_GRANT 0x0000029E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_RD_GRANT 0x0000029F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_FL_GRANT 0x000002A0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_RD_OUTSTANDING 0x000002A1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED_SYSMEM_RD_OUTSTANDING 0x000002A2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_CACHE_REQ 0x000002A3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_NCACHE_REQ 0x000002A4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_VIDMEM_REQ 0x000002A5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_L2BYPASS_REQ 0x000002A6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_REQ_NO_CL 0x000002A7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_REQ_CL_NO_GNT 0x000002A8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_REQ_HOL_BLOCKED 0x000002A9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_REQ_RT_BLOCKED 0x000002AA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_REQ_FAM_BLOCKED 0x000002AB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_REQ_CACHEOP_BLOCKED 0x000002AC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_RBUF_FULL 0x000002AD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_MMU_PENDING 0x000002AE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_WDAT_BUFFER_FULL 0x000002AF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_REQ_GNT 0x000002B0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_WR_GRANT 0x000002B1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_RD_GRANT 0x000002B2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_FL_GRANT 0x000002B3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_RD_OUTSTANDING 0x000002B4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED0_SYSMEM_RD_OUTSTANDING 0x000002B5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_CACHE_REQ 0x000002B6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_NCACHE_REQ 0x000002B7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_VIDMEM_REQ 0x000002B8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_L2BYPASS_REQ 0x000002B9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_REQ_NO_CL 0x000002BA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_REQ_CL_NO_GNT 0x000002BB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_REQ_HOL_BLOCKED 0x000002BC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_REQ_RT_BLOCKED 0x000002BD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_REQ_FAM_BLOCKED 0x000002BE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_REQ_CACHEOP_BLOCKED 0x000002BF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_RBUF_FULL 0x000002C0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_MMU_PENDING 0x000002C1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_WDAT_BUFFER_FULL 0x000002C2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_REQ_GNT 0x000002C3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_WR_GRANT 0x000002C4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_RD_GRANT 0x000002C5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_FL_GRANT 0x000002C6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_RD_OUTSTANDING 0x000002C7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED1_SYSMEM_RD_OUTSTANDING 0x000002C8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_CACHE_REQ 0x000002C9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_NCACHE_REQ 0x000002CA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_VIDMEM_REQ 0x000002CB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_L2BYPASS_REQ 0x000002CC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_REQ_NO_CL 0x000002CD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_REQ_CL_NO_GNT 0x000002CE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_REQ_HOL_BLOCKED 0x000002CF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_REQ_RT_BLOCKED 0x000002D0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_REQ_FAM_BLOCKED 0x000002D1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_REQ_CACHEOP_BLOCKED 0x000002D2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_RBUF_FULL 0x000002D3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_MMU_PENDING 0x000002D4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_WDAT_BUFFER_FULL 0x000002D5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_REQ_GNT 0x000002D6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_WR_GRANT 0x000002D7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_RD_GRANT 0x000002D8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_FL_GRANT 0x000002D9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_RD_OUTSTANDING 0x000002DA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED2_SYSMEM_RD_OUTSTANDING 0x000002DB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_CACHE_REQ 0x000002DC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_NCACHE_REQ 0x000002DD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_VIDMEM_REQ 0x000002DE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_L2BYPASS_REQ 0x000002DF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_REQ_NO_CL 0x000002E0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_REQ_CL_NO_GNT 0x000002E1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_REQ_HOL_BLOCKED 0x000002E2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_REQ_RT_BLOCKED 0x000002E3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_REQ_FAM_BLOCKED 0x000002E4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_REQ_CACHEOP_BLOCKED 0x000002E5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_RBUF_FULL 0x000002E6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_MMU_PENDING 0x000002E7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_WDAT_BUFFER_FULL 0x000002E8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_REQ_GNT 0x000002E9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_WR_GRANT 0x000002EA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_RD_GRANT 0x000002EB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_FL_GRANT 0x000002EC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_RD_OUTSTANDING 0x000002ED /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED3_SYSMEM_RD_OUTSTANDING 0x000002EE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_CACHE_REQ 0x000002EF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_NCACHE_REQ 0x000002F0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_VIDMEM_REQ 0x000002F1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_L2BYPASS_REQ 0x000002F2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_REQ_NO_CL 0x000002F3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_REQ_CL_NO_GNT 0x000002F4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_REQ_HOL_BLOCKED 0x000002F5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_REQ_RT_BLOCKED 0x000002F6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_REQ_FAM_BLOCKED 0x000002F7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_REQ_CACHEOP_BLOCKED 0x000002F8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_RBUF_FULL 0x000002F9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_MMU_PENDING 0x000002FA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_WDAT_BUFFER_FULL 0x000002FB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_REQ_GNT 0x000002FC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_WR_GRANT 0x000002FD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_RD_GRANT 0x000002FE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_FL_GRANT 0x000002FF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_RD_OUTSTANDING 0x00000300 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED4_SYSMEM_RD_OUTSTANDING 0x00000301 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_CACHE_REQ 0x00000302 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_NCACHE_REQ 0x00000303 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_VIDMEM_REQ 0x00000304 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_L2BYPASS_REQ 0x00000305 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_REQ_NO_CL 0x00000306 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_REQ_CL_NO_GNT 0x00000307 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_REQ_HOL_BLOCKED 0x00000308 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_REQ_RT_BLOCKED 0x00000309 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_REQ_FAM_BLOCKED 0x0000030A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_REQ_CACHEOP_BLOCKED 0x0000030B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_RBUF_FULL 0x0000030C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_MMU_PENDING 0x0000030D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_WDAT_BUFFER_FULL 0x0000030E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_REQ_GNT 0x0000030F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_WR_GRANT 0x00000310 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_RD_GRANT 0x00000311 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_FL_GRANT 0x00000312 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_RD_OUTSTANDING 0x00000313 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED5_SYSMEM_RD_OUTSTANDING 0x00000314 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_CACHE_REQ 0x00000315 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_NCACHE_REQ 0x00000316 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_VIDMEM_REQ 0x00000317 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_L2BYPASS_REQ 0x00000318 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_REQ_NO_CL 0x00000319 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_REQ_CL_NO_GNT 0x0000031A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_REQ_HOL_BLOCKED 0x0000031B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_REQ_RT_BLOCKED 0x0000031C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_REQ_FAM_BLOCKED 0x0000031D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_REQ_CACHEOP_BLOCKED 0x0000031E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_RBUF_FULL 0x0000031F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_MMU_PENDING 0x00000320 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_WDAT_BUFFER_FULL 0x00000321 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_REQ_GNT 0x00000322 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_WR_GRANT 0x00000323 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_RD_GRANT 0x00000324 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_FL_GRANT 0x00000325 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_RD_OUTSTANDING 0x00000326 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED6_SYSMEM_RD_OUTSTANDING 0x00000327 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_CACHE_REQ 0x00000328 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_NCACHE_REQ 0x00000329 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_VIDMEM_REQ 0x0000032A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_L2BYPASS_REQ 0x0000032B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_REQ_NO_CL 0x0000032C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_REQ_CL_NO_GNT 0x0000032D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_REQ_HOL_BLOCKED 0x0000032E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_REQ_RT_BLOCKED 0x0000032F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_REQ_FAM_BLOCKED 0x00000330 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_REQ_CACHEOP_BLOCKED 0x00000331 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_RBUF_FULL 0x00000332 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_MMU_PENDING 0x00000333 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_WDAT_BUFFER_FULL 0x00000334 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_REQ_GNT 0x00000335 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_WR_GRANT 0x00000336 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_RD_GRANT 0x00000337 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_FL_GRANT 0x00000338 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_RD_OUTSTANDING 0x00000339 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SKED7_SYSMEM_RD_OUTSTANDING 0x0000033A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_CACHE_REQ 0x0000033B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NCACHE_REQ 0x0000033C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_VIDMEM_REQ 0x0000033D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_L2BYPASS_REQ 0x0000033E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_REQ_NO_CL 0x0000033F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_REQ_CL_NO_GNT 0x00000340 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_REQ_HOL_BLOCKED 0x00000341 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_REQ_RT_BLOCKED 0x00000342 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_REQ_FAM_BLOCKED 0x00000343 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_REQ_CACHEOP_BLOCKED 0x00000344 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_RBUF_FULL 0x00000345 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_MMU_PENDING 0x00000346 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_WDAT_BUFFER_FULL 0x00000347 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_REQ_GNT 0x00000348 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_WR_GRANT 0x00000349 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_RD_GRANT 0x0000034A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_FL_GRANT 0x0000034B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_RD_OUTSTANDING 0x0000034C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_SYSMEM_RD_OUTSTANDING 0x0000034D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_CACHE_REQ 0x0000034E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_NCACHE_REQ 0x0000034F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_VIDMEM_REQ 0x00000350 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_L2BYPASS_REQ 0x00000351 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_REQ_NO_CL 0x00000352 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_REQ_CL_NO_GNT 0x00000353 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_REQ_HOL_BLOCKED 0x00000354 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_REQ_RT_BLOCKED 0x00000355 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_REQ_FAM_BLOCKED 0x00000356 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_REQ_CACHEOP_BLOCKED 0x00000357 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_RBUF_FULL 0x00000358 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_MMU_PENDING 0x00000359 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_WDAT_BUFFER_FULL 0x0000035A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_REQ_GNT 0x0000035B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_WR_GRANT 0x0000035C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_RD_GRANT 0x0000035D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_FL_GRANT 0x0000035E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_RD_OUTSTANDING 0x0000035F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SCC_NB_SYSMEM_RD_OUTSTANDING 0x00000360 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_CACHE_REQ 0x00000361 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_NCACHE_REQ 0x00000362 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_VIDMEM_REQ 0x00000363 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_L2BYPASS_REQ 0x00000364 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_REQ_NO_CL 0x00000365 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_REQ_CL_NO_GNT 0x00000366 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_REQ_HOL_BLOCKED 0x00000367 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_REQ_RT_BLOCKED 0x00000368 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_REQ_FAM_BLOCKED 0x00000369 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_REQ_CACHEOP_BLOCKED 0x0000036A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_RBUF_FULL 0x0000036B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_MMU_PENDING 0x0000036C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_WDAT_BUFFER_FULL 0x0000036D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_REQ_GNT 0x0000036E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_WR_GRANT 0x0000036F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_RD_GRANT 0x00000370 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_FL_GRANT 0x00000371 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_RD_OUTSTANDING 0x00000372 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PD_SYSMEM_RD_OUTSTANDING 0x00000373 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_CACHE_REQ 0x00000374 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_NCACHE_REQ 0x00000375 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_VIDMEM_REQ 0x00000376 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_L2BYPASS_REQ 0x00000377 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_NO_CL 0x00000378 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_CL_NO_GNT 0x00000379 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_HOL_BLOCKED 0x0000037A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_RT_BLOCKED 0x0000037B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_FAM_BLOCKED 0x0000037C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_CACHEOP_BLOCKED 0x0000037D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_RBUF_FULL 0x0000037E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_MMU_PENDING 0x0000037F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_WDAT_BUFFER_FULL 0x00000380 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_GNT 0x00000381 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_WR_GRANT 0x00000382 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_RD_GRANT 0x00000383 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_FL_GRANT 0x00000384 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_RD_OUTSTANDING 0x00000385 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_SYSMEM_RD_OUTSTANDING 0x00000386 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_CACHE_REQ 0x00000387 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_NCACHE_REQ 0x00000388 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_VIDMEM_REQ 0x00000389 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_L2BYPASS_REQ 0x0000038A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_NO_CL 0x0000038B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_CL_NO_GNT 0x0000038C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_HOL_BLOCKED 0x0000038D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_RT_BLOCKED 0x0000038E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_FAM_BLOCKED 0x0000038F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_CACHEOP_BLOCKED 0x00000390 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_RBUF_FULL 0x00000391 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_MMU_PENDING 0x00000392 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_WDAT_BUFFER_FULL 0x00000393 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_GNT 0x00000394 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_WR_GRANT 0x00000395 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_RD_GRANT 0x00000396 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_FL_GRANT 0x00000397 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_RD_OUTSTANDING 0x00000398 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_SYSMEM_RD_OUTSTANDING 0x00000399 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_CACHE_REQ 0x0000039A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_NCACHE_REQ 0x0000039B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_VIDMEM_REQ 0x0000039C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_L2BYPASS_REQ 0x0000039D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_NO_CL 0x0000039E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_CL_NO_GNT 0x0000039F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_HOL_BLOCKED 0x000003A0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_RT_BLOCKED 0x000003A1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_FAM_BLOCKED 0x000003A2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_CACHEOP_BLOCKED 0x000003A3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_RBUF_FULL 0x000003A4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_MMU_PENDING 0x000003A5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_WDAT_BUFFER_FULL 0x000003A6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_GNT 0x000003A7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_WR_GRANT 0x000003A8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_RD_GRANT 0x000003A9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_FL_GRANT 0x000003AA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_RD_OUTSTANDING 0x000003AB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_SYSMEM_RD_OUTSTANDING 0x000003AC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_CACHE_REQ 0x000003AD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_NCACHE_REQ 0x000003AE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_VIDMEM_REQ 0x000003AF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_L2BYPASS_REQ 0x000003B0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_NO_CL 0x000003B1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_CL_NO_GNT 0x000003B2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_HOL_BLOCKED 0x000003B3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_RT_BLOCKED 0x000003B4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_FAM_BLOCKED 0x000003B5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_CACHEOP_BLOCKED 0x000003B6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_RBUF_FULL 0x000003B7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_MMU_PENDING 0x000003B8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_WDAT_BUFFER_FULL 0x000003B9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_GNT 0x000003BA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_WR_GRANT 0x000003BB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_RD_GRANT 0x000003BC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_FL_GRANT 0x000003BD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_RD_OUTSTANDING 0x000003BE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_SYSMEM_RD_OUTSTANDING 0x000003BF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_CACHE_REQ 0x000003C0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_NCACHE_REQ 0x000003C1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_VIDMEM_REQ 0x000003C2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_L2BYPASS_REQ 0x000003C3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_NO_CL 0x000003C4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_CL_NO_GNT 0x000003C5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_HOL_BLOCKED 0x000003C6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_RT_BLOCKED 0x000003C7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_FAM_BLOCKED 0x000003C8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_CACHEOP_BLOCKED 0x000003C9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_RBUF_FULL 0x000003CA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_MMU_PENDING 0x000003CB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_WDAT_BUFFER_FULL 0x000003CC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_GNT 0x000003CD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_WR_GRANT 0x000003CE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_RD_GRANT 0x000003CF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_FL_GRANT 0x000003D0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_RD_OUTSTANDING 0x000003D1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_SYSMEM_RD_OUTSTANDING 0x000003D2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_CACHE_REQ 0x000003D3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_NCACHE_REQ 0x000003D4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_VIDMEM_REQ 0x000003D5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_L2BYPASS_REQ 0x000003D6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_NO_CL 0x000003D7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_CL_NO_GNT 0x000003D8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_HOL_BLOCKED 0x000003D9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_RT_BLOCKED 0x000003DA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_FAM_BLOCKED 0x000003DB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_CACHEOP_BLOCKED 0x000003DC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_RBUF_FULL 0x000003DD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_MMU_PENDING 0x000003DE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_WDAT_BUFFER_FULL 0x000003DF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_GNT 0x000003E0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_WR_GRANT 0x000003E1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_RD_GRANT 0x000003E2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_FL_GRANT 0x000003E3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_RD_OUTSTANDING 0x000003E4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_SYSMEM_RD_OUTSTANDING 0x000003E5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_CACHE_REQ 0x000003E6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_NCACHE_REQ 0x000003E7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_VIDMEM_REQ 0x000003E8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_L2BYPASS_REQ 0x000003E9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_NO_CL 0x000003EA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_CL_NO_GNT 0x000003EB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_HOL_BLOCKED 0x000003EC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_RT_BLOCKED 0x000003ED /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_FAM_BLOCKED 0x000003EE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_CACHEOP_BLOCKED 0x000003EF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_RBUF_FULL 0x000003F0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_MMU_PENDING 0x000003F1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_WDAT_BUFFER_FULL 0x000003F2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_GNT 0x000003F3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_WR_GRANT 0x000003F4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_RD_GRANT 0x000003F5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_FL_GRANT 0x000003F6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_RD_OUTSTANDING 0x000003F7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_SYSMEM_RD_OUTSTANDING 0x000003F8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_CACHE_REQ 0x000003F9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_NCACHE_REQ 0x000003FA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_VIDMEM_REQ 0x000003FB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_L2BYPASS_REQ 0x000003FC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_NO_CL 0x000003FD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_CL_NO_GNT 0x000003FE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_HOL_BLOCKED 0x000003FF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_RT_BLOCKED 0x00000400 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_FAM_BLOCKED 0x00000401 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_CACHEOP_BLOCKED 0x00000402 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_RBUF_FULL 0x00000403 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_MMU_PENDING 0x00000404 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_WDAT_BUFFER_FULL 0x00000405 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_GNT 0x00000406 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_WR_GRANT 0x00000407 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_RD_GRANT 0x00000408 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_FL_GRANT 0x00000409 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_RD_OUTSTANDING 0x0000040A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_SYSMEM_RD_OUTSTANDING 0x0000040B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_CACHE_REQ 0x0000040C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_NCACHE_REQ 0x0000040D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_VIDMEM_REQ 0x0000040E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_L2BYPASS_REQ 0x0000040F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_NO_CL 0x00000410 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_CL_NO_GNT 0x00000411 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_HOL_BLOCKED 0x00000412 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_RT_BLOCKED 0x00000413 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_FAM_BLOCKED 0x00000414 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_CACHEOP_BLOCKED 0x00000415 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_RBUF_FULL 0x00000416 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_MMU_PENDING 0x00000417 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_WDAT_BUFFER_FULL 0x00000418 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_GNT 0x00000419 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_WR_GRANT 0x0000041A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_RD_GRANT 0x0000041B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_FL_GRANT 0x0000041C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_RD_OUTSTANDING 0x0000041D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_SYSMEM_RD_OUTSTANDING 0x0000041E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_CACHE_REQ 0x0000041F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_NCACHE_REQ 0x00000420 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_VIDMEM_REQ 0x00000421 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_L2BYPASS_REQ 0x00000422 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_NO_CL 0x00000423 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_CL_NO_GNT 0x00000424 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_HOL_BLOCKED 0x00000425 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_RT_BLOCKED 0x00000426 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_FAM_BLOCKED 0x00000427 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_CACHEOP_BLOCKED 0x00000428 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_RBUF_FULL 0x00000429 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_MMU_PENDING 0x0000042A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_WDAT_BUFFER_FULL 0x0000042B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_GNT 0x0000042C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_WR_GRANT 0x0000042D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_RD_GRANT 0x0000042E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_FL_GRANT 0x0000042F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_RD_OUTSTANDING 0x00000430 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_SYSMEM_RD_OUTSTANDING 0x00000431 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_CACHE_REQ 0x00000432 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_NCACHE_REQ 0x00000433 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_VIDMEM_REQ 0x00000434 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_L2BYPASS_REQ 0x00000435 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_NO_CL 0x00000436 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_CL_NO_GNT 0x00000437 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_HOL_BLOCKED 0x00000438 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_RT_BLOCKED 0x00000439 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_FAM_BLOCKED 0x0000043A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_CACHEOP_BLOCKED 0x0000043B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_RBUF_FULL 0x0000043C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_MMU_PENDING 0x0000043D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_WDAT_BUFFER_FULL 0x0000043E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_GNT 0x0000043F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_WR_GRANT 0x00000440 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_RD_GRANT 0x00000441 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_FL_GRANT 0x00000442 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_RD_OUTSTANDING 0x00000443 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_SYSMEM_RD_OUTSTANDING 0x00000444 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_CACHE_REQ 0x00000445 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_NCACHE_REQ 0x00000446 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_VIDMEM_REQ 0x00000447 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_L2BYPASS_REQ 0x00000448 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_NO_CL 0x00000449 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_CL_NO_GNT 0x0000044A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_HOL_BLOCKED 0x0000044B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_RT_BLOCKED 0x0000044C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_FAM_BLOCKED 0x0000044D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_CACHEOP_BLOCKED 0x0000044E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_RBUF_FULL 0x0000044F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_MMU_PENDING 0x00000450 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_WDAT_BUFFER_FULL 0x00000451 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_GNT 0x00000452 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_WR_GRANT 0x00000453 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_RD_GRANT 0x00000454 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_FL_GRANT 0x00000455 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_RD_OUTSTANDING 0x00000456 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_SYSMEM_RD_OUTSTANDING 0x00000457 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_CACHE_REQ 0x00000458 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_NCACHE_REQ 0x00000459 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_VIDMEM_REQ 0x0000045A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_L2BYPASS_REQ 0x0000045B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_NO_CL 0x0000045C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_CL_NO_GNT 0x0000045D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_HOL_BLOCKED 0x0000045E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_RT_BLOCKED 0x0000045F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_FAM_BLOCKED 0x00000460 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_CACHEOP_BLOCKED 0x00000461 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_RBUF_FULL 0x00000462 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_MMU_PENDING 0x00000463 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_WDAT_BUFFER_FULL 0x00000464 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_GNT 0x00000465 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_WR_GRANT 0x00000466 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_RD_GRANT 0x00000467 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_FL_GRANT 0x00000468 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_RD_OUTSTANDING 0x00000469 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_SYSMEM_RD_OUTSTANDING 0x0000046A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_CACHE_REQ 0x0000046B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_NCACHE_REQ 0x0000046C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_VIDMEM_REQ 0x0000046D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_L2BYPASS_REQ 0x0000046E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_NO_CL 0x0000046F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_CL_NO_GNT 0x00000470 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_HOL_BLOCKED 0x00000471 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_RT_BLOCKED 0x00000472 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_FAM_BLOCKED 0x00000473 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_CACHEOP_BLOCKED 0x00000474 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_RBUF_FULL 0x00000475 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_MMU_PENDING 0x00000476 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_WDAT_BUFFER_FULL 0x00000477 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_GNT 0x00000478 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_WR_GRANT 0x00000479 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_RD_GRANT 0x0000047A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_FL_GRANT 0x0000047B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_RD_OUTSTANDING 0x0000047C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_SYSMEM_RD_OUTSTANDING 0x0000047D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_CACHE_REQ 0x0000047E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_NCACHE_REQ 0x0000047F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_VIDMEM_REQ 0x00000480 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_L2BYPASS_REQ 0x00000481 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_NO_CL 0x00000482 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_CL_NO_GNT 0x00000483 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_HOL_BLOCKED 0x00000484 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_RT_BLOCKED 0x00000485 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_FAM_BLOCKED 0x00000486 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_CACHEOP_BLOCKED 0x00000487 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_RBUF_FULL 0x00000488 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_MMU_PENDING 0x00000489 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_WDAT_BUFFER_FULL 0x0000048A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_GNT 0x0000048B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_WR_GRANT 0x0000048C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_RD_GRANT 0x0000048D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_FL_GRANT 0x0000048E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_RD_OUTSTANDING 0x0000048F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_SYSMEM_RD_OUTSTANDING 0x00000490 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_CACHE_REQ 0x00000491 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_NCACHE_REQ 0x00000492 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_VIDMEM_REQ 0x00000493 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_L2BYPASS_REQ 0x00000494 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_NO_CL 0x00000495 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_CL_NO_GNT 0x00000496 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_HOL_BLOCKED 0x00000497 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_RT_BLOCKED 0x00000498 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_FAM_BLOCKED 0x00000499 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_CACHEOP_BLOCKED 0x0000049A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_RBUF_FULL 0x0000049B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_MMU_PENDING 0x0000049C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_WDAT_BUFFER_FULL 0x0000049D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_GNT 0x0000049E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_WR_GRANT 0x0000049F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_RD_GRANT 0x000004A0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_FL_GRANT 0x000004A1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_RD_OUTSTANDING 0x000004A2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_SYSMEM_RD_OUTSTANDING 0x000004A3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_CACHE_REQ 0x000004A4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_NCACHE_REQ 0x000004A5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_VIDMEM_REQ 0x000004A6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_L2BYPASS_REQ 0x000004A7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_NO_CL 0x000004A8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_CL_NO_GNT 0x000004A9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_HOL_BLOCKED 0x000004AA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_RT_BLOCKED 0x000004AB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_FAM_BLOCKED 0x000004AC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_CACHEOP_BLOCKED 0x000004AD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_RBUF_FULL 0x000004AE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_MMU_PENDING 0x000004AF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_WDAT_BUFFER_FULL 0x000004B0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_GNT 0x000004B1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_WR_GRANT 0x000004B2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_RD_GRANT 0x000004B3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_FL_GRANT 0x000004B4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_RD_OUTSTANDING 0x000004B5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_SYSMEM_RD_OUTSTANDING 0x000004B6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_CACHE_REQ 0x000004B7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_NCACHE_REQ 0x000004B8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_VIDMEM_REQ 0x000004B9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_L2BYPASS_REQ 0x000004BA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_NO_CL 0x000004BB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_CL_NO_GNT 0x000004BC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_HOL_BLOCKED 0x000004BD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_RT_BLOCKED 0x000004BE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_FAM_BLOCKED 0x000004BF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_CACHEOP_BLOCKED 0x000004C0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_RBUF_FULL 0x000004C1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_MMU_PENDING 0x000004C2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_WDAT_BUFFER_FULL 0x000004C3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_GNT 0x000004C4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_WR_GRANT 0x000004C5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_RD_GRANT 0x000004C6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_FL_GRANT 0x000004C7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_RD_OUTSTANDING 0x000004C8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_SYSMEM_RD_OUTSTANDING 0x000004C9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_CACHE_REQ 0x000004CA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_NCACHE_REQ 0x000004CB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_VIDMEM_REQ 0x000004CC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_L2BYPASS_REQ 0x000004CD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_NO_CL 0x000004CE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_CL_NO_GNT 0x000004CF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_HOL_BLOCKED 0x000004D0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_RT_BLOCKED 0x000004D1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_FAM_BLOCKED 0x000004D2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_CACHEOP_BLOCKED 0x000004D3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_RBUF_FULL 0x000004D4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_MMU_PENDING 0x000004D5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_WDAT_BUFFER_FULL 0x000004D6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_GNT 0x000004D7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_WR_GRANT 0x000004D8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_RD_GRANT 0x000004D9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_FL_GRANT 0x000004DA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_RD_OUTSTANDING 0x000004DB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_SYSMEM_RD_OUTSTANDING 0x000004DC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_CACHE_REQ 0x000004DD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_NCACHE_REQ 0x000004DE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_VIDMEM_REQ 0x000004DF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_L2BYPASS_REQ 0x000004E0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_NO_CL 0x000004E1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_CL_NO_GNT 0x000004E2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_HOL_BLOCKED 0x000004E3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_RT_BLOCKED 0x000004E4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_FAM_BLOCKED 0x000004E5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_CACHEOP_BLOCKED 0x000004E6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_RBUF_FULL 0x000004E7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_MMU_PENDING 0x000004E8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_WDAT_BUFFER_FULL 0x000004E9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_GNT 0x000004EA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_WR_GRANT 0x000004EB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_RD_GRANT 0x000004EC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_FL_GRANT 0x000004ED /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_RD_OUTSTANDING 0x000004EE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_SYSMEM_RD_OUTSTANDING 0x000004EF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_CACHE_REQ 0x000004F0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_NCACHE_REQ 0x000004F1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_VIDMEM_REQ 0x000004F2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_L2BYPASS_REQ 0x000004F3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_REQ_NO_CL 0x000004F4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_REQ_CL_NO_GNT 0x000004F5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_REQ_HOL_BLOCKED 0x000004F6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_REQ_RT_BLOCKED 0x000004F7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_REQ_FAM_BLOCKED 0x000004F8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_REQ_CACHEOP_BLOCKED 0x000004F9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_RBUF_FULL 0x000004FA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_MMU_PENDING 0x000004FB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_WDAT_BUFFER_FULL 0x000004FC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_REQ_GNT 0x000004FD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_WR_GRANT 0x000004FE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_RD_GRANT 0x000004FF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_FL_GRANT 0x00000500 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_RD_OUTSTANDING 0x00000501 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ACTRS_SYSMEM_RD_OUTSTANDING 0x00000502 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_BAR_WR_GRANT 0x00000503 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_HOST_BAR_RD_GRANT 0x00000504 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_SVPR_PI 0x00000505 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_NEEDS_AES 0x00000506 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000507 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000508 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000509 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_RD_REQ_WPRID1_ENCRYPT 0x0000050A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_WR_REQ_WPRID1_ENCRYPT 0x0000050B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_RD_REQ_WPRID2_ENCRYPT 0x0000050C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_WR_REQ_WPRID2_ENCRYPT 0x0000050D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_RD_REQ_WPRID3_ENCRYPT 0x0000050E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE0_WR_REQ_WPRID3_ENCRYPT 0x0000050F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_SVPR_PI 0x00000510 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_NEEDS_AES 0x00000511 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000512 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000513 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000514 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_RD_REQ_WPRID1_ENCRYPT 0x00000515 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_WR_REQ_WPRID1_ENCRYPT 0x00000516 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_RD_REQ_WPRID2_ENCRYPT 0x00000517 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_WR_REQ_WPRID2_ENCRYPT 0x00000518 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_RD_REQ_WPRID3_ENCRYPT 0x00000519 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE1_WR_REQ_WPRID3_ENCRYPT 0x0000051A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_SVPR_PI 0x0000051B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_NEEDS_AES 0x0000051C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_NEEDS_AES_ITER_AES_BUSY 0x0000051D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x0000051E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_REQ_NONEED_AES_GO_THRO_ITER_AES 0x0000051F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_RD_REQ_WPRID1_ENCRYPT 0x00000520 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_WR_REQ_WPRID1_ENCRYPT 0x00000521 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_RD_REQ_WPRID2_ENCRYPT 0x00000522 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_WR_REQ_WPRID2_ENCRYPT 0x00000523 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_RD_REQ_WPRID3_ENCRYPT 0x00000524 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE2_WR_REQ_WPRID3_ENCRYPT 0x00000525 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_SVPR_PI 0x00000526 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_NEEDS_AES 0x00000527 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000528 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000529 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_REQ_NONEED_AES_GO_THRO_ITER_AES 0x0000052A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_RD_REQ_WPRID1_ENCRYPT 0x0000052B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_WR_REQ_WPRID1_ENCRYPT 0x0000052C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_RD_REQ_WPRID2_ENCRYPT 0x0000052D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_WR_REQ_WPRID2_ENCRYPT 0x0000052E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_RD_REQ_WPRID3_ENCRYPT 0x0000052F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE_WR_REQ_WPRID3_ENCRYPT 0x00000530 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_SVPR_PI 0x00000531 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_NEEDS_AES 0x00000532 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000533 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000534 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000535 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_RD_REQ_WPRID1_ENCRYPT 0x00000536 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_WR_REQ_WPRID1_ENCRYPT 0x00000537 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_RD_REQ_WPRID2_ENCRYPT 0x00000538 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_WR_REQ_WPRID2_ENCRYPT 0x00000539 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_RD_REQ_WPRID3_ENCRYPT 0x0000053A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE0_WR_REQ_WPRID3_ENCRYPT 0x0000053B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_SVPR_PI 0x0000053C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_NEEDS_AES 0x0000053D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_NEEDS_AES_ITER_AES_BUSY 0x0000053E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x0000053F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000540 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_RD_REQ_WPRID1_ENCRYPT 0x00000541 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_WR_REQ_WPRID1_ENCRYPT 0x00000542 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_RD_REQ_WPRID2_ENCRYPT 0x00000543 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_WR_REQ_WPRID2_ENCRYPT 0x00000544 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_RD_REQ_WPRID3_ENCRYPT 0x00000545 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE1_WR_REQ_WPRID3_ENCRYPT 0x00000546 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_SVPR_PI 0x00000547 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_NEEDS_AES 0x00000548 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000549 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x0000054A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_REQ_NONEED_AES_GO_THRO_ITER_AES 0x0000054B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_RD_REQ_WPRID1_ENCRYPT 0x0000054C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_WR_REQ_WPRID1_ENCRYPT 0x0000054D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_RD_REQ_WPRID2_ENCRYPT 0x0000054E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_WR_REQ_WPRID2_ENCRYPT 0x0000054F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_RD_REQ_WPRID3_ENCRYPT 0x00000550 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE2_WR_REQ_WPRID3_ENCRYPT 0x00000551 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_SVPR_PI 0x00000552 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_NEEDS_AES 0x00000553 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000554 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000555 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000556 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_RD_REQ_WPRID1_ENCRYPT 0x00000557 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_WR_REQ_WPRID1_ENCRYPT 0x00000558 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_RD_REQ_WPRID2_ENCRYPT 0x00000559 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_WR_REQ_WPRID2_ENCRYPT 0x0000055A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_RD_REQ_WPRID3_ENCRYPT 0x0000055B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE3_WR_REQ_WPRID3_ENCRYPT 0x0000055C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_SVPR_PI 0x0000055D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_NEEDS_AES 0x0000055E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_NEEDS_AES_ITER_AES_BUSY 0x0000055F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000560 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000561 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_RD_REQ_WPRID1_ENCRYPT 0x00000562 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_WR_REQ_WPRID1_ENCRYPT 0x00000563 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_RD_REQ_WPRID2_ENCRYPT 0x00000564 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_WR_REQ_WPRID2_ENCRYPT 0x00000565 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_RD_REQ_WPRID3_ENCRYPT 0x00000566 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE4_WR_REQ_WPRID3_ENCRYPT 0x00000567 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_SVPR_PI 0x00000568 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_NEEDS_AES 0x00000569 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_NEEDS_AES_ITER_AES_BUSY 0x0000056A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x0000056B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_REQ_NONEED_AES_GO_THRO_ITER_AES 0x0000056C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_RD_REQ_WPRID1_ENCRYPT 0x0000056D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_WR_REQ_WPRID1_ENCRYPT 0x0000056E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_RD_REQ_WPRID2_ENCRYPT 0x0000056F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_WR_REQ_WPRID2_ENCRYPT 0x00000570 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_RD_REQ_WPRID3_ENCRYPT 0x00000571 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE5_WR_REQ_WPRID3_ENCRYPT 0x00000572 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_SVPR_PI 0x00000573 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_NEEDS_AES 0x00000574 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000575 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000576 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000577 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_RD_REQ_WPRID1_ENCRYPT 0x00000578 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_WR_REQ_WPRID1_ENCRYPT 0x00000579 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_RD_REQ_WPRID2_ENCRYPT 0x0000057A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_WR_REQ_WPRID2_ENCRYPT 0x0000057B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_RD_REQ_WPRID3_ENCRYPT 0x0000057C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE6_WR_REQ_WPRID3_ENCRYPT 0x0000057D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_SVPR_PI 0x0000057E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_NEEDS_AES 0x0000057F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000580 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000581 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000582 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_RD_REQ_WPRID1_ENCRYPT 0x00000583 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_WR_REQ_WPRID1_ENCRYPT 0x00000584 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_RD_REQ_WPRID2_ENCRYPT 0x00000585 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_WR_REQ_WPRID2_ENCRYPT 0x00000586 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_RD_REQ_WPRID3_ENCRYPT 0x00000587 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FE7_WR_REQ_WPRID3_ENCRYPT 0x00000588 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_SVPR_PI 0x00000589 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_NEEDS_AES 0x0000058A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_NEEDS_AES_ITER_AES_BUSY 0x0000058B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x0000058C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_REQ_NONEED_AES_GO_THRO_ITER_AES 0x0000058D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_RD_REQ_WPRID1_ENCRYPT 0x0000058E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_WR_REQ_WPRID1_ENCRYPT 0x0000058F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_RD_REQ_WPRID2_ENCRYPT 0x00000590 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_WR_REQ_WPRID2_ENCRYPT 0x00000591 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_RD_REQ_WPRID3_ENCRYPT 0x00000592 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SEC_WR_REQ_WPRID3_ENCRYPT 0x00000593 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_SVPR_PI 0x00000594 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_NEEDS_AES 0x00000595 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000596 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000597 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000598 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_RD_REQ_WPRID1_ENCRYPT 0x00000599 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_WR_REQ_WPRID1_ENCRYPT 0x0000059A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_RD_REQ_WPRID2_ENCRYPT 0x0000059B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_WR_REQ_WPRID2_ENCRYPT 0x0000059C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_RD_REQ_WPRID3_ENCRYPT 0x0000059D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_GSP_WR_REQ_WPRID3_ENCRYPT 0x0000059E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_SVPR_PI 0x0000059F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_NEEDS_AES 0x000005A0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_NEEDS_AES_ITER_AES_BUSY 0x000005A1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000005A2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000005A3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_RD_REQ_WPRID1_ENCRYPT 0x000005A4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_WR_REQ_WPRID1_ENCRYPT 0x000005A5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_RD_REQ_WPRID2_ENCRYPT 0x000005A6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_WR_REQ_WPRID2_ENCRYPT 0x000005A7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_RD_REQ_WPRID3_ENCRYPT 0x000005A8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PMU_WR_REQ_WPRID3_ENCRYPT 0x000005A9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_SVPR_PI 0x000005AA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_NEEDS_AES 0x000005AB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_NEEDS_AES_ITER_AES_BUSY 0x000005AC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000005AD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000005AE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_RD_REQ_WPRID1_ENCRYPT 0x000005AF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_WR_REQ_WPRID1_ENCRYPT 0x000005B0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_RD_REQ_WPRID2_ENCRYPT 0x000005B1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_WR_REQ_WPRID2_ENCRYPT 0x000005B2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_RD_REQ_WPRID3_ENCRYPT 0x000005B3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_PERF_WR_REQ_WPRID3_ENCRYPT 0x000005B4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_SVPR_PI 0x000005B5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_NEEDS_AES 0x000005B6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_NEEDS_AES_ITER_AES_BUSY 0x000005B7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000005B8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000005B9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_RD_REQ_WPRID1_ENCRYPT 0x000005BA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_WR_REQ_WPRID1_ENCRYPT 0x000005BB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_RD_REQ_WPRID2_ENCRYPT 0x000005BC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_WR_REQ_WPRID2_ENCRYPT 0x000005BD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_RD_REQ_WPRID3_ENCRYPT 0x000005BE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_FBFALCON_WR_REQ_WPRID3_ENCRYPT 0x000005BF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_SVPR_PI 0x000005C0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_NEEDS_AES 0x000005C1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_NEEDS_AES_ITER_AES_BUSY 0x000005C2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000005C3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000005C4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_RD_REQ_WPRID1_ENCRYPT 0x000005C5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_WR_REQ_WPRID1_ENCRYPT 0x000005C6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_RD_REQ_WPRID2_ENCRYPT 0x000005C7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_WR_REQ_WPRID2_ENCRYPT 0x000005C8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_RD_REQ_WPRID3_ENCRYPT 0x000005C9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DNISO_WR_REQ_WPRID3_ENCRYPT 0x000005CA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_SVPR_PI 0x000005CB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_NEEDS_AES 0x000005CC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_NEEDS_AES_ITER_AES_BUSY 0x000005CD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000005CE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000005CF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_RD_REQ_WPRID1_ENCRYPT 0x000005D0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_WR_REQ_WPRID1_ENCRYPT 0x000005D1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_RD_REQ_WPRID2_ENCRYPT 0x000005D2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_WR_REQ_WPRID2_ENCRYPT 0x000005D3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_RD_REQ_WPRID3_ENCRYPT 0x000005D4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_DWBIF_WR_REQ_WPRID3_ENCRYPT 0x000005D5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_SVPR_PI 0x000005D6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_NEEDS_AES 0x000005D7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_NEEDS_AES_ITER_AES_BUSY 0x000005D8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000005D9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000005DA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_RD_REQ_WPRID1_ENCRYPT 0x000005DB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_WR_REQ_WPRID1_ENCRYPT 0x000005DC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_RD_REQ_WPRID2_ENCRYPT 0x000005DD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_WR_REQ_WPRID2_ENCRYPT 0x000005DE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_RD_REQ_WPRID3_ENCRYPT 0x000005DF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC0_WR_REQ_WPRID3_ENCRYPT 0x000005E0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_SVPR_PI 0x000005E1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_NEEDS_AES 0x000005E2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_NEEDS_AES_ITER_AES_BUSY 0x000005E3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000005E4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000005E5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_RD_REQ_WPRID1_ENCRYPT 0x000005E6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_WR_REQ_WPRID1_ENCRYPT 0x000005E7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_RD_REQ_WPRID2_ENCRYPT 0x000005E8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_WR_REQ_WPRID2_ENCRYPT 0x000005E9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_RD_REQ_WPRID3_ENCRYPT 0x000005EA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC1_WR_REQ_WPRID3_ENCRYPT 0x000005EB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_SVPR_PI 0x000005EC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_NEEDS_AES 0x000005ED /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_NEEDS_AES_ITER_AES_BUSY 0x000005EE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000005EF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000005F0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_RD_REQ_WPRID1_ENCRYPT 0x000005F1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_WR_REQ_WPRID1_ENCRYPT 0x000005F2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_RD_REQ_WPRID2_ENCRYPT 0x000005F3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_WR_REQ_WPRID2_ENCRYPT 0x000005F4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_RD_REQ_WPRID3_ENCRYPT 0x000005F5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC2_WR_REQ_WPRID3_ENCRYPT 0x000005F6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_SVPR_PI 0x000005F7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_NEEDS_AES 0x000005F8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_NEEDS_AES_ITER_AES_BUSY 0x000005F9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000005FA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000005FB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_RD_REQ_WPRID1_ENCRYPT 0x000005FC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_WR_REQ_WPRID1_ENCRYPT 0x000005FD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_RD_REQ_WPRID2_ENCRYPT 0x000005FE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_WR_REQ_WPRID2_ENCRYPT 0x000005FF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_RD_REQ_WPRID3_ENCRYPT 0x00000600 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC3_WR_REQ_WPRID3_ENCRYPT 0x00000601 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_SVPR_PI 0x00000602 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_NEEDS_AES 0x00000603 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000604 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000605 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000606 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_RD_REQ_WPRID1_ENCRYPT 0x00000607 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_WR_REQ_WPRID1_ENCRYPT 0x00000608 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_RD_REQ_WPRID2_ENCRYPT 0x00000609 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_WR_REQ_WPRID2_ENCRYPT 0x0000060A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_RD_REQ_WPRID3_ENCRYPT 0x0000060B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC4_WR_REQ_WPRID3_ENCRYPT 0x0000060C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_SVPR_PI 0x0000060D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_NEEDS_AES 0x0000060E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_NEEDS_AES_ITER_AES_BUSY 0x0000060F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000610 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000611 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_RD_REQ_WPRID1_ENCRYPT 0x00000612 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_WR_REQ_WPRID1_ENCRYPT 0x00000613 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_RD_REQ_WPRID2_ENCRYPT 0x00000614 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_WR_REQ_WPRID2_ENCRYPT 0x00000615 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_RD_REQ_WPRID3_ENCRYPT 0x00000616 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVDEC5_WR_REQ_WPRID3_ENCRYPT 0x00000617 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_SVPR_PI 0x00000618 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_NEEDS_AES 0x00000619 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_NEEDS_AES_ITER_AES_BUSY 0x0000061A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x0000061B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_REQ_NONEED_AES_GO_THRO_ITER_AES 0x0000061C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_RD_REQ_WPRID1_ENCRYPT 0x0000061D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_WR_REQ_WPRID1_ENCRYPT 0x0000061E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_RD_REQ_WPRID2_ENCRYPT 0x0000061F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_WR_REQ_WPRID2_ENCRYPT 0x00000620 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_RD_REQ_WPRID3_ENCRYPT 0x00000621 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC0_WR_REQ_WPRID3_ENCRYPT 0x00000622 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_SVPR_PI 0x00000623 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_NEEDS_AES 0x00000624 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000625 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000626 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000627 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_RD_REQ_WPRID1_ENCRYPT 0x00000628 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_WR_REQ_WPRID1_ENCRYPT 0x00000629 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_RD_REQ_WPRID2_ENCRYPT 0x0000062A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_WR_REQ_WPRID2_ENCRYPT 0x0000062B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_RD_REQ_WPRID3_ENCRYPT 0x0000062C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC1_WR_REQ_WPRID3_ENCRYPT 0x0000062D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_SVPR_PI 0x0000062E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_NEEDS_AES 0x0000062F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000630 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000631 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000632 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_RD_REQ_WPRID1_ENCRYPT 0x00000633 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_WR_REQ_WPRID1_ENCRYPT 0x00000634 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_RD_REQ_WPRID2_ENCRYPT 0x00000635 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_WR_REQ_WPRID2_ENCRYPT 0x00000636 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_RD_REQ_WPRID3_ENCRYPT 0x00000637 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVENC2_WR_REQ_WPRID3_ENCRYPT 0x00000638 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_SVPR_PI 0x00000639 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_NEEDS_AES 0x0000063A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_NEEDS_AES_ITER_AES_BUSY 0x0000063B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x0000063C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_REQ_NONEED_AES_GO_THRO_ITER_AES 0x0000063D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_RD_REQ_WPRID1_ENCRYPT 0x0000063E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_WR_REQ_WPRID1_ENCRYPT 0x0000063F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_RD_REQ_WPRID2_ENCRYPT 0x00000640 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_WR_REQ_WPRID2_ENCRYPT 0x00000641 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_RD_REQ_WPRID3_ENCRYPT 0x00000642 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG0_WR_REQ_WPRID3_ENCRYPT 0x00000643 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_SVPR_PI 0x00000644 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_NEEDS_AES 0x00000645 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000646 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000647 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000648 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_RD_REQ_WPRID1_ENCRYPT 0x00000649 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_WR_REQ_WPRID1_ENCRYPT 0x0000064A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_RD_REQ_WPRID2_ENCRYPT 0x0000064B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_WR_REQ_WPRID2_ENCRYPT 0x0000064C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_RD_REQ_WPRID3_ENCRYPT 0x0000064D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG1_WR_REQ_WPRID3_ENCRYPT 0x0000064E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_SVPR_PI 0x0000064F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_NEEDS_AES 0x00000650 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_NEEDS_AES_ITER_AES_BUSY 0x00000651 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x00000652 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_REQ_NONEED_AES_GO_THRO_ITER_AES 0x00000653 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_RD_REQ_WPRID1_ENCRYPT 0x00000654 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_WR_REQ_WPRID1_ENCRYPT 0x00000655 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_RD_REQ_WPRID2_ENCRYPT 0x00000656 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_WR_REQ_WPRID2_ENCRYPT 0x00000657 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_RD_REQ_WPRID3_ENCRYPT 0x00000658 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_NVJPG2_WR_REQ_WPRID3_ENCRYPT 0x00000659 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_SVPR_PI 0x0000065A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_NEEDS_AES 0x0000065B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_NEEDS_AES_ITER_AES_BUSY 0x0000065C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x0000065D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_REQ_NONEED_AES_GO_THRO_ITER_AES 0x0000065E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_RD_REQ_WPRID1_ENCRYPT 0x0000065F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_WR_REQ_WPRID1_ENCRYPT 0x00000660 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_RD_REQ_WPRID2_ENCRYPT 0x00000661 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_WR_REQ_WPRID2_ENCRYPT 0x00000662 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_RD_REQ_WPRID3_ENCRYPT 0x00000663 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_OFA0_WR_REQ_WPRID3_ENCRYPT 0x00000664 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SVPR_PO 0x00000665 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SVPR_PI 0x00000666 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SVPR_PI_MMU2CARB 0x00000667 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_SVPR_PI_ACK 0x00000668 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID0_RD_DATA_THRO_ITER 0x00000669 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID0_RD_DATA_THRO_RDP 0x0000066A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID0_WR_DATA_THRO_ITER 0x0000066B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID0_WR_DATA_THRO_RDP 0x0000066C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID1_RD_DATA_THRO_ITER 0x0000066D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID1_RD_DATA_THRO_RDP 0x0000066E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID1_WR_DATA_THRO_ITER 0x0000066F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID1_WR_DATA_THRO_RDP 0x00000670 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID2_RD_DATA_THRO_ITER 0x00000671 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID2_RD_DATA_THRO_RDP 0x00000672 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID2_WR_DATA_THRO_ITER 0x00000673 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID2_WR_DATA_THRO_RDP 0x00000674 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID3_RD_DATA_THRO_ITER 0x00000675 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID3_RD_DATA_THRO_RDP 0x00000676 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID3_WR_DATA_THRO_ITER 0x00000677 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ENCRYPT_WPRID3_WR_DATA_THRO_RDP 0x00000678 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ITER_AES_ENCRYPT_HAPPENING 0x00000679 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_ITER_AES_NONENCRYPT_HAPPENING 0x0000067A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_RDP_AES_ENCRYPT_HAPPENING 0x0000067B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_RDP_AES_NONENCRYPT_HAPPENING 0x0000067C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_32B_VC0_RD 0x0000067D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_64B_VC0_RD 0x0000067E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_96B_VC0_RD 0x0000067F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_128B_VC0_RD 0x00000680 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_160B_VC0_RD 0x00000681 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_192B_VC0_RD 0x00000682 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_224B_VC0_RD 0x00000683 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_256B_VC0_RD 0x00000684 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_P2P_VC0_RD 0x00000685 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_READ_VC0 0x00000686 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_32B_VC0_WR 0x00000687 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_64B_VC0_WR 0x00000688 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_96B_VC0_WR 0x00000689 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_128B_VC0_WR 0x0000068A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_P2P_VC0_WR 0x0000068B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_WRITE_VC0 0x0000068C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_32B_VC1_RD 0x0000068D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_64B_VC1_RD 0x0000068E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_96B_VC1_RD 0x0000068F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_128B_VC1_RD 0x00000690 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_160B_VC1_RD 0x00000691 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_192B_VC1_RD 0x00000692 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_224B_VC1_RD 0x00000693 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_256B_VC1_RD 0x00000694 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_P2P_VC1_RD 0x00000695 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_READ_VC1 0x00000696 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_32B_VC1_WR 0x00000697 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_64B_VC1_WR 0x00000698 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_96B_VC1_WR 0x00000699 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_128B_VC1_WR 0x0000069A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_P2P_VC1_WR 0x0000069B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_XVE_WRITE_VC1 0x0000069C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3 0x0000069D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_CACHE_REQ 0x0000069E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_NCACHE_REQ 0x0000069F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_VIDMEM_REQ 0x000006A0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_L2BYPASS_REQ 0x000006A1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_NO_CL 0x000006A2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_CL_NO_GNT 0x000006A3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_HOL_BLOCKED 0x000006A4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_RT_BLOCKED 0x000006A5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_FAM_BLOCKED 0x000006A6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_CACHEOP_BLOCKED 0x000006A7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_RBUF_FULL 0x000006A8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_MMU_PENDING 0x000006A9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_WDAT_BUFFER_FULL 0x000006AA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_GNT 0x000006AB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_WR_GRANT 0x000006AC /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_RD_GRANT 0x000006AD /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_FL_GRANT 0x000006AE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_RD_OUTSTANDING 0x000006AF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_SYSMEM_RD_OUTSTANDING 0x000006B0 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_SVPR_PI 0x000006B1 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_NEEDS_AES 0x000006B2 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_NEEDS_AES_ITER_AES_BUSY 0x000006B3 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_NEEDS_AES_CLIENT_OTHER_ITER 0x000006B4 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_REQ_NONEED_AES_GO_THRO_ITER_AES 0x000006B5 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_RD_REQ_WPRID1_ENCRYPT 0x000006B6 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_WR_REQ_WPRID1_ENCRYPT 0x000006B7 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_RD_REQ_WPRID2_ENCRYPT 0x000006B8 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_WR_REQ_WPRID2_ENCRYPT 0x000006B9 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_RD_REQ_WPRID3_ENCRYPT 0x000006BA /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_GRP0_CE3_WR_REQ_WPRID3_ENCRYPT 0x000006BB /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_ADR_OF_INTEREST_L2B 0x00000750 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_CACHE_OP_FULL 0x00000751 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_FLUSH_FIFO_FULL 0x00000752 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H_THIN0_PVLD 0x00000753 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H_THIN0_PRDY 0x00000754 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F_THIN0_MBAR_CMD_PVLD 0x00000755 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F_THIN0_MBAR_CMD_PRDY 0x00000756 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F_THIN0_ACK_PVLD 0x00000757 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F_THIN0_ACK_PRDY 0x00000758 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_ITER0_WDAT_HOL_BLK 0x00000759 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_SYSMEM_RDAT_L2REF_HOL_BLK 0x0000075A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_SYSMEM_RDAT_L2BYP_HOL_BLK 0x0000075B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_L2BYP_CMD_HOL_BLK 0x0000075C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H0_IG_FLUSH_REQ 0x0000075D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F0_IG_FLUSH_ACK 0x0000075E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H0_EG_FLUSH_REQ 0x0000075F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F0_NVL_FLUSH_ACK 0x00000760 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H0_NVL_FLUSH_REQ 0x00000761 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F0_EG_FLUSH_ACK 0x00000762 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H1_IG_FLUSH_REQ 0x00000763 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F1_IG_FLUSH_ACK 0x00000764 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H1_EG_FLUSH_REQ 0x00000765 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F1_NVL_FLUSH_ACK 0x00000766 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H1_NVL_FLUSH_REQ 0x00000767 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F1_EG_FLUSH_ACK 0x00000768 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_P2P0 0x00000769 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_P2P1 0x0000076A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_P2P2 0x0000076B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_P2P3 0x0000076C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_P2P4 0x0000076D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_P2P5 0x0000076E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_P2P6 0x0000076F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_P2P7 0x00000770 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_SYSCOH 0x00000771 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_MBOPT_KILL_FLUSH_SYSNCOH 0x00000772 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_RRRB_CAMPING 0x00000773 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_ITER1_WDAT_HOL_BLK 0x00000774 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_ITER2_WDAT_HOL_BLK 0x00000775 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_ITER3_WDAT_HOL_BLK 0x00000776 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_ITER4_WDAT_HOL_BLK 0x00000777 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_ITER5_WDAT_HOL_BLK 0x00000778 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_ITER6_WDAT_HOL_BLK 0x00000779 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H_THIN1_PVLD 0x0000077A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_F2H_THIN1_PRDY 0x0000077B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F_THIN1_MBAR_CMD_PVLD 0x0000077C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F_THIN1_MBAR_CMD_PRDY 0x0000077D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F_THIN1_ACK_PVLD 0x0000077E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL0_H2F_THIN1_ACK_PRDY 0x0000077F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL1 21:11 /* RWIVF */ #define NV_PFB_NISO_PM_CLIENT_SEL1_GRP0_HOST 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_CLIENT_SEL1_GRP0_STATIC_PATTERN_0_1_GROUP 0x000007FE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_SEL1_GRP0_STATIC_PATTERN_1_1_GROUP 0x000007FF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL 29:22 /* RWIVF */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_STATIC_PATTERN_0A_5_GROUP 0x000000FE /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_STATIC_PATTERN_15_5_GROUP 0x000000FF /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_INGRESS_BLCPG_STATUS 0x00000001 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_INGRESS_ISO_BLCPG_STATUS 0x00000002 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_EGRESS_BLCPG_STATUS 0x00000003 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_EGRESS_ISO_BLCPG_STATUS 0x00000004 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NISO_STATUS 0x00000005 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ISO_STATUS 0x00000006 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_INGRESS_STATUS 0x00000007 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_INGRESS_ISO_STATUS 0x00000008 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_EGRESS_STATUS 0x00000009 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_EGRESS_ISO_STATUS 0x0000000A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_RT_STATUS 0x0000000B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FAM_STATUS 0x0000000C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_WDP_STATUS 0x0000000D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_MMU_STATUS 0x0000000E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SYSMEM_INGRESS_STATUS 0x0000000F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_RARB_STATUS 0x00000010 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_RDP_STATUS 0x00000011 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SYSMEM_EGRESS_STATUS 0x00000012 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_BLK_ACTIVITY_NISO 0x00000013 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_BLK_ACTIVITY_ISO 0x00000014 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_HOST 0x00000015 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_HOST_CPU 0x00000016 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_HOST_CPU_NB 0x00000017 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC0 0x00000018 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC1 0x00000019 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC2 0x0000001A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC3 0x0000001B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC4 0x0000001C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC5 0x0000001D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC6 0x0000001E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC7 0x0000001F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC8 0x00000020 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC9 0x00000021 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC10 0x00000022 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ESC11 0x00000023 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_P2P 0x00000024 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_MMU 0x00000025 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_MMU_NB 0x00000026 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_CE0 0x00000027 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_CE1 0x00000028 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_CE2 0x00000029 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_CE_SHIM 0x0000002A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FE 0x0000002B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FE0 0x0000002C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FE1 0x0000002D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FE2 0x0000002E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FE3 0x0000002F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FE4 0x00000030 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FE5 0x00000031 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FE6 0x00000032 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FE7 0x00000033 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SKED 0x00000034 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SKED0 0x00000035 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SKED1 0x00000036 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SKED2 0x00000037 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SKED3 0x00000038 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SKED4 0x00000039 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SKED5 0x0000003A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SKED6 0x0000003B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SKED7 0x0000003C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SCC 0x0000003D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SCC_NB 0x0000003E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_PD 0x0000003F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SEC 0x00000040 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_GSP 0x00000041 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_PMU 0x00000042 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_PERF 0x00000043 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_FBFALCON 0x00000044 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DNISO 0x00000045 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DWBIF 0x00000046 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVDEC0 0x00000047 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVDEC1 0x00000048 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVDEC2 0x00000049 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVDEC3 0x0000004A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVDEC4 0x0000004B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVDEC5 0x0000004C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVENC0 0x0000004D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVENC1 0x0000004E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVENC2 0x0000004F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVJPG0 0x00000050 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVJPG1 0x00000051 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_NVJPG2 0x00000052 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_OFA0 0x00000053 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS 0x00000054 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_RASTERTWOD 0x00000055 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SSYNC 0x00000056 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_PD_MSG0 0x00000057 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_PD_MSG1 0x00000058 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE0 0x00000059 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE1 0x0000005A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE2 0x0000005B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE3 0x0000005C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE4 0x0000005D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE5 0x0000005E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE6 0x0000005F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE7 0x00000060 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE8 0x00000061 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE9 0x00000062 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE10 0x00000063 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE11 0x00000064 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE12 0x00000065 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE13 0x00000066 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE14 0x00000067 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE15 0x00000068 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE16 0x00000069 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE17 0x0000006A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE18 0x0000006B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE19 0x0000006C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE20 0x0000006D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_SLCG_ON_ZONE21 0x0000006E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DEBUG_BUS_0 0x0000006F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DEBUG_BUS_1 0x00000070 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DEBUG_BUS_2 0x00000071 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DEBUG_BUS_3 0x00000072 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DEBUG_BUS_4 0x00000073 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DEBUG_BUS_5 0x00000074 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DEBUG_BUS_6 0x00000075 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_DEBUG_BUS_7 0x00000076 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_UPDT_MIMC 0x00000077 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_UPDT_MOMC 0x00000078 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_UPDT_ALL 0x00000079 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NEW_ALLOC_MIMC 0x0000007A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NEW_ALLOC_MOMC 0x0000007B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NEW_ALLOC_ALL 0x0000007C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_UPDT_BF_MERGE_MIMC 0x0000007D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_UPDT_BF_MERGE_MOMC 0x0000007E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_UPDT_BF_MERGE_ALL 0x0000007F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_UPDT_AF_MERGE_MIMC 0x00000080 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_UPDT_AF_MERGE_MOMC 0x00000081 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_UPDT_AF_MERGE_ALL 0x00000082 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NG0_EVICTIONS_MIMC 0x00000083 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NG0_EVICTIONS_MOMC 0x00000084 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NG0_EVICTIONS_ALL 0x00000085 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NG1_EVICTIONS_MIMC 0x00000086 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NG1_EVICTIONS_MOMC 0x00000087 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NG1_EVICTIONS_ALL 0x00000088 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_EVICTIONS_MIMC 0x00000089 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_EVICTIONS_MOMC 0x0000008A /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_EVICTIONS_ALL 0x0000008B /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NOTI_GEN_IN_MIMC 0x0000008C /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NOTI_GEN_IN_MOMC 0x0000008D /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NOTI_GEN_IN_ALL 0x0000008E /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NOTI_TRIG_IN_MIMC 0x0000008F /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NOTI_TRIG_IN_MOMC 0x00000090 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_ACTRS_NOTI_TRIG_IN_ALL 0x00000091 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_MUX_SEL_CE3 0x00000092 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_ENABLE 31:31 /* RWEVF */ #define NV_PFB_NISO_PM_CLIENT_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_PM_CLIENT_ENABLE_OFF 0x00000000 /* RWE-V */ #define NV_PFB_NISO_PM_INTFC 0x00100C1C /* RW-4R */ #define NV_PFB_NISO_PM_INTFC_SEL0 9:0 /* RWIVF */ #define NV_PFB_NISO_PM_INTFC_SEL0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_STATIC_PATTERN_0_1_GROUP 0x000003fe /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_STATIC_PATTERN_1_1_GROUP 0x000003ff /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HOST 0x00000210 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HOST_CPU 0x00000211 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HOST_CPU_NB 0x00000212 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC0 0x00000213 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC1 0x00000214 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC2 0x00000215 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC3 0x00000216 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC4 0x00000217 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC5 0x00000218 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC6 0x00000219 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC7 0x0000021A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC8 0x0000021B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC9 0x0000021C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC10 0x0000021D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ESC11 0x0000021E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_P2P 0x0000021F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_MMU 0x00000220 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_MMU_NB 0x00000221 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_CE0 0x00000222 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_CE1 0x00000223 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_CE2 0x00000224 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_CE_SHIM 0x00000225 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE 0x00000226 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE0 0x00000227 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE1 0x00000228 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE2 0x00000229 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE3 0x0000022A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE4 0x0000022B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE5 0x0000022C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE6 0x0000022D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE7 0x0000022E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SKED 0x0000022F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SKED0 0x00000230 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SKED1 0x00000231 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SKED2 0x00000232 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SKED3 0x00000233 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SKED4 0x00000234 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SKED5 0x00000235 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SKED6 0x00000236 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SKED7 0x00000237 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCC 0x00000238 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCC_NB 0x00000239 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_PD 0x0000023A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SEC 0x0000023B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_GSP 0x0000023C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_PMU 0x0000023D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_PERF 0x0000023E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBFALCON 0x0000023F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_DNISO 0x00000240 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_DWBIF 0x00000241 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVDEC0 0x00000242 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVDEC1 0x00000243 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVDEC2 0x00000244 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVDEC3 0x00000245 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVDEC4 0x00000246 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVDEC5 0x00000247 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVENC0 0x00000248 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVENC1 0x00000249 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVENC2 0x0000024A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVJPG0 0x0000024B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVJPG1 0x0000024C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NVJPG2 0x0000024D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_OFA0 0x0000024E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ACTRS 0x0000024F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RASTERTWOD 0x00000250 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SSYNC 0x00000251 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_PD_MSG0 0x00000252 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_PD_MSG1 0x00000253 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FE_WDAT 0x00000254 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCC_WDAT 0x00000255 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCC_NB_WDAT 0x00000256 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ACTRS_WDAT 0x00000257 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HOST_WDAT 0x00000258 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HOST_CPU_WDAT 0x00000259 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HOST_CPU_NB_WDAT 0x0000025A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ISOHUB 0x0000025B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HOST 0x0000025C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HOST_CPU 0x0000025D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HOST_CPU_NB 0x0000025E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC0 0x0000025F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC1 0x00000260 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC2 0x00000261 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC3 0x00000262 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC4 0x00000263 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC5 0x00000264 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC6 0x00000265 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC7 0x00000266 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC8 0x00000267 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC9 0x00000268 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC10 0x00000269 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ESC11 0x0000026A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_P2P 0x0000026B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_MMU 0x0000026C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_MMU_NB 0x0000026D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_CE0 0x0000026E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_CE1 0x0000026F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_CE2 0x00000270 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_CE_SHIM 0x00000271 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE 0x00000272 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE0 0x00000273 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE1 0x00000274 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE2 0x00000275 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE3 0x00000276 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE4 0x00000277 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE5 0x00000278 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE6 0x00000279 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE7 0x0000027A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED 0x0000027B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED0 0x0000027C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED1 0x0000027D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED2 0x0000027E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED3 0x0000027F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED4 0x00000280 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED5 0x00000281 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED6 0x00000282 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED7 0x00000283 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SCC 0x00000284 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SCC_NB 0x00000285 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_PD 0x00000286 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SEC 0x00000287 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_GSP 0x00000288 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_PMU 0x00000289 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_PERF 0x0000028A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBFALCON 0x0000028B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_DNISO 0x0000028C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_DWBIF 0x0000028D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVDEC0 0x0000028E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVDEC1 0x0000028F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVDEC2 0x00000290 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVDEC3 0x00000291 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVDEC4 0x00000292 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVDEC5 0x00000293 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVENC0 0x00000294 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVENC1 0x00000295 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVENC2 0x00000296 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVJPG0 0x00000297 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVJPG1 0x00000298 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NVJPG2 0x00000299 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_OFA0 0x0000029A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ACTRS 0x0000029B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RASTERTWOD 0x0000029C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SSYNC 0x0000029D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_PD_MSG0 0x0000029E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_PD_MSG1 0x0000029F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FE_WDAT 0x000002A0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SCC_WDAT 0x000002A1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SCC_NB_WDAT 0x000002A2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ACTRS_WDAT 0x000002A3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HOST_WDAT 0x000002A4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HOST_CPU_WDAT 0x000002A5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HOST_CPU_NB_WDAT 0x000002A6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ISOHUB 0x000002A7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_CE3 0x000002A8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_CE3 0x000002A9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_NB 0x00000020 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_NB 0x00000021 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_NB 0x00000022 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_NB 0x00000023 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_B 0x00000024 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_B 0x00000025 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_B 0x00000026 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_B 0x00000027 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_NINB 0x00000028 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_NINB 0x00000029 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_NINB 0x0000002A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_NINB 0x0000002B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_ISO 0x0000002C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_ISO 0x0000002D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_ISO 0x0000002E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_ISO 0x0000002F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_DATA_NB 0x00000030 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_DATA_NB 0x00000031 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_DATA_NB 0x00000032 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_DATA_NB 0x00000033 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_DATA_B 0x00000034 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_DATA_B 0x00000035 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_DATA_B 0x00000036 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_DATA_B 0x00000037 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_DATA_NINB 0x00000038 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_DATA_NINB 0x00000039 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_DATA_NINB 0x0000003A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_DATA_NINB 0x0000003B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_NB 0x00000020 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_NB 0x00000021 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_NB 0x00000022 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_NB 0x00000023 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_B 0x00000024 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_B 0x00000025 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_B 0x00000026 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_B 0x00000027 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_NINB 0x00000028 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_NINB 0x00000029 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_NINB 0x0000002A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_NINB 0x0000002B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_ISO 0x0000002C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_ISO 0x0000002D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_ISO 0x0000002E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_ISO 0x0000002F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_DATA_NB 0x00000030 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_DATA_NB 0x00000031 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_DATA_NB 0x00000032 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_DATA_NB 0x00000033 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_DATA_B 0x00000034 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_DATA_B 0x00000035 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_DATA_B 0x00000036 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_DATA_B 0x00000037 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_DATA_NINB 0x00000038 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_DATA_NINB 0x00000039 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_DATA_NINB 0x0000003A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_DATA_NINB 0x0000003B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_DWBIF_PITCH_REQ 0x0000003D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_DWBIF_BL_REQ 0x0000003E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC0_CMD_NB 0x00000040 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC1_CMD_NB 0x00000041 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC2_CMD_NB 0x00000042 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC3_CMD_NB 0x00000043 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC0_CMD_B 0x00000044 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC1_CMD_B 0x00000045 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC2_CMD_B 0x00000046 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC3_CMD_B 0x00000047 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC0_CMD_NINB 0x00000048 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC1_CMD_NINB 0x00000049 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC2_CMD_NINB 0x0000004a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC3_CMD_NINB 0x0000004b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC0_CMD_NIB 0x0000004c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC1_CMD_NIB 0x0000004d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC2_CMD_NIB 0x0000004e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC3_CMD_NIB 0x0000004f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC0_DATA_NB 0x00000050 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC1_DATA_NB 0x00000051 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC2_DATA_NB 0x00000052 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC3_DATA_NB 0x00000053 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC0_DATA_ISO 0x00000054 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC1_DATA_ISO 0x00000055 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC2_DATA_ISO 0x00000056 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC3_DATA_ISO 0x00000057 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC0_DATA_NINB 0x00000058 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC1_DATA_NINB 0x00000059 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC2_DATA_NINB 0x0000005a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC3_DATA_NINB 0x0000005b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC0_DATA_B 0x0000005c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC1_DATA_B 0x0000005d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC2_DATA_B 0x0000005e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XBAR2HNIC3_DATA_B 0x0000005f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH0_CMD_NB 0x00000040 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH1_CMD_NB 0x00000041 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH2_CMD_NB 0x00000042 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH3_CMD_NB 0x00000043 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH0_CMD_B 0x00000044 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH1_CMD_B 0x00000045 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH2_CMD_B 0x00000046 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH3_CMD_B 0x00000047 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH0_CMD_NINB 0x00000048 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH1_CMD_NINB 0x00000049 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH2_CMD_NINB 0x0000004a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH3_CMD_NINB 0x0000004b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH0_CMD_NIB 0x0000004c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH1_CMD_NIB 0x0000004d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH2_CMD_NIB 0x0000004e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH3_CMD_NIB 0x0000004f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH0_DATA_NB 0x00000050 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH1_DATA_NB 0x00000051 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH2_DATA_NB 0x00000052 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH3_DATA_NB 0x00000053 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH0_DATA_ISO 0x00000054 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH1_DATA_ISO 0x00000055 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH2_DATA_ISO 0x00000056 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH3_DATA_ISO 0x00000057 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH0_DATA_NINB 0x00000058 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH1_DATA_NINB 0x00000059 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH2_DATA_NINB 0x0000005a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH3_DATA_NINB 0x0000005b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH0_DATA_B 0x0000005c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH1_DATA_B 0x0000005d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH2_DATA_B 0x0000005e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HSH2FBH3_DATA_B 0x0000005f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ARB2MMU 0x00000060 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HUB2MMUHUBTLB0 0x00000061 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HUB2MMUHUBTLB1 0x00000062 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_VC_NINB 0x00000063 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_VC_NIB 0x00000064 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_VC_NB 0x00000065 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_VC_B 0x00000066 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_MSG_CLIENT2HNIC 0x00000067 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XVE2FB_RDAT_VC0 0x00000068 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC02SYSMEM_VC0 0x00000069 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC12SYSMEM_VC0 0x0000006a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC22SYSMEM_VC0 0x0000006b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC32SYSMEM_VC0 0x0000006c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FB2XVE_NP_VC0 0x0000006d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FB2XVE_PW_VC0 0x0000006e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC02MSG 0x0000006f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC12MSG 0x00000070 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC22MSG 0x00000071 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC32MSG 0x00000072 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_MSG2SSYNC 0x00000073 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_MSG2FE 0x00000074 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_MSG2PMA 0x00000200 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RT2RARB_COMPL 0x00000075 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_NISO_CLIENTS_RDAT 0x00000076 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_RD 0x00000077 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_RD 0x00000078 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_RD 0x00000079 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_RD 0x0000007a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_WR 0x0000007b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_WR 0x0000007c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_WR 0x0000007d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_WR 0x0000007e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_CM 0x0000007f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_CM 0x00000080 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_CM 0x00000081 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_CM 0x00000082 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_DATA_RDAT 0x00000083 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_DATA_RDAT 0x00000084 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_DATA_RDAT 0x00000085 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_DATA_RDAT 0x00000086 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_DATA_WDAT 0x00000087 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_DATA_WDAT 0x00000088 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_DATA_WDAT 0x00000089 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_DATA_WDAT 0x0000008a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_DATA_MSG 0x0000008b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_DATA_MSG 0x0000008c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_DATA_MSG 0x0000008d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_DATA_MSG 0x0000008e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_RD 0x00000077 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_RD 0x00000078 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_RD 0x00000079 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_RD 0x0000007a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_WR 0x0000007b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_WR 0x0000007c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_WR 0x0000007d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_WR 0x0000007e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_CM 0x0000007f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_CM 0x00000080 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_CM 0x00000081 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_CM 0x00000082 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_DATA_RDAT 0x00000083 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_DATA_RDAT 0x00000084 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_DATA_RDAT 0x00000085 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_DATA_RDAT 0x00000086 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_DATA_WDAT 0x00000087 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_DATA_WDAT 0x00000088 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_DATA_WDAT 0x00000089 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_DATA_WDAT 0x0000008a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_DATA_MSG 0x0000008b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_DATA_MSG 0x0000008c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_DATA_MSG 0x0000008d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_DATA_MSG 0x0000008e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RARB2RDP 0x0000008f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SYSMEM_PSS_0 0x00000090 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SYSMEM_PSS_1 0x00000091 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SYSMEM_PSS_2 0x00000092 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SYSMEM_PSS_3 0x00000093 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RRRB2RT_NISO_0 0x00000094 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RRRB2RT_NISO_1 0x00000095 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RRRB2RT_NISO_2 0x00000096 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RRRB2RT_NISO_3 0x00000097 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RRRB2RT_ISO_0 0x00000098 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RRRB2RT_ISO_1 0x00000099 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RRRB2RT_ISO_2 0x0000009a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RRRB2RT_ISO_3 0x0000009b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC02SYSMEM_VC1 0x0000009c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC12SYSMEM_VC1 0x0000009d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC22SYSMEM_VC1 0x0000009e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC32SYSMEM_VC1 0x0000009f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FB2XVE_NP_VC1 0x000000a0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FB2XVE_PW_VC1 0x000000a1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XVE2FB_RDAT_VC1 0x000000a2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ISO_HEAD0 0x000000a3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ISO_HEAD1 0x000000a4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_L2B_CMD 0x000000a5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_L2B_WDAT 0x000000a6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2SYSMEM_VC0 0x000000a7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2SYSMEM_VC1 0x000000a8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_VC_NINB_OUT_ST 0x000000ad /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_VC_NIB_OUT_ST 0x000000ae /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_VC_NB_OUT_ST 0x000000af /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_VC_B_OUT_ST 0x000000b0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_MSG_CLIENT2HNIC_OUT_ST 0x000000b1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_XVE2FB_RDAT_VC0_OUT_ST 0x000000b2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2SYSMEM_VC0_IN_ST 0x000000b3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2SYSMEM_VC1_IN_ST 0x000000b4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC02MSG_GNT 0x000000b5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC12MSG_GNT 0x000000b6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC22MSG_GNT 0x000000b7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC32MSG_GNT 0x000000b8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_CARB2ITER_NVOL_L2B 0x000000b9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FB2XVE_VC0_WID2_WR 0x000000ba /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FB2XVE_VC0_WID2_RD 0x000000bb /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FB2XVE_VC1_WID2_WR 0x000000bc /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FB2XVE_VC1_WID2_RD 0x000000bd /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_CARB2ITER_L2B 0x000000be /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC02SYSMEM_RD 0x000000bf /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC12SYSMEM_RD 0x000000c0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC22SYSMEM_RD 0x000000c1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC32SYSMEM_RD 0x000000c2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_PCIE_MEMBAR_LAT 0x000000c3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_INGRESS_WAKEUP0 0x000000c4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_INGRESS_WAKEUP1 0x000000c5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_INGRESS_WAKEUP2 0x000000c6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_INGRESS_WAKEUP3 0x000000c7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_INGRESS_WAKEUP4 0x000000c8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_INGRESS_WAKEUP5 0x000000c9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_EGRESS_WAKEUP0 0x000000ca /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_EGRESS_WAKEUP1 0x000000cb /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_EGRESS_WAKEUP2 0x000000cc /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_EGRESS_WAKEUP3 0x000000cd /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_EGRESS_WAKEUP4 0x000000ce /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_INGRESS_ISO_WAKEUP0 0x000000cf /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_EGRESS_ISO_WAKEUP0 0x000000d0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_EGRESS_ISO_WAKEUP1 0x000000d1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_MMUFILL_WAKEUP 0x000000d2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ISO_WAKEUP0 0x000000d3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_ISO_WAKEUP1 0x000000d4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_MEMBAR 0x000000d7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_MEMBAR 0x000000d8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_MEMBAR 0x000000d9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_MEMBAR 0x000000da /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_MEMBAR 0x000000d7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_MEMBAR 0x000000d8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_MEMBAR 0x000000d9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_MEMBAR 0x000000da /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2HOST_GWC_IN_ACTIVE 0x000000db /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2SKED_GWC_IN_ACTIVE 0x000000dc /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_EGRESS_ISO_WAKEUP2 0x000000dd /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBFALCON_PITCH_REQ 0x000000DE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBFALCON_BL_REQ 0x000000DF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RAST 0x000000e0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_PE 0x000000e1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_L1C 0x000000e2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_TEX0 0x000000e3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_TEX1 0x000000e4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_GCC 0x000000e5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_GPCCS 0x000000e6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_PROP 0x000000e7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RAST_WDAT 0x000000e8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_PE_WDAT 0x000000e9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_L1C_WDAT 0x000000ea /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_GPCCS_WDAT 0x000000eb /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_RESP 0x000000f2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_RESP 0x000000f3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH0_CMD_RESP 0x000000f4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH1_CMD_RESP 0x000000f5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_DATA_RESP 0x000000f6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_DATA_RESP 0x000000f7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH0_DATA_RESP 0x000000f8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH1_DATA_RESP 0x000000f9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_RESP 0x000000f2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_RESP 0x000000f3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR0_CMD_RESP 0x000000f4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR1_CMD_RESP 0x000000f5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_DATA_RESP 0x000000f6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_DATA_RESP 0x000000f7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR0_DATA_RESP 0x000000f8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR1_DATA_RESP 0x000000f9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_CLIENT2MMU_RESP_PENDING 0x000000fa /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR0_CMD_NB 0x00000120 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR1_CMD_NB 0x00000121 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR2_CMD_NB 0x00000122 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR3_CMD_NB 0x00000123 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR0_CMD_B 0x00000124 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR1_CMD_B 0x00000125 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR2_CMD_B 0x00000126 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR3_CMD_B 0x00000127 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR0_CMD_NINB 0x00000128 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR1_CMD_NINB 0x00000129 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR2_CMD_NINB 0x0000012A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR3_CMD_NINB 0x0000012B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR0_CMD_ISO 0x0000012C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR1_CMD_ISO 0x0000012D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR2_CMD_ISO 0x0000012E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR3_CMD_ISO 0x0000012F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR0_DATA_NB 0x00000130 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR1_DATA_NB 0x00000131 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR2_DATA_NB 0x00000132 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR3_DATA_NB 0x00000133 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR0_DATA_B 0x00000134 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR1_DATA_B 0x00000135 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR2_DATA_B 0x00000136 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR3_DATA_B 0x00000137 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR0_DATA_NINB 0x00000138 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR1_DATA_NINB 0x00000139 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR2_DATA_NINB 0x0000013A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XBAR3_DATA_NINB 0x0000013B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH0_CMD_NB 0x00000120 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH1_CMD_NB 0x00000121 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH2_CMD_NB 0x00000122 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH3_CMD_NB 0x00000123 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH0_CMD_B 0x00000124 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH1_CMD_B 0x00000125 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH2_CMD_B 0x00000126 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH3_CMD_B 0x00000127 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH0_CMD_NINB 0x00000128 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH1_CMD_NINB 0x00000129 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH2_CMD_NINB 0x0000012A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH3_CMD_NINB 0x0000012B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH0_CMD_ISO 0x0000012C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH1_CMD_ISO 0x0000012D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH2_CMD_ISO 0x0000012E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH3_CMD_ISO 0x0000012F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH0_DATA_NB 0x00000130 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH1_DATA_NB 0x00000131 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH2_DATA_NB 0x00000132 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH3_DATA_NB 0x00000133 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH0_DATA_B 0x00000134 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH1_DATA_B 0x00000135 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH2_DATA_B 0x00000136 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH3_DATA_B 0x00000137 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH0_DATA_NINB 0x00000138 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH1_DATA_NINB 0x00000139 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH2_DATA_NINB 0x0000013A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FBH2HSH3_DATA_NINB 0x0000013B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC0_CMD_NB 0x00000140 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC1_CMD_NB 0x00000141 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC2_CMD_NB 0x00000142 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC3_CMD_NB 0x00000143 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC0_CMD_B 0x00000144 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC1_CMD_B 0x00000145 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC2_CMD_B 0x00000146 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC3_CMD_B 0x00000147 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC0_CMD_NINB 0x00000148 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC1_CMD_NINB 0x00000149 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC2_CMD_NINB 0x0000014a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC3_CMD_NINB 0x0000014b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC0_CMD_NIB 0x0000014c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC1_CMD_NIB 0x0000014d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC2_CMD_NIB 0x0000014e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC3_CMD_NIB 0x0000014f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC0_DATA_NB 0x00000150 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC1_DATA_NB 0x00000151 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC2_DATA_NB 0x00000152 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC3_DATA_NB 0x00000153 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC0_DATA_ISO 0x00000154 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC1_DATA_ISO 0x00000155 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC2_DATA_ISO 0x00000156 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC3_DATA_ISO 0x00000157 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC0_DATA_NINB 0x00000158 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC1_DATA_NINB 0x00000159 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC2_DATA_NINB 0x0000015a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC3_DATA_NINB 0x0000015b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC0_DATA_B 0x0000015c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC1_DATA_B 0x0000015d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC2_DATA_B 0x0000015e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC3_DATA_B 0x0000015f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH0_CMD_NB 0x00000140 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH1_CMD_NB 0x00000141 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH2_CMD_NB 0x00000142 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH3_CMD_NB 0x00000143 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH0_CMD_B 0x00000144 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH1_CMD_B 0x00000145 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH2_CMD_B 0x00000146 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH3_CMD_B 0x00000147 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH0_CMD_NINB 0x00000148 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH1_CMD_NINB 0x00000149 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH2_CMD_NINB 0x0000014a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH3_CMD_NINB 0x0000014b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH0_CMD_NIB 0x0000014c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH1_CMD_NIB 0x0000014d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH2_CMD_NIB 0x0000014e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH3_CMD_NIB 0x0000014f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH0_DATA_NB 0x00000150 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH1_DATA_NB 0x00000151 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH2_DATA_NB 0x00000152 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH3_DATA_NB 0x00000153 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH0_DATA_ISO 0x00000154 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH1_DATA_ISO 0x00000155 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH2_DATA_ISO 0x00000156 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH3_DATA_ISO 0x00000157 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH0_DATA_NINB 0x00000158 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH1_DATA_NINB 0x00000159 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH2_DATA_NINB 0x0000015a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH3_DATA_NINB 0x0000015b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH0_DATA_B 0x0000015c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH1_DATA_B 0x0000015d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH2_DATA_B 0x0000015e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH3_DATA_B 0x0000015f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ARB2MMU 0x00000160 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HUB2MMUHUBTLB0 0x00000161 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HUB2MMUHUBTLB1 0x00000162 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_VC_NINB 0x00000163 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_VC_NIB 0x00000164 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_VC_NB 0x00000165 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_VC_B 0x00000166 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_MSG_CLIENT2HNIC 0x00000167 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XVE2FB_RDAT_VC0 0x00000168 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC02SYSMEM_VC0 0x00000169 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC12SYSMEM_VC0 0x0000016a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC22SYSMEM_VC0 0x0000016b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC32SYSMEM_VC0 0x0000016c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FB2XVE_NP_VC0 0x0000016d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FB2XVE_PW_VC0 0x0000016e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC02MSG 0x0000016f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC12MSG 0x00000170 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC22MSG 0x00000171 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC32MSG 0x00000172 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_MSG2SSYNC 0x00000173 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_MSG2FE 0x00000174 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_MSG2PMA 0x00000201 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RT2RARB_COMPL 0x00000175 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_NISO_CLIENTS_RDAT 0x00000176 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_DISPNISO_PITCH_REQ 0x0000017A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_DISPNISO_BL_REQ 0x0000017B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_GSP_PITCH_REQ 0x00000182 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_GSP_BL_REQ 0x00000183 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_CE_SHIM_PITCH_REQ 0x00000186 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_CE_SHIM_BL_REQ 0x00000187 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RARB2RDP 0x0000018f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SYSMEM_PSS_0 0x00000190 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SYSMEM_PSS_1 0x00000191 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SYSMEM_PSS_2 0x00000192 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SYSMEM_PSS_3 0x00000193 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB2RT_NISO_0 0x00000194 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB2RT_NISO_1 0x00000195 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB2RT_NISO_2 0x00000196 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB2RT_NISO_3 0x00000197 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB2RT_ISO_0 0x00000198 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB2RT_ISO_1 0x00000199 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB2RT_ISO_2 0x0000019a /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB2RT_ISO_3 0x0000019b /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC02SYSMEM_VC1 0x0000019c /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC12SYSMEM_VC1 0x0000019d /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC22SYSMEM_VC1 0x0000019e /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC32SYSMEM_VC1 0x0000019f /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FB2XVE_NP_VC1 0x000001a0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FB2XVE_PW_VC1 0x000001a1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XVE2FB_RDAT_VC1 0x000001a2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ISO_HEAD0 0x000001a3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ISO_HEAD1 0x000001a4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_L2B_CMD 0x000001a5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_L2B_WDAT 0x000001a6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2SYSMEM_VC0 0x000001a7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2SYSMEM_VC1 0x000001a8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC0_DATA_RD 0x000001a9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC1_DATA_RD 0x000001aa /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC2_DATA_RD 0x000001ab /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XBAR2HNIC3_DATA_RD 0x000001ac /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH0_DATA_RD 0x000001a9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH1_DATA_RD 0x000001aa /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH2_DATA_RD 0x000001ab /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HSH2FBH3_DATA_RD 0x000001ac /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_VC_NINB_OUT_ST 0x000001ad /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_VC_NIB_OUT_ST 0x000001ae /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_VC_NB_OUT_ST 0x000001af /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_VC_B_OUT_ST 0x000001b0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_MSG_CLIENT2HNIC_OUT_ST 0x000001b1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_XVE2FB_RDAT_VC0_OUT_ST 0x000001b2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2SYSMEM_VC0_IN_ST 0x000001b3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2SYSMEM_VC1_IN_ST 0x000001b4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC02MSG_GNT 0x000001b5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC12MSG_GNT 0x000001b6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC22MSG_GNT 0x000001b7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC32MSG_GNT 0x000001b8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_CARB2ITER_NVOL_L2B 0x000001b9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FB2XVE_VC0_WID2_WR 0x000001ba /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FB2XVE_VC0_WID2_RD 0x000001bb /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FB2XVE_VC1_WID2_WR 0x000001bc /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_FB2XVE_VC1_WID2_RD 0x000001bd /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_CARB2ITER_L2B 0x000001be /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC02SYSMEM_RD 0x000001bf /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC12SYSMEM_RD 0x000001c0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC22SYSMEM_RD 0x000001c1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC32SYSMEM_RD 0x000001c2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_PCIE_MEMBAR_LAT 0x000001c3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2MSG_OUT_ST 0x000001c4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XVE_VC0_OUT_ST 0x000001c5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2XVE_VC1_OUT_ST 0x000001c6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_CLIENT2MMU_OUT_ST 0x000001c7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB_BUSY 0x000001c8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_RRRB_ISO_BUSY 0x000001c9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2HOST_GWC_IN_ST 0x000001ca /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2SKED_GWC_IN_ST 0x000001cb /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2HOST_GWC_OUT_ST 0x000001cc /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2SKED_GWC_OUT_ST 0x000001cd /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2HOST_GWC_FIFO_FULL 0x000001ce /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2SKED_GWC_FIFO_FULL 0x000001cf /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2SKED_GWC_OUT_PEND 0x000001f0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HNIC2HOST_GWC_OUT_PEND 0x000001f1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_SKED2FB_FLUSH_ACK_PEND 0x000001f2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_HOST2FB_FLUSH_ACK_PEND 0x000001f3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_GPC_MEMBAR_WAITING_SKED2FB_FLUSH_ACK 0x000001f4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_GPC_MEMBAR_WAITING_HOST2FB_FLUSH_ACK 0x000001f5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_GPC_MEMBAR_PENDING 0x000001f6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ITER0_VC_NINB_PACK_RD_CMD 0x000001f7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ITER0_VC_NB_PACK_RD_CMD 0x000001f8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ITER0_VC_B_PACK_RD_CMD 0x000001f9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ITER1_VC_B_PACK_RD_CMD 0x000001fa /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP1_ITER0_VC_ISO_PACK_RD_CMD 0x000001fb /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_PACK_RD 0x000001d6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_PACK_RD 0x000001d7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_PACK_RD 0x000001d8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_PACK_RD 0x000001d9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR0_CMD_CONCAT_WR 0x000001da /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR1_CMD_CONCAT_WR 0x000001db /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR2_CMD_CONCAT_WR 0x000001dc /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_HNIC2XBAR3_CMD_CONCAT_WR 0x000001dd /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_PACK_RD 0x000001d6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_PACK_RD 0x000001d7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_PACK_RD 0x000001d8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_PACK_RD 0x000001d9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_CONCAT_WR 0x000001da /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_CONCAT_WR 0x000001db /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_CONCAT_WR 0x000001dc /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_CONCAT_WR 0x000001dd /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RDP0_STALLED_OUTPUT_VLD_BUT_NOT_NXT 0x000001de /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RDP1_STALLED_OUTPUT_VLD_BUT_NOT_NXT 0x000001df /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RDP2_STALLED_OUTPUT_VLD_BUT_NOT_NXT 0x000001e0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_RDP3_STALLED_OUTPUT_VLD_BUT_NOT_NXT 0x000001e1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCRUB_START 0x000001e4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCRUB_END 0x000001e5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCRUB_IN_PROGRESS 0x000001e6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCRUB_SM0_WAITING_ON_MB_ACK 0x000001e7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCRUB_SM1_WAITING_ON_MB_ACK 0x000001e8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCRUB_SM0_STALL 0x000001e9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCRUB_SM1_STALL 0x000001ea /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_SCRUB_WASTED_CYCLE 0x000001eb /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH0_CMD_SCRUB 0x000001ec /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH1_CMD_SCRUB 0x000001ed /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH2_CMD_SCRUB 0x000001ee /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL0_GRP0_FBH2HSH3_CMD_SCRUB 0x000001ef /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL1 19:10 /* RWIVF */ #define NV_PFB_NISO_PM_INTFC_SEL1_GRP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_INTFC_SEL1_GRP0_STATIC_PATTERN_0_1_GROUP 0x000003fe /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL1_GRP0_STATIC_PATTERN_1_1_GROUP 0x000003ff /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2 28:20 /* RWIVF */ #define NV_PFB_NISO_PM_INTFC_SEL2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_INTFC_SEL2_STATIC_PATTERN_0_1_GROUP 0x000001FE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_STATIC_PATTERN_1_1_GROUP 0x000001FF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_XFER_NB 0x00000000 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_XFER_B 0x00000001 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_XFER_NINB 0x00000002 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_B_REQ_NO_CLR 0x00000004 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_NB_REQ_NO_CLR 0x00000005 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_NINB_REQ_NO_CLR 0x00000006 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_ISO_REQ_NO_CLR 0x00000007 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_B_REQ_NO_GNT 0x00000008 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_NB_REQ_NO_GNT 0x00000009 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_NINB_REQ_NO_GNT 0x0000000A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_ISO_REQ_NO_GNT 0x0000000B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_B_CREDIT_GE1 0x0000000C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_NB_CREDIT_GE1 0x0000000D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_NINB_CREDIT_GE1 0x0000000E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_ISO_CREDIT_GE1 0x0000000F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_B_CREDIT_GE5 0x00000010 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_NB_CREDIT_GE5 0x00000011 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_NINB_CREDIT_GE5 0x00000012 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_ISO_CREDIT_GE5 0x00000013 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_RW_SZ0 0x00000014 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_RW_SZ1 0x00000015 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_RW_SZ2 0x00000016 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_RW_SZ3 0x00000017 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_SYSMEM_RW_SZ0 0x00000018 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_SYSMEM_RW_SZ1 0x00000019 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_SYSMEM_RW_SZ2 0x0000001A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_SYSMEM_RW_SZ3 0x0000001B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_VC_NINB_CONCAT_WR_CMD 0x0000001C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_VC_NB_CONCAT_WR_CMD 0x0000001D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR0_VC_B_CONCAT_WR_CMD 0x0000001E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_XFER_NB 0x00000000 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_XFER_B 0x00000001 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_XFER_NINB 0x00000002 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_B_REQ_NO_CLR 0x00000004 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_NB_REQ_NO_CLR 0x00000005 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_NINB_REQ_NO_CLR 0x00000006 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_ISO_REQ_NO_CLR 0x00000007 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_B_REQ_NO_GNT 0x00000008 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_NB_REQ_NO_GNT 0x00000009 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_NINB_REQ_NO_GNT 0x0000000A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_ISO_REQ_NO_GNT 0x0000000B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_B_CREDIT_GE1 0x0000000C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_NB_CREDIT_GE1 0x0000000D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_NINB_CREDIT_GE1 0x0000000E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_ISO_CREDIT_GE1 0x0000000F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_B_CREDIT_GE5 0x00000010 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_NB_CREDIT_GE5 0x00000011 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_NINB_CREDIT_GE5 0x00000012 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_ISO_CREDIT_GE5 0x00000013 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_RW_SZ0 0x00000014 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_RW_SZ1 0x00000015 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_RW_SZ2 0x00000016 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_RW_SZ3 0x00000017 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_SYSMEM_RW_SZ0 0x00000018 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_SYSMEM_RW_SZ1 0x00000019 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_SYSMEM_RW_SZ2 0x0000001A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_SYSMEM_RW_SZ3 0x0000001B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_VC_NINB_CONCAT_WR_CMD 0x0000001C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_VC_NB_CONCAT_WR_CMD 0x0000001D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH0_VC_B_CONCAT_WR_CMD 0x0000001E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_XFER_NB 0x00000020 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_XFER_B 0x00000021 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_XFER_NINB 0x00000022 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_B_REQ_NO_CLR 0x00000024 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_NB_REQ_NO_CLR 0x00000025 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_NINB_REQ_NO_CLR 0x00000026 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_ISO_REQ_NO_CLR 0x00000027 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_B_REQ_NO_GNT 0x00000028 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_NB_REQ_NO_GNT 0x00000029 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_NINB_REQ_NO_GNT 0x0000002A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_ISO_REQ_NO_GNT 0x0000002B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_B_CREDIT_GE1 0x0000002C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_NB_CREDIT_GE1 0x0000002D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_NINB_CREDIT_GE1 0x0000002E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_ISO_CREDIT_GE1 0x0000002F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_B_CREDIT_GE5 0x00000030 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_NB_CREDIT_GE5 0x00000031 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_NINB_CREDIT_GE5 0x00000032 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_ISO_CREDIT_GE5 0x00000033 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_RW_SZ0 0x00000034 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_RW_SZ1 0x00000035 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_RW_SZ2 0x00000036 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_RW_SZ3 0x00000037 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_SYSMEM_RW_SZ0 0x00000038 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_SYSMEM_RW_SZ1 0x00000039 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_SYSMEM_RW_SZ2 0x0000003A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_SYSMEM_RW_SZ3 0x0000003B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_VC_NINB_CONCAT_WR_CMD 0x0000003C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_VC_NB_CONCAT_WR_CMD 0x0000003D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR1_VC_B_CONCAT_WR_CMD 0x0000003E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_XFER_NB 0x00000020 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_XFER_B 0x00000021 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_XFER_NINB 0x00000022 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_B_REQ_NO_CLR 0x00000024 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_NB_REQ_NO_CLR 0x00000025 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_NINB_REQ_NO_CLR 0x00000026 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_ISO_REQ_NO_CLR 0x00000027 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_B_REQ_NO_GNT 0x00000028 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_NB_REQ_NO_GNT 0x00000029 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_NINB_REQ_NO_GNT 0x0000002A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_ISO_REQ_NO_GNT 0x0000002B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_B_CREDIT_GE1 0x0000002C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_NB_CREDIT_GE1 0x0000002D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_NINB_CREDIT_GE1 0x0000002E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_ISO_CREDIT_GE1 0x0000002F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_B_CREDIT_GE5 0x00000030 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_NB_CREDIT_GE5 0x00000031 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_NINB_CREDIT_GE5 0x00000032 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_ISO_CREDIT_GE5 0x00000033 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_RW_SZ0 0x00000034 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_RW_SZ1 0x00000035 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_RW_SZ2 0x00000036 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_RW_SZ3 0x00000037 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_SYSMEM_RW_SZ0 0x00000038 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_SYSMEM_RW_SZ1 0x00000039 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_SYSMEM_RW_SZ2 0x0000003A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_SYSMEM_RW_SZ3 0x0000003B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_VC_NINB_CONCAT_WR_CMD 0x0000003C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_VC_NB_CONCAT_WR_CMD 0x0000003D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH1_VC_B_CONCAT_WR_CMD 0x0000003E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_XFER_NB 0x00000040 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_XFER_B 0x00000041 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_XFER_NINB 0x00000042 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_B_REQ_NO_CLR 0x00000044 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_NB_REQ_NO_CLR 0x00000045 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_NINB_REQ_NO_CLR 0x00000046 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_ISO_REQ_NO_CLR 0x00000047 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_B_REQ_NO_GNT 0x00000048 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_NB_REQ_NO_GNT 0x00000049 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_NINB_REQ_NO_GNT 0x0000004A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_ISO_REQ_NO_GNT 0x0000004B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_B_CREDIT_GE1 0x0000004C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_NB_CREDIT_GE1 0x0000004D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_NINB_CREDIT_GE1 0x0000004E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_ISO_CREDIT_GE1 0x0000004F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_B_CREDIT_GE5 0x00000050 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_NB_CREDIT_GE5 0x00000051 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_NINB_CREDIT_GE5 0x00000052 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_ISO_CREDIT_GE5 0x00000053 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_RW_SZ0 0x00000054 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_RW_SZ1 0x00000055 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_RW_SZ2 0x00000056 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_RW_SZ3 0x00000057 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_SYSMEM_RW_SZ0 0x00000058 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_SYSMEM_RW_SZ1 0x00000059 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_SYSMEM_RW_SZ2 0x0000005A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_SYSMEM_RW_SZ3 0x0000005B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_VC_NINB_CONCAT_WR_CMD 0x0000005C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_VC_NB_CONCAT_WR_CMD 0x0000005D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR2_VC_B_CONCAT_WR_CMD 0x0000005E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_XFER_NB 0x00000040 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_XFER_B 0x00000041 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_XFER_NINB 0x00000042 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_B_REQ_NO_CLR 0x00000044 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_NB_REQ_NO_CLR 0x00000045 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_NINB_REQ_NO_CLR 0x00000046 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_ISO_REQ_NO_CLR 0x00000047 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_B_REQ_NO_GNT 0x00000048 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_NB_REQ_NO_GNT 0x00000049 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_NINB_REQ_NO_GNT 0x0000004A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_ISO_REQ_NO_GNT 0x0000004B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_B_CREDIT_GE1 0x0000004C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_NB_CREDIT_GE1 0x0000004D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_NINB_CREDIT_GE1 0x0000004E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_ISO_CREDIT_GE1 0x0000004F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_B_CREDIT_GE5 0x00000050 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_NB_CREDIT_GE5 0x00000051 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_NINB_CREDIT_GE5 0x00000052 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_ISO_CREDIT_GE5 0x00000053 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_RW_SZ0 0x00000054 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_RW_SZ1 0x00000055 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_RW_SZ2 0x00000056 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_RW_SZ3 0x00000057 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_SYSMEM_RW_SZ0 0x00000058 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_SYSMEM_RW_SZ1 0x00000059 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_SYSMEM_RW_SZ2 0x0000005A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_SYSMEM_RW_SZ3 0x0000005B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_VC_NINB_CONCAT_WR_CMD 0x0000005C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_VC_NB_CONCAT_WR_CMD 0x0000005D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH2_VC_B_CONCAT_WR_CMD 0x0000005E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_XFER_NB 0x00000060 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_XFER_B 0x00000061 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_XFER_NINB 0x00000062 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_B_REQ_NO_CLR 0x00000064 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_NB_REQ_NO_CLR 0x00000065 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_NINB_REQ_NO_CLR 0x00000066 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_ISO_REQ_NO_CLR 0x00000067 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_B_REQ_NO_GNT 0x00000068 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_NB_REQ_NO_GNT 0x00000069 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_NINB_REQ_NO_GNT 0x0000006A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_ISO_REQ_NO_GNT 0x0000006B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_B_CREDIT_GE1 0x0000006C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_NB_CREDIT_GE1 0x0000006D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_NINB_CREDIT_GE1 0x0000006E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_ISO_CREDIT_GE1 0x0000006F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_B_CREDIT_GE5 0x00000070 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_NB_CREDIT_GE5 0x00000071 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_NINB_CREDIT_GE5 0x00000072 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_ISO_CREDIT_GE5 0x00000073 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_RW_SZ0 0x00000074 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_RW_SZ1 0x00000075 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_RW_SZ2 0x00000076 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_RW_SZ3 0x00000077 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_SYSMEM_RW_SZ0 0x00000078 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_SYSMEM_RW_SZ1 0x00000079 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_SYSMEM_RW_SZ2 0x0000007A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_SYSMEM_RW_SZ3 0x0000007B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_VC_NINB_CONCAT_WR_CMD 0x0000007C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_VC_NB_CONCAT_WR_CMD 0x0000007D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HNIC2XBAR3_VC_B_CONCAT_WR_CMD 0x0000007E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_XFER_NB 0x00000060 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_XFER_B 0x00000061 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_XFER_NINB 0x00000062 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_B_REQ_NO_CLR 0x00000064 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_NB_REQ_NO_CLR 0x00000065 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_NINB_REQ_NO_CLR 0x00000066 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_ISO_REQ_NO_CLR 0x00000067 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_B_REQ_NO_GNT 0x00000068 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_NB_REQ_NO_GNT 0x00000069 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_NINB_REQ_NO_GNT 0x0000006A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_ISO_REQ_NO_GNT 0x0000006B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_B_CREDIT_GE1 0x0000006C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_NB_CREDIT_GE1 0x0000006D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_NINB_CREDIT_GE1 0x0000006E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_ISO_CREDIT_GE1 0x0000006F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_B_CREDIT_GE5 0x00000070 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_NB_CREDIT_GE5 0x00000071 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_NINB_CREDIT_GE5 0x00000072 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_ISO_CREDIT_GE5 0x00000073 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_RW_SZ0 0x00000074 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_RW_SZ1 0x00000075 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_RW_SZ2 0x00000076 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_RW_SZ3 0x00000077 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_SYSMEM_RW_SZ0 0x00000078 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_SYSMEM_RW_SZ1 0x00000079 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_SYSMEM_RW_SZ2 0x0000007A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_SYSMEM_RW_SZ3 0x0000007B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_VC_NINB_CONCAT_WR_CMD 0x0000007C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_VC_NB_CONCAT_WR_CMD 0x0000007D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_FBH2HSH3_VC_B_CONCAT_WR_CMD 0x0000007E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_XFER_SYSMEM_RD 0x00000080 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_XFER_SYSMEM_WR 0x00000081 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_XFER_SYSMEM_RW_SZ0 0x00000082 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_XFER_SYSMEM_RW_SZ1 0x00000083 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_XFER_SYSMEM_RW_SZ2 0x00000084 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_XFER_SYSMEM_RW_SZ3 0x00000085 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_XFER_MSG 0x00000086 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_XFER_ACK 0x00000087 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_XFER_RDAT 0x00000088 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_BF_SYSMEM_REQ_NO_CLR 0x00000089 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_BF_SYSMEM_REQ_NO_GNT 0x0000008A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_BF_SYSMEM_GNT 0x0000008B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_BG_MEMBAR_REQ_NO_CLR 0x0000008C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_BG_MEMBAR_REQ_NO_GNT 0x0000008D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_BG_MEMBAR_GNT 0x0000008E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_NB_MSG_REQ_NO_CLR 0x0000008F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_NB_MSG_REQ_NO_GNT 0x00000090 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_NB_MSG_GNT 0x00000091 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_NINB_SYSMEM_REQ_NO_CLR 0x00000092 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_NINB_SYSMEM_REQ_NO_GNT 0x00000093 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_NINB_SYSMEM_GNT 0x00000094 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_NB_RDAT_REQ_NO_CLR 0x00000095 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_NB_RDAT_REQ_NO_GNT 0x00000096 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_NB_RDAT_GNT 0x00000097 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_BG_GWC_REQ_NO_CLR 0x00000098 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_BG_GWC_REQ_NO_GNT 0x00000099 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC0_BG_GWC_GNT 0x0000009A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_XFER_SYSMEM_RD 0x00000080 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_XFER_SYSMEM_WR 0x00000081 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_XFER_SYSMEM_RW_SZ0 0x00000082 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_XFER_SYSMEM_RW_SZ1 0x00000083 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_XFER_SYSMEM_RW_SZ2 0x00000084 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_XFER_SYSMEM_RW_SZ3 0x00000085 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_XFER_MSG 0x00000086 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_XFER_ACK 0x00000087 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_XFER_RDAT 0x00000088 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_BF_SYSMEM_REQ_NO_CLR 0x00000089 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_BF_SYSMEM_REQ_NO_GNT 0x0000008A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_BF_SYSMEM_GNT 0x0000008B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_BG_MEMBAR_REQ_NO_CLR 0x0000008C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_BG_MEMBAR_REQ_NO_GNT 0x0000008D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_BG_MEMBAR_GNT 0x0000008E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_NB_MSG_REQ_NO_CLR 0x0000008F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_NB_MSG_REQ_NO_GNT 0x00000090 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_NB_MSG_GNT 0x00000091 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_NINB_SYSMEM_REQ_NO_CLR 0x00000092 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_NINB_SYSMEM_REQ_NO_GNT 0x00000093 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_NINB_SYSMEM_GNT 0x00000094 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_NB_RDAT_REQ_NO_CLR 0x00000095 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_NB_RDAT_REQ_NO_GNT 0x00000096 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_NB_RDAT_GNT 0x00000097 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_BG_GWC_REQ_NO_CLR 0x00000098 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_BG_GWC_REQ_NO_GNT 0x00000099 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH0_BG_GWC_GNT 0x0000009A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_XFER_SYSMEM_RD 0x000000A0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_XFER_SYSMEM_WR 0x000000A1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_XFER_SYSMEM_RW_SZ0 0x000000A2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_XFER_SYSMEM_RW_SZ1 0x000000A3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_XFER_SYSMEM_RW_SZ2 0x000000A4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_XFER_SYSMEM_RW_SZ3 0x000000A5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_XFER_MSG 0x000000A6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_XFER_ACK 0x000000A7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_XFER_RDAT 0x000000A8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_BF_SYSMEM_REQ_NO_CLR 0x000000A9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_BF_SYSMEM_REQ_NO_GNT 0x000000AA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_BF_SYSMEM_GNT 0x000000AB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_BG_MEMBAR_REQ_NO_CLR 0x000000AC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_BG_MEMBAR_REQ_NO_GNT 0x000000AD /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_BG_MEMBAR_GNT 0x000000AE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_NB_MSG_REQ_NO_CLR 0x000000AF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_NB_MSG_REQ_NO_GNT 0x000000B0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_NB_MSG_GNT 0x000000B1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_NINB_SYSMEM_REQ_NO_CLR 0x000000B2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_NINB_SYSMEM_REQ_NO_GNT 0x000000B3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_NINB_SYSMEM_GNT 0x000000B4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_NB_RDAT_REQ_NO_CLR 0x000000B5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_NB_RDAT_REQ_NO_GNT 0x000000B6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_NB_RDAT_GNT 0x000000B7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_BG_GWC_REQ_NO_CLR 0x000000B8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_BG_GWC_REQ_NO_GNT 0x000000B9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC1_BG_GWC_GNT 0x000000BA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_XFER_SYSMEM_RD 0x000000A0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_XFER_SYSMEM_WR 0x000000A1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_XFER_SYSMEM_RW_SZ0 0x000000A2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_XFER_SYSMEM_RW_SZ1 0x000000A3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_XFER_SYSMEM_RW_SZ2 0x000000A4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_XFER_SYSMEM_RW_SZ3 0x000000A5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_XFER_MSG 0x000000A6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_XFER_ACK 0x000000A7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_XFER_RDAT 0x000000A8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_BF_SYSMEM_REQ_NO_CLR 0x000000A9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_BF_SYSMEM_REQ_NO_GNT 0x000000AA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_BF_SYSMEM_GNT 0x000000AB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_BG_MEMBAR_REQ_NO_CLR 0x000000AC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_BG_MEMBAR_REQ_NO_GNT 0x000000AD /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_BG_MEMBAR_GNT 0x000000AE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_NB_MSG_REQ_NO_CLR 0x000000AF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_NB_MSG_REQ_NO_GNT 0x000000B0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_NB_MSG_GNT 0x000000B1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_NINB_SYSMEM_REQ_NO_CLR 0x000000B2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_NINB_SYSMEM_REQ_NO_GNT 0x000000B3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_NINB_SYSMEM_GNT 0x000000B4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_NB_RDAT_REQ_NO_CLR 0x000000B5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_NB_RDAT_REQ_NO_GNT 0x000000B6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_NB_RDAT_GNT 0x000000B7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_BG_GWC_REQ_NO_CLR 0x000000B8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_BG_GWC_REQ_NO_GNT 0x000000B9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH1_BG_GWC_GNT 0x000000BA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_XFER_SYSMEM_RD 0x000000C0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_XFER_SYSMEM_WR 0x000000C1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_XFER_SYSMEM_RW_SZ0 0x000000C2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_XFER_SYSMEM_RW_SZ1 0x000000C3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_XFER_SYSMEM_RW_SZ2 0x000000C4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_XFER_SYSMEM_RW_SZ3 0x000000C5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_XFER_MSG 0x000000C6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_XFER_ACK 0x000000C7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_XFER_RDAT 0x000000C8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_BF_SYSMEM_REQ_NO_CLR 0x000000C9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_BF_SYSMEM_REQ_NO_GNT 0x000000CA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_BF_SYSMEM_GNT 0x000000CB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_BG_MEMBAR_REQ_NO_CLR 0x000000CC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_BG_MEMBAR_REQ_NO_GNT 0x000000CD /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_BG_MEMBAR_GNT 0x000000CE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_NB_MSG_REQ_NO_CLR 0x000000CF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_NB_MSG_REQ_NO_GNT 0x000000D0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_NB_MSG_GNT 0x000000D1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_NINB_SYSMEM_REQ_NO_CLR 0x000000D2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_NINB_SYSMEM_REQ_NO_GNT 0x000000D3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_NINB_SYSMEM_GNT 0x000000D4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_NB_RDAT_REQ_NO_CLR 0x000000D5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_NB_RDAT_REQ_NO_GNT 0x000000D6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_NB_RDAT_GNT 0x000000D7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_BG_GWC_REQ_NO_CLR 0x000000D8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_BG_GWC_REQ_NO_GNT 0x000000D9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC2_BG_GWC_GNT 0x000000DA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_XFER_SYSMEM_RD 0x000000C0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_XFER_SYSMEM_WR 0x000000C1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_XFER_SYSMEM_RW_SZ0 0x000000C2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_XFER_SYSMEM_RW_SZ1 0x000000C3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_XFER_SYSMEM_RW_SZ2 0x000000C4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_XFER_SYSMEM_RW_SZ3 0x000000C5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_XFER_MSG 0x000000C6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_XFER_ACK 0x000000C7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_XFER_RDAT 0x000000C8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_BF_SYSMEM_REQ_NO_CLR 0x000000C9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_BF_SYSMEM_REQ_NO_GNT 0x000000CA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_BF_SYSMEM_GNT 0x000000CB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_BG_MEMBAR_REQ_NO_CLR 0x000000CC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_BG_MEMBAR_REQ_NO_GNT 0x000000CD /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_BG_MEMBAR_GNT 0x000000CE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_NB_MSG_REQ_NO_CLR 0x000000CF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_NB_MSG_REQ_NO_GNT 0x000000D0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_NB_MSG_GNT 0x000000D1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_NINB_SYSMEM_REQ_NO_CLR 0x000000D2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_NINB_SYSMEM_REQ_NO_GNT 0x000000D3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_NINB_SYSMEM_GNT 0x000000D4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_NB_RDAT_REQ_NO_CLR 0x000000D5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_NB_RDAT_REQ_NO_GNT 0x000000D6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_NB_RDAT_GNT 0x000000D7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_BG_GWC_REQ_NO_CLR 0x000000D8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_BG_GWC_REQ_NO_GNT 0x000000D9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH2_BG_GWC_GNT 0x000000DA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_XFER_SYSMEM_RD 0x000000E0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_XFER_SYSMEM_WR 0x000000E1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_XFER_SYSMEM_RW_SZ0 0x000000E2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_XFER_SYSMEM_RW_SZ1 0x000000E3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_XFER_SYSMEM_RW_SZ2 0x000000E4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_XFER_SYSMEM_RW_SZ3 0x000000E5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_XFER_MSG 0x000000E6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_XFER_ACK 0x000000E7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_XFER_RDAT 0x000000E8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_BF_SYSMEM_REQ_NO_CLR 0x000000E9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_BF_SYSMEM_REQ_NO_GNT 0x000000EA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_BF_SYSMEM_GNT 0x000000EB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_BG_MEMBAR_REQ_NO_CLR 0x000000EC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_BG_MEMBAR_REQ_NO_GNT 0x000000ED /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_BG_MEMBAR_GNT 0x000000EE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_NB_MSG_REQ_NO_CLR 0x000000EF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_NB_MSG_REQ_NO_GNT 0x000000F0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_NB_MSG_GNT 0x000000F1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_NINB_SYSMEM_REQ_NO_CLR 0x000000F2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_NINB_SYSMEM_REQ_NO_GNT 0x000000F3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_NINB_SYSMEM_GNT 0x000000F4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_NB_RDAT_REQ_NO_CLR 0x000000F5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_NB_RDAT_REQ_NO_GNT 0x000000F6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_NB_RDAT_GNT 0x000000F7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_BG_GWC_REQ_NO_CLR 0x000000F8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_BG_GWC_REQ_NO_GNT 0x000000F9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_XBAR2HNIC3_BG_GWC_GNT 0x000000FA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_XFER_SYSMEM_RD 0x000000E0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_XFER_SYSMEM_WR 0x000000E1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_XFER_SYSMEM_RW_SZ0 0x000000E2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_XFER_SYSMEM_RW_SZ1 0x000000E3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_XFER_SYSMEM_RW_SZ2 0x000000E4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_XFER_SYSMEM_RW_SZ3 0x000000E5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_XFER_MSG 0x000000E6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_XFER_ACK 0x000000E7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_XFER_RDAT 0x000000E8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_BF_SYSMEM_REQ_NO_CLR 0x000000E9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_BF_SYSMEM_REQ_NO_GNT 0x000000EA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_BF_SYSMEM_GNT 0x000000EB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_BG_MEMBAR_REQ_NO_CLR 0x000000EC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_BG_MEMBAR_REQ_NO_GNT 0x000000ED /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_BG_MEMBAR_GNT 0x000000EE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_NB_MSG_REQ_NO_CLR 0x000000EF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_NB_MSG_REQ_NO_GNT 0x000000F0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_NB_MSG_GNT 0x000000F1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_NINB_SYSMEM_REQ_NO_CLR 0x000000F2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_NINB_SYSMEM_REQ_NO_GNT 0x000000F3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_NINB_SYSMEM_GNT 0x000000F4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_NB_RDAT_REQ_NO_CLR 0x000000F5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_NB_RDAT_REQ_NO_GNT 0x000000F6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_NB_RDAT_GNT 0x000000F7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_BG_GWC_REQ_NO_CLR 0x000000F8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_BG_GWC_REQ_NO_GNT 0x000000F9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_HSH2FBH3_BG_GWC_GNT 0x000000FA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_STALL_CYCLES_PCIE_MIMC 0x000000FB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_DRPD_PKT_PCIE_MIMC 0x000000FC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_STALL_CYCLES 0x000000FD /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_GT_3_MIMC_BANK_NOTI 0x000000FE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_LT_3_MIMC_BANK_NOTI 0x000000FF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_GT_3_MOMC_BANK_NOTI 0x00000100 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_LT_3_MOMC_BANK_NOTI 0x00000101 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_MIMC_MOMC_BANK_NOTI 0x00000102 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_BANK_NOTI_MIMC_WON 0x00000103 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_BANK_NOTI_MOMC_WON 0x00000104 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_0 0x00000105 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_1 0x00000106 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_2 0x00000107 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_3 0x00000108 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_4 0x00000109 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_5 0x0000010A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_6 0x00000172 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_7 0x00000173 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_8 0x00000174 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_9 0x00000175 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_10 0x00000176 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_11 0x00000177 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MIMC_IFACE_12 0x00000178 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_0 0x0000010C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_1 0x0000010D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_2 0x0000010E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_3 0x0000010F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_4 0x00000110 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_5 0x00000111 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_6 0x00000179 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_7 0x0000017A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_8 0x0000017B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_9 0x0000017C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_10 0x0000017D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_UPDT_PER_MOMC_IFACE_11 0x0000017E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MIMC_BANK_0 0x00000112 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MIMC_BANK_1 0x00000113 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MIMC_BANK_2 0x00000114 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MIMC_BANK_3 0x00000115 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MIMC_BANK_4 0x00000116 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MIMC_BANK_5 0x00000117 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MIMC_BANK_6 0x00000118 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MIMC_BANK_7 0x00000119 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MOMC_BANK_0 0x0000011A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MOMC_BANK_1 0x0000011B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MOMC_BANK_2 0x0000011C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MOMC_BANK_3 0x0000011D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MOMC_BANK_4 0x0000011E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MOMC_BANK_5 0x0000011F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MOMC_BANK_6 0x00000120 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NEW_ALLOC_PER_MOMC_BANK_7 0x00000121 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MIMC_BANK_0 0x00000122 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MIMC_BANK_1 0x00000123 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MIMC_BANK_2 0x00000124 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MIMC_BANK_3 0x00000125 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MIMC_BANK_4 0x00000126 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MIMC_BANK_5 0x00000127 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MIMC_BANK_6 0x00000128 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MIMC_BANK_7 0x00000129 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MOMC_BANK_0 0x0000012A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MOMC_BANK_1 0x0000012B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MOMC_BANK_2 0x0000012C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MOMC_BANK_3 0x0000012D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MOMC_BANK_4 0x0000012E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MOMC_BANK_5 0x0000012F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MOMC_BANK_6 0x00000130 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG0_EVCTNS_PER_MOMC_BANK_7 0x00000131 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MIMC_BANK_0 0x00000132 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MIMC_BANK_1 0x00000133 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MIMC_BANK_2 0x00000134 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MIMC_BANK_3 0x00000135 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MIMC_BANK_4 0x00000136 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MIMC_BANK_5 0x00000137 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MIMC_BANK_6 0x00000138 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MIMC_BANK_7 0x00000139 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MOMC_BANK_0 0x0000013A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MOMC_BANK_1 0x0000013B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MOMC_BANK_2 0x0000013C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MOMC_BANK_3 0x0000013D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MOMC_BANK_4 0x0000013E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MOMC_BANK_5 0x0000013F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MOMC_BANK_6 0x00000140 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NG1_EVCTNS_PER_MOMC_BANK_7 0x00000141 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MIMC_BANK_0 0x00000142 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MIMC_BANK_1 0x00000143 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MIMC_BANK_2 0x00000144 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MIMC_BANK_3 0x00000145 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MIMC_BANK_4 0x00000146 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MIMC_BANK_5 0x00000147 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MIMC_BANK_6 0x00000148 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MIMC_BANK_7 0x00000149 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MOMC_BANK_0 0x0000014A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MOMC_BANK_1 0x0000014B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MOMC_BANK_2 0x0000014C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MOMC_BANK_3 0x0000014D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MOMC_BANK_4 0x0000014E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MOMC_BANK_5 0x0000014F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MOMC_BANK_6 0x00000150 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_TOTAL_EVCTNS_PER_MOMC_BANK_7 0x00000151 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MIMC_BANK_0 0x00000152 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MIMC_BANK_1 0x00000153 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MIMC_BANK_2 0x00000154 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MIMC_BANK_3 0x00000155 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MIMC_BANK_4 0x00000156 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MIMC_BANK_5 0x00000157 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MIMC_BANK_6 0x00000158 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MIMC_BANK_7 0x00000159 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MOMC_BANK_0 0x0000015A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MOMC_BANK_1 0x0000015B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MOMC_BANK_2 0x0000015C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MOMC_BANK_3 0x0000015D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MOMC_BANK_4 0x0000015E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MOMC_BANK_5 0x0000015F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MOMC_BANK_6 0x00000160 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_GEN_PER_MOMC_BANK_7 0x00000161 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MIMC_BANK_0 0x00000162 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MIMC_BANK_1 0x00000163 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MIMC_BANK_2 0x00000164 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MIMC_BANK_3 0x00000165 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MIMC_BANK_4 0x00000166 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MIMC_BANK_5 0x00000167 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MIMC_BANK_6 0x00000168 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MIMC_BANK_7 0x00000169 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MOMC_BANK_0 0x0000016A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MOMC_BANK_1 0x0000016B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MOMC_BANK_2 0x0000016C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MOMC_BANK_3 0x0000016D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MOMC_BANK_4 0x0000016E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MOMC_BANK_5 0x0000016F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MOMC_BANK_6 0x00000170 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_ACTRS_NOTI_TRIG_PER_MOMC_BANK_7 0x00000171 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED0_PUTPTR_ACTIVE 0x00000180 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED1_PUTPTR_ACTIVE 0x00000181 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED2_PUTPTR_ACTIVE 0x00000182 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED3_PUTPTR_ACTIVE 0x00000183 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED4_PUTPTR_ACTIVE 0x00000184 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED5_PUTPTR_ACTIVE 0x00000185 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED6_PUTPTR_ACTIVE 0x00000186 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED7_PUTPTR_ACTIVE 0x00000187 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKEDT_PUTPTR_STALLED_BETWEEN_THREADS 0x00000188 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED0_PUTPTR_SENT_WITH_FE2ALL_RST_ASSERTED 0x00000189 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED1_PUTPTR_SENT_WITH_FE2ALL_RST_ASSERTED 0x0000018A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED2_PUTPTR_SENT_WITH_FE2ALL_RST_ASSERTED 0x0000018B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED3_PUTPTR_SENT_WITH_FE2ALL_RST_ASSERTED 0x0000018C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED4_PUTPTR_SENT_WITH_FE2ALL_RST_ASSERTED 0x0000018D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED5_PUTPTR_SENT_WITH_FE2ALL_RST_ASSERTED 0x0000018E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED6_PUTPTR_SENT_WITH_FE2ALL_RST_ASSERTED 0x0000018F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2SKED7_PUTPTR_SENT_WITH_FE2ALL_RST_ASSERTED 0x00000190 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2PMA_VALID 0x00000191 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2PMA_STALLED 0x00000192 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_FB2PMA_DRPD_WITH_RESET_ASSERTED 0x00000193 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_F2H_DEMOTE_ANY_FE 0x00000194 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_F2H_DEMOTE_ANY_SKED 0x00000195 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_CE0_PHYS_PEER 0x00000196 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_CE1_PHYS_PEER 0x00000197 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_CE2_PHYS_PEER 0x00000198 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_F2H_WR_FLA 0x00000199 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_F2H_RD_FLA 0x0000019A /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_F2H_GRED_FLA 0x0000019B /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_POISON_ON_H2F0 0x0000019C /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_POISON_ON_H2F1 0x0000019D /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_POISON_TO_CE0 0x0000019E /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_POISON_TO_CE1 0x0000019F /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_POISON_TO_CE2 0x000001A0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_ATR_POISON_TO_MMUFILL 0x000001A1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_RDAT_POISON_TO_MMUFILL 0x000001A2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_POISON_INTR_GENERATED 0x000001A3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_POISON_INTR_MERGED_DUE_TO_STALL 0x000001A4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_INGRESS_ACTRS_CFIFO_STALLED 0x000001A5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_INGRESS_ACTRS_CFIFO_PKT_DROPPED 0x000001A6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_VC_LL_REQ 0x000001A7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_VC_LL_GNT 0x000001A8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_VC_B_BLOCKING_VC_LL 0x000001A9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_VC_LL_BLOCKING_VC_B 0x000001AA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR0_CMD_LL 0x000001AB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR1_CMD_LL 0x000001AC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR2_CMD_LL 0x000001AD /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR3_CMD_LL 0x000001AE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_REQ_FORCE_NB 0x000001AF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_GNT_CPU_B 0x000001B0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_GNT_CPU_NB 0x000001B1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_BLOCKING 0x000001B2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WRACKORDFIFO_BLOCKING 0x000001B3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WDPORDFIFO_BLOCKING 0x000001B4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_NOT_EMPTY 0x000001B5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WRACKORDFIFO_NOT_EMPTY 0x000001B6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WDPORDFIFO_NOT_EMPTY 0x000001B7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_IN_BIND 0x000001B8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_IN_PEERINVAL 0x000001B9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_IN_SYSINVAL 0x000001BA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_IN_CLEAN_COMPTAG 0x000001BB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_IN_FLUSH_DIRTY 0x000001BC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_OUT_BIND 0x000001BD /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_OUT_PEERINVAL 0x000001BE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_OUT_SYSINVAL 0x000001BF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_OUT_CLEAN_COMPTAG 0x000001C0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_BFIFO_OUT_FLUSH_DIRTY 0x000001C1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WDAT_CNT_SNAPPED 0x000001C2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WDAT_PROCESSING_CPU_B 0x000001C3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WDAT_PROCESSING_CPU_NB 0x000001C4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WDAT_LAST_XFER 0x000001C5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WRACK_FOR_CPU_B 0x000001C6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HOSTUI_WRACK_FOR_CPU_NB 0x000001C7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_SOFTFLUSH_REQ 0x000001C8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_SOFTFLUSH_COMPL 0x000001C9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_ATSD_ARB_GNT_PORT0 0x000001E6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_ATSD_ARB_GNT_PORT1 0x000001E7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_ATSD_ARB_BUSY 0x000001E8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_ATR_REQ_PORT0 0x000001E9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_ATR_REQ_PORT1 0x000001EA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR0_LL_REQ_NO_CLR 0x000001EB /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR1_LL_REQ_NO_CLR 0x000001EC /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR2_LL_REQ_NO_CLR 0x000001ED /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR3_LL_REQ_NO_CLR 0x000001EE /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR0_LL_CREDIT_GE1 0x000001EF /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR1_LL_CREDIT_GE1 0x000001F0 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR2_LL_CREDIT_GE1 0x000001F1 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR3_LL_CREDIT_GE1 0x000001F2 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR0_LL_CREDIT_GE5 0x000001F3 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR1_LL_CREDIT_GE5 0x000001F4 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR2_LL_CREDIT_GE5 0x000001F5 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_HNIC2XBAR3_LL_CREDIT_GE5 0x000001F6 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_ADR_OF_INTEREST_ON_H2F0 0x000001F7 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_ADR_OF_INTEREST_ON_H2F1 0x000001F8 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_ADR_OF_INTEREST_ON_MMU2HUB 0x000001F9 /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_CE3_PHYS_PEER 0x000001FA /* RW--V */ #define NV_PFB_NISO_PM_INTFC_SEL2_GRP0_POISON_TO_CE3 0x000001FB /* RW--V */ #define NV_PFB_NISO_PM_FIFO 0x00100C20 /* RW-4R */ #define NV_PFB_NISO_PM_FIFO_SEL0 8:0 /* RWIVF */ #define NV_PFB_NISO_PM_FIFO_SEL0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_FIFO_SEL0_STATIC_PATTERN_0_1_GROUP 0x000001FE /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_STATIC_PATTERN_1_1_GROUP 0x000001FF /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HOST 0x000000A0 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HOST_CPU 0x000000A1 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HOST_CPU_NB 0x000000A2 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC0 0x000000A3 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC1 0x000000A4 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC2 0x000000A5 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC3 0x000000A6 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC4 0x000000A7 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC5 0x000000A8 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC6 0x000000A9 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC7 0x000000AA /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC8 0x000000AB /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC9 0x000000AC /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC10 0x000000AD /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ESC11 0x000000AE /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_P2P 0x000000AF /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_MMU 0x000000B0 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_MMU_NB 0x000000B1 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_CE0 0x000000B2 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_CE1 0x000000B3 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_CE2 0x000000B4 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_CE_SHIM 0x000000B5 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FE 0x000000B6 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FE0 0x000000B7 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FE1 0x000000B8 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FE2 0x000000B9 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FE3 0x000000BA /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FE4 0x000000BB /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FE5 0x000000BC /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FE6 0x000000BD /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FE7 0x000000BE /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SKED 0x000000BF /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SKED0 0x000000C0 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SKED1 0x000000C1 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SKED2 0x000000C2 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SKED3 0x000000C3 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SKED4 0x000000C4 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SKED5 0x000000C5 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SKED6 0x000000C6 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SKED7 0x000000C7 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SCC 0x000000C8 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SCC_NB 0x000000C9 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_PD 0x000000CA /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SEC 0x000000CB /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_GSP 0x000000CC /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_PMU 0x000000CD /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_PERF 0x000000CE /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FBFALCON 0x000000CF /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_DNISO 0x000000D0 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_DWBIF 0x000000D1 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVDEC0 0x000000D2 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVDEC1 0x000000D3 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVDEC2 0x000000D4 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVDEC3 0x000000D5 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVDEC4 0x000000D6 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVDEC5 0x000000D7 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVENC0 0x000000D8 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVENC1 0x000000D9 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVENC2 0x000000DA /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVJPG0 0x000000DB /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVJPG1 0x000000DC /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NVJPG2 0x000000DD /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_OFA0 0x000000DE /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ACTRS 0x000000DF /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RASTERTWOD 0x000000E0 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SSYNC 0x000000E1 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_PD_MSG0 0x000000E2 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_PD_MSG1 0x000000E3 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_HOST 0x000000E4 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_HOST_CPU 0x000000E5 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_HOST_CPU_NB 0x000000E6 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC0 0x000000E7 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC1 0x000000E8 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC2 0x000000E9 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC3 0x000000EA /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC4 0x000000EB /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC5 0x000000EC /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC6 0x000000ED /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC7 0x000000EE /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC8 0x000000EF /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC9 0x000000F0 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC10 0x000000F1 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ESC11 0x000000F2 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_P2P 0x000000F3 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_MMU 0x000000F4 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_MMU_NB 0x000000F5 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_CE0 0x000000F6 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_CE1 0x000000F7 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_CE2 0x000000F8 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_CE_SHIM 0x000000F9 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FE 0x000000FA /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FE0 0x000000FB /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FE1 0x000000FC /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FE2 0x000000FD /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FE3 0x000000FE /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FE4 0x000000FF /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FE5 0x00000100 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FE6 0x00000101 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FE7 0x00000102 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SKED 0x00000103 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SKED0 0x00000104 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SKED1 0x00000105 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SKED2 0x00000106 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SKED3 0x00000107 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SKED4 0x00000108 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SKED5 0x00000109 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SKED6 0x0000010A /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SKED7 0x0000010B /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SCC 0x0000010C /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SCC_NB 0x0000010D /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_PD 0x0000010E /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_SEC 0x0000010F /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_GSP 0x00000110 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_PMU 0x00000111 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_PERF 0x00000112 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_FBFALCON 0x00000113 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_DNISO 0x00000114 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_DWBIF 0x00000115 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVDEC0 0x00000116 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVDEC1 0x00000117 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVDEC2 0x00000118 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVDEC3 0x00000119 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVDEC4 0x0000011A /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVDEC5 0x0000011B /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVENC0 0x0000011C /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVENC1 0x0000011D /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVENC2 0x0000011E /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVJPG0 0x0000011F /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVJPG1 0x00000120 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_NVJPG2 0x00000121 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_OFA0 0x00000122 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_ACTRS 0x00000123 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_CE3 0x00000124 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_CE3 0x00000125 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SYSMEM_VC0_REQ0 0x0000001F /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SYSMEM_VC0_REQ1 0x00000020 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SYSMEM_VC0_REQ2 0x00000021 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SYSMEM_VC0_REQ3 0x00000022 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NISO_RRRB0 0x00000023 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NISO_RRRB1 0x00000024 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NISO_RRRB2 0x00000025 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_NISO_RRRB3 0x00000026 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ISO_RRRB0 0x00000027 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ISO_RRRB1 0x00000028 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ISO_RRRB2 0x00000029 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ISO_RRRB3 0x0000002A /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FAM_NINB 0x0000002B /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FAM 0x0000002C /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FAM_SF_HOST 0x0000002D /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FAM_SF_XVE 0x0000002E /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_XVE_RDAT 0x0000002F /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_VIP_LATENCY 0x00000030 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_TLB 0x00000031 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SYSMEM_VC1_REQ0 0x00000032 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SYSMEM_VC1_REQ1 0x00000033 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SYSMEM_VC1_REQ2 0x00000034 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_SYSMEM_VC1_REQ3 0x00000035 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT 0x00000036 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ISO_RT 0x00000037 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_XBAR2HNIC0 0x00000038 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_XBAR2HNIC1 0x00000039 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_XBAR2HNIC2 0x0000003a /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_XBAR2HNIC3 0x0000003b /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HSH2FBH0 0x00000038 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HSH2FBH1 0x00000039 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HSH2FBH2 0x0000003a /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HSH2FBH3 0x0000003b /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC2XBAR0 0x0000003c /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC2XBAR1 0x0000003d /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC2XBAR2 0x0000003e /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC2XBAR3 0x0000003f /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FBH2HSH0 0x0000003c /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FBH2HSH1 0x0000003d /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FBH2HSH2 0x0000003e /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FBH2HSH3 0x0000003f /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_OUTBUF_MSG0 0x00000040 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_OUTBUF_MSG1 0x00000041 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_OUTBUF_MSG2 0x00000042 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_OUTBUF_MSG3 0x00000043 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_INBUF_MSG0 0x00000044 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_INBUF_MSG1 0x00000045 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_INBUF_MSG2 0x00000046 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_INBUF_MSG3 0x00000047 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ITER_NINB 0x00000048 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ITER_NIB 0x00000049 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ITER_NB 0x0000004a /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ITER_B 0x0000004b /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ITER_FLUSH 0x0000004c /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC02SYSMEM_P_VC0 0x0000004d /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC12SYSMEM_P_VC0 0x0000004e /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC22SYSMEM_P_VC0 0x0000004f /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC32SYSMEM_P_VC0 0x00000050 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC02SYSMEM_P_VC1 0x00000051 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC12SYSMEM_P_VC1 0x00000052 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC22SYSMEM_P_VC1 0x00000053 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC32SYSMEM_P_VC1 0x00000054 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC02SYSMEM_NP_VC0 0x00000055 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC12SYSMEM_NP_VC0 0x00000056 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC22SYSMEM_NP_VC0 0x00000057 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC32SYSMEM_NP_VC0 0x00000058 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC02SYSMEM_NP_VC1 0x00000059 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC12SYSMEM_NP_VC1 0x0000005a /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC22SYSMEM_NP_VC1 0x0000005b /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_HNIC32SYSMEM_NP_VC1 0x0000005c /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RDP 0x0000005d /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT2RARB_COMPL 0x0000005e /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_RT_THRESHOLD 0x00000072 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_FAM_THRESHOLD 0x00000073 /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL0_ITER_LL 0x0000009B /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL1 18:10 /* RWIVF */ #define NV_PFB_NISO_PM_FIFO_SEL1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_FIFO_SEL1_STATIC_PATTERN_0_1_GROUP 0x000001FE /* RW--V */ #define NV_PFB_NISO_PM_FIFO_SEL1_STATIC_PATTERN_1_1_GROUP 0x000001FF /* RW--V */ #define NV_PFB_NISO_PM_FIFO_HNIC_INTFC 28:20 /* RWIVF */ #define NV_PFB_NISO_PM_FIFO_HNIC_INTFC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PM_FIFO_HNIC_INTFC_STATIC_PATTERN_0_1_GROUP 0x000001FE /* RW--V */ #define NV_PFB_NISO_PM_FIFO_HNIC_INTFC_STATIC_PATTERN_1_1_GROUP 0x000001FF /* RW--V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT 0x00100C30 /* RW-4R */ #define NV_PFB_NISO_SCHEDULER_WEIGHT__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_MEMBAR 3:0 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_MEMBAR_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_MSG 7:4 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_MSG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_RD 11:8 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_RD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_WR 15:12 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_WR_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_SYSMEM 19:16 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT_SYSMEM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2 0x00100C28 /* RW-4R */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_VC_NON_BLOCKING 3:0 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_VC_NON_BLOCKING_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_VC_BLOCKING 7:4 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_VC_BLOCKING_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_VC_NISO_NB 11:8 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_VC_NISO_NB_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_SCRUBBER 15:12 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_SCRUBBER_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_ATSD_ACK 19:16 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_ATSD_ACK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_VC_LL 23:20 /* RWIVF */ #define NV_PFB_NISO_SCHEDULER_WEIGHT2_VC_LL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ISO_READ_LIMITS 0x00100C34 /* RW-4R */ #define NV_PFB_NISO_ISO_READ_LIMITS_RT 9:0 /* RWIVF */ #define NV_PFB_NISO_ISO_READ_LIMITS_RT_MAX 0x00000181 /* RW--V */ #define NV_PFB_NISO_ISO_READ_LIMITS_RT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_FULL 19:10 /* RWIVF */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_FULL_MAX 0x000000B9 /* RW--V */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_FULL_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_REDUCED 29:20 /* RWIVF */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_REDUCED_IMP 0x0000005A /* RWI-V */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_REDUCED_MAX 0x000000B9 /* RW--V */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_REDUCED_ZERO 0x00000000 /* RW--V */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_DYNAMIC_SIZE 30:30 /* RWIVF */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_DYNAMIC_SIZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_DYNAMIC_SIZE_EN 0x00000001 /* RW--V */ #define NV_PFB_NISO_ISO_READ_LIMITS_RRRB_DYNAMIC_SIZE_DIS 0x00000000 /* RW--V */ #define NV_PFB_NISO_READ_LIMITS 0x00100C38 /* RW-4R */ #define NV_PFB_NISO_READ_LIMITS_RT 10:0 /* RWIVF */ #define NV_PFB_NISO_READ_LIMITS_RT_MAX 0x000007ff /* RWI-V */ #define NV_PFB_NISO_READ_LIMITS_RT_EN 11:11 /* RWIVF */ #define NV_PFB_NISO_READ_LIMITS_RT_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_NISO_READ_LIMITS_RT_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_NISO_READ_LIMITS_RRRB 22:12 /* RWIVF */ #define NV_PFB_NISO_READ_LIMITS_RRRB_MAX 0x000007ff /* RWI-V */ #define NV_PFB_NISO_READ_LIMITS_RRRB_EN 23:23 /* RWIVF */ #define NV_PFB_NISO_READ_LIMITS_RRRB_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_NISO_READ_LIMITS_RRRB_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_NISO_READ_STAT 0x00100C3C /* RW-4R */ #define NV_PFB_NISO_READ_STAT_MAX_RT_SIZE 10:0 /* R--VF */ #define NV_PFB_NISO_READ_STAT_MAX_RRRB_SIZE 22:12 /* R--VF */ #define NV_PFB_NISO_READ_STAT_MONITOR_EN 31:31 /* RWIVF */ #define NV_PFB_NISO_READ_STAT_MONITOR_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_NISO_READ_STAT_MONITOR_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_NISO_STICKY_NACK 0x00100C50 /* RW-4R */ #define NV_PFB_NISO_STICKY_NACK_ALL_CLIENTS 0:0 /* RWIVF */ #define NV_PFB_NISO_STICKY_NACK_ALL_CLIENTS_NACK 0x00000000 /* RWI-V */ #define NV_PFB_NISO_STICKY_NACK_ALL_CLIENTS_DONT 0x00000001 /* RW--V */ #define NV_PFB_NISO_STICKY_NACK_CLEAR_ALL 1:1 /* RWIVF */ #define NV_PFB_NISO_STICKY_NACK_CLEAR_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_STICKY_NACK_CLEAR_ALL_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_NISO_STICKY_NACK_BAR2_ACTRS 2:2 /* RWIVF */ #define NV_PFB_NISO_STICKY_NACK_BAR2_ACTRS_NACK 0x00000000 /* RWI-V */ #define NV_PFB_NISO_STICKY_NACK_BAR2_ACTRS_DONT 0x00000001 /* RW--V */ #define NV_PFB_NISO_CLIENT_REQ_LM0 0x00100C54 /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_LM0__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_CLIENT_REQ_LM0_CE0 3:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM0_CE0_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM0_CE1 7:4 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM0_CE1_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM0_DNISO 11:8 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM0_DNISO_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM0_FE 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM0_FE_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM0_HOST 19:16 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM0_HOST_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM0_SEC 27:24 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM0_SEC_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM0_NVDEC0 31:28 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM0_NVDEC0_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM1 0x00100C58 /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_LM1_PD 3:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM1_PD_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM1_PM 7:4 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM1_PM_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM1_PMU 11:8 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM1_PMU_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM1_PTP 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM1_PTP_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM1_SCC 19:16 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM1_SCC_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM1_NVENC2 23:20 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM1_NVENC2_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM1_VIP 27:24 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM1_VIP_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM1_NVENC1 31:28 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM1_NVENC1_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM2 0x00100C5C /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_LM2_MMU 3:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM2_MMU_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM2_HOST_NONCPU 7:4 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM2_HOST_NONCPU_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM2_SCC_NB 11:8 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM2_SCC_NB_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM2_NVENC0 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM2_NVENC0_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM2_SKED 23:20 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM2_SKED_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM2_FBFALCON 31:28 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM2_FBFALCON_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM3 0x00100000 /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_LM3_DISPNISO 3:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM3_DISPNISO_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM3_GSP 7:4 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM3_GSP_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM3_CE_SHIM 11:8 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM3_CE_SHIM_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM3_ACTRS 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM3_ACTRS_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM3_NVDEC1 19:16 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM3_NVDEC1_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_LM4 0x00100010 /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_LM4_OFA0 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_LM4_OFA0_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN0 0x00100C60 /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_MN0_CE0 3:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN0_CE0_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN0_CE1 7:4 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN0_CE1_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN0_DNISO 11:8 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN0_DNISO_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN0_FE 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN0_FE_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN0_HOST 19:16 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN0_HOST_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN0_NVENC2 23:20 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN0_NVENC2_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN0_SEC 27:24 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN0_SEC_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN0_NVDEC0 31:28 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN0_NVDEC0_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN1 0x00100C64 /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_MN1_PD 3:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN1_PD_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN1_PM 7:4 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN1_PM_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN1_PMU 11:8 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN1_PMU_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN1_PTP 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN1_PTP_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN1_SCC 19:16 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN1_SCC_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN1_NVENC2 23:20 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN1_NVENC2_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN1_VIP 27:24 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN1_VIP_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN1_NVENC1 31:28 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN1_NVENC1_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN2 0x00100C68 /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_MN2_MMU 3:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN2_MMU_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN2_HOST_NONCPU 7:4 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN2_HOST_NONCPU_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN2_SCC_NB 11:8 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN2_SCC_NB_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN2_NVENC0 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN2_NVENC0_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN2_SKED 23:20 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN2_SKED_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN2_FBFALCON 31:28 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN2_FBFALCON_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN3 0x00100004 /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_MN3_DISPNISO 3:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN3_DISPNISO_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN3_GSP 7:4 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN3_GSP_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN3_CE_SHIM 11:8 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN3_CE_SHIM_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN3_ACTRS 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN3_ACTRS_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN3_NVDEC1 19:16 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN3_NVDEC1_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_REQ_MN4 0x0010000C /* RW-4R */ #define NV_PFB_NISO_CLIENT_REQ_MN4_OFA0 15:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_REQ_MN4_OFA0_NO_LIMIT 0x0000000F /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0 0x00100C6C /* RW-4R */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE0 2:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE0_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE0_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE0_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE0_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE0_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE0_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE0_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE0_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE1 5:3 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE1_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE1_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE1_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE1_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE1_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE1_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE1_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_CE1_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_DNISO 8:6 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_DNISO_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_DNISO_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_DNISO_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_DNISO_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_DNISO_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_DNISO_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_DNISO_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_DNISO_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_FE 11:9 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_FE_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_FE_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_FE_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_FE_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_FE_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_FE_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_FE_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_FE_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST 14:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_NB 17:15 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_NB_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_NB_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_NB_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_NB_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_NB_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_NB_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_NB_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_HOST_NB_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_NVENC2 20:18 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_NVENC2_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_NVENC2_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_NVENC2_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_NVENC2_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_NVENC2_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_NVENC2_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_NVENC2_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_NVENC2_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_SEC 23:21 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_SEC_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_SEC_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_SEC_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_SEC_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_SEC_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_SEC_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_SEC_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_SEC_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PD 26:24 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PD_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PD_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PD_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PD_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PD_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PD_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PD_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PD_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PM 30:28 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PM_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PM_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PM_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PM_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PM_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PM_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PM_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM0_PM_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1 0x00100C70 /* RW-4R */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PMU 2:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PMU_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PMU_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PMU_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PMU_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PMU_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PMU_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PMU_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PMU_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVDEC0 5:3 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVDEC0_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVDEC0_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVDEC0_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVDEC0_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVDEC0_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVDEC0_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVDEC0_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVDEC0_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PTP 8:6 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PTP_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PTP_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PTP_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PTP_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PTP_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PTP_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PTP_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_PTP_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC 11:9 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC1 14:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC1_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC1_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC1_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC1_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC1_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC1_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC1_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC1_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_VIP 17:15 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_VIP_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_VIP_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_VIP_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_VIP_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_VIP_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_VIP_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_VIP_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_VIP_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_HOST_NONCPU 20:18 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_HOST_NONCPU_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_HOST_NONCPU_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_HOST_NONCPU_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_HOST_NONCPU_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_HOST_NONCPU_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_HOST_NONCPU_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_HOST_NONCPU_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_HOST_NONCPU_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_NB 23:21 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_NB_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_NB_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_NB_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_NB_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_NB_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_NB_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_NB_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_SCC_NB_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC0 26:24 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC0_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC0_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC0_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC0_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC0_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC0_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC0_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM1_NVENC0_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2 0x00100C4C /* RW-4R */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_SKED 2:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_SKED_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_SKED_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_SKED_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_SKED_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_SKED_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_SKED_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_SKED_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_SKED_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_FBFALCON 8:6 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_FBFALCON_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_FBFALCON_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_FBFALCON_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_FBFALCON_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_FBFALCON_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_FBFALCON_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_FBFALCON_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM2_FBFALCON_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3 0x00100008 /* RW-4R */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_DISPNISO 2:0 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_DISPNISO_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_DISPNISO_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_DISPNISO_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_DISPNISO_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_DISPNISO_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_DISPNISO_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_DISPNISO_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_DISPNISO_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_GSP 5:3 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_GSP_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_GSP_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_GSP_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_GSP_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_GSP_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_GSP_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_GSP_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_GSP_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_CE_SHIM 8:6 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_CE_SHIM_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_CE_SHIM_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_CE_SHIM_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_CE_SHIM_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_CE_SHIM_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_CE_SHIM_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_CE_SHIM_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_CE_SHIM_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_ACTRS 11:9 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_ACTRS_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_ACTRS_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_ACTRS_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_ACTRS_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_ACTRS_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_ACTRS_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_ACTRS_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_ACTRS_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_NVDEC1 14:12 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_NVDEC1_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_NVDEC1_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_NVDEC1_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_NVDEC1_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_NVDEC1_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_NVDEC1_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_NVDEC1_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM3_NVDEC1_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4 0x00100014 /* RW-4R */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4_OFA0 5:3 /* RWIVF */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4_OFA0_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4_OFA0_1 0x00000001 /* RWI-V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4_OFA0_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4_OFA0_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4_OFA0_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4_OFA0_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4_OFA0_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_CLIENT_MMU_REQ_LM4_OFA0_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD 0x00100C74 /* RW-4R */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ 3:0 /* RWIVF */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_1 0x00000001 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_8 0x00000008 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_9 0x00000009 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_10 0x0000000A /* RWI-V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_11 0x0000000B /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_READ_12 0x0000000C /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE 7:4 /* RWIVF */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE_1 0x00000001 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE_7 0x00000007 /* RWI-V */ #define NV_PFB_NISO_LATENCY_THRESHOLD_WRITE_8 0x00000008 /* RW--V */ #define NV_PFB_NISO_FB_INTR 0x00100C78 /* R--4R */ #define NV_PFB_NISO_FB_INTR_FBPA 16-1:0 /* R--VF */ #define NV_PFB_NISO_SYSMEM 0x00100C7C /* RW-4R */ #define NV_PFB_NISO_SYSMEM__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_SYSMEM_REQFIFO_VC0_NP 5:0 /* RWIVF */ #define NV_PFB_NISO_SYSMEM_REQFIFO_VC0_NP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_SYSMEM_REQFIFO_VC0_PW 11:6 /* RWIVF */ #define NV_PFB_NISO_SYSMEM_REQFIFO_VC0_PW_INIT 0x00000010 /* RWI-V */ #define NV_PFB_NISO_SYSMEM_REQFIFO_VC0_PW_7_6 13:12 /* RWIVF */ #define NV_PFB_NISO_SYSMEM_REQFIFO_VC0_PW_7_6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_SYSMEM_REQFIFO_VC0_NP_7_6 17:16 /* RWIVF */ #define NV_PFB_NISO_SYSMEM_REQFIFO_VC0_NP_7_6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_XV_CFG0 0x00100F00 /* RW-4R */ #define NV_PFB_XV_CFG0_CPU_ACCESS 0:0 /* RWIVF */ #define NV_PFB_XV_CFG0_CPU_ACCESS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_XV_CFG0_CPU_ACCESS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_XV_UPPER_ADDR 0x00100F04 /* RW-4R */ #define NV_PFB_XV_UPPER_ADDR_ADR_63_47 16:0 /* RWIVF */ #define NV_PFB_XV_UPPER_ADDR_ADR_63_47_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_BLK_ACT_CTRL 0x00100F10 /* RW-4R */ #define NV_PFB_NISO_BLK_ACT_CTRL_INDEX 3:0 /* RWIVF */ #define NV_PFB_NISO_BLK_ACT_CTRL_INDEX_ZERO 0 /* RWI-V */ #define NV_PFB_NISO_BLK_ACT_CTRL_INDEX_MAX 7 /* RW--V */ #define NV_PFB_NISO_BLK_ACT_CTRL_DISABLE 31:31 /* RWIVF */ #define NV_PFB_NISO_BLK_ACT_CTRL_DISABLE_ON 1 /* RW--V */ #define NV_PFB_NISO_BLK_ACT_CTRL_DISABLE_OFF 0 /* RWI-V */ #define NV_PFB_NISO_BLK_ACT_DATA 0x00100F14 /* RW-4R */ #define NV_PFB_NISO_BLK_ACT_DATA_WEIGHT 31:0 /* RWIVF */ #define NV_PFB_NISO_BLK_ACT_DATA_WEIGHT_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ISO_DEPTH_RRRB 0x00100F18 /* R--4R */ #define NV_PFB_NISO_ISO_DEPTH_RRRB_HW 9:0 /* R--VF */ #define NV_PFB_NISO_ISO_DEPTH_RRRB_PROG 19:10 /* R--VF */ #define NV_PFB_NISO_ISO_DEPTH_RRRB_USED 29:20 /* R--VF */ #define NV_PFB_NISO_ISO_DEPTH_RRRB_ENTRY_SIZE 30:30 /* R--VF */ #define NV_PFB_NISO_ISO_DEPTH_RRRB_ENTRY_SIZE_32B 0 /* R---V */ #define NV_PFB_NISO_ISO_DEPTH_RRRB_ENTRY_SIZE_64B 1 /* R---V */ #define NV_PFB_NISO_ISO_DEPTH_RRRB_CFG_ACTIVE 31:31 /* R--VF */ #define NV_PFB_NISO_ISO_DEPTH_RRRB_CFG_ACTIVE_FULL 0 /* R---V */ #define NV_PFB_NISO_ISO_DEPTH_RRRB_CFG_ACTIVE_REDUCED 1 /* R---V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG 0x00100D10 /* RWE4R */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_IDLE_CG_DLY_CNT__PROD 0x00000030 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1 0x00100D14 /* RWE4R */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1_SLCG 31:1 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1_SLCG_DISABLED 0x7FFFFFFF /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_CG1_SLCG__PROD 0x00000610 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG 0x00100D30 /* RWE4R */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_IDLE_CG_DLY_CNT__PROD 0x00000030 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG1 0x00100D34 /* RWE4R */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG1__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG 0x00100D3C /* RWE4R */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG1 0x00100D40 /* RWE4R */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG1__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_EGRESS_ISO_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG 0x00100D48 /* RWE4R */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG1 0x00100D4C /* RWE4R */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG1__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_NISO_INGRESS_ISO_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_ISO_CG 0x00100D1C /* RWE4R */ #define NV_PFB_PRI_FB_ISO_CG__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_ISO_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_PRI_FB_ISO_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_ISO_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PFB_PRI_FB_ISO_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_PRI_FB_ISO_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_ISO_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_ISO_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_ISO_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_PRI_FB_ISO_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_ISO_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_PRI_FB_ISO_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_PRI_FB_ISO_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_ISO_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_ISO_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_ISO_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_PRI_FB_ISO_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_ISO_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_PRI_FB_ISO_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_ISO_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_PRI_FB_ISO_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_PRI_FB_ISO_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_ISO_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_PRI_FB_ISO_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_FB_ISO_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_FB_ISO_CG1 0x00100D20 /* RWE4R */ #define NV_PFB_PRI_FB_ISO_CG1__PRIV_LEVEL_MASK 0x00100B34 /* */ #define NV_PFB_PRI_FB_ISO_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_PRI_FB_ISO_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_FB_ISO_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_FB_ISO_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG 0x00100D70 /* RW-4R */ #define NV_PFB_NISO_PRI_DEBUG__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_PRI_DEBUG_MMU_REQ_SHARED_DISABLE 0:0 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_MMU_REQ_SHARED_DISABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_MMU_REQ_SHARED_DISABLE_1 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_IO_CLIENT_ENABLE 1:1 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_L2B_IO_CLIENT_ENABLE_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_IO_CLIENT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_IO_CLIENT_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_IO_CLIENT_ENABLE_ON 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_MMU_FILL_ENABLE 2:2 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_L2B_MMU_FILL_ENABLE_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_MMU_FILL_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_MMU_FILL_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_MMU_FILL_ENABLE_ON 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_OOO_CLIENT_ENABLE 3:3 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_L2B_OOO_CLIENT_ENABLE_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_OOO_CLIENT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_OOO_CLIENT_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_L2B_OOO_CLIENT_ENABLE_ON 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_FAM_QUIESCENT 4:4 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_FAM_QUIESCENT_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_FAM_QUIESCENT_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_SPLIT_READ_HOLE_GE2 5:5 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_SPLIT_READ_HOLE_GE2_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_SPLIT_READ_HOLE_GE2_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_SYSMEM_STARVE_VIDMEM_FIX_EN 6:6 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_SYSMEM_STARVE_VIDMEM_FIX_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_SYSMEM_STARVE_VIDMEM_FIX_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_SYSMEM_STARVE_VIDMEM_FIX_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_VC0_READ_PASS_WRITE 7:7 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_VC0_READ_PASS_WRITE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_VC0_READ_PASS_WRITE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_PSS 8:8 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_PSS_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_PSS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_PSS_PTP 9:9 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_PSS_PTP_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_PSS_PTP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_PSS_CPU 10:10 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_PSS_CPU_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_PSS_CPU_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_ISO_BL_B2B_CLK 11:11 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_ISO_BL_B2B_CLK_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_ISO_BL_B2B_CLK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_VC0_NP_WRR_WEIGHT 15:12 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_VC0_NP_WRR_WEIGHT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_VC0_PW_WRR_WEIGHT 19:16 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_VC0_PW_WRR_WEIGHT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_VC1_NP_WRR_WEIGHT 23:20 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_VC1_NP_WRR_WEIGHT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_VC1_PW_WRR_WEIGHT 27:24 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_VC1_PW_WRR_WEIGHT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_P2P_COMPL_WRR_WEIGHT 31:28 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG_FB2XV_P2P_COMPL_WRR_WEIGHT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1 0x00100D74 /* RW-4R */ #define NV_PFB_NISO_PRI_DEBUG1__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_PRI_DEBUG1_HOL_LIMIT 7:0 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_HOL_LIMIT_INIT 255 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_THRESHOLD 10:8 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_THRESHOLD_NO_LIMIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_THRESHOLD_2 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_THRESHOLD_4 0x00000002 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_THRESHOLD_8 0x00000003 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_THRESHOLD_16 0x00000004 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_THRESHOLD_32 0x00000005 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_THRESHOLD_64 0x00000006 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_RD_WATERMARK_BIT8 11:11 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_RD_WATERMARK_BIT8_OFF 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_LIMITER 13:12 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_LIMITER_8B 0x00000001 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_WR_LIMITER_16B 0x00000002 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_PSS_FAKE_LATENCY_MODE 14:14 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_PSS_FAKE_LATENCY_MODE_IDLEONLY 0 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_PSS_FAKE_LATENCY_MODE_ALLENTRY 1 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_GPCMEMBAR_SYSFLUSH_FORCE 15:15 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_GPCMEMBAR_SYSFLUSH_FORCE_ON 1 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_GPCMEMBAR_SYSFLUSH_FORCE_OFF 0 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_PSS_FAKE_LATENCY_VALUE 19:16 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_PSS_FAKE_LATENCY_VALUE_0 0x00000000 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_PSS_FAKE_LATENCY_VALUE_3 0x00000003 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_RD_WATERMARK 27:20 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_SYSMEM_RD_WATERMARK_OFF 0x000000FF /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_CONFIG 30:28 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_CONFIG_0 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_CONFIG_1 0x00000001 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_CONFIG_2 0x00000002 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_CONFIG_3 0x00000003 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_CONFIG_4 0x00000004 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_CONFIG_5 0x00000005 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_CONFIG_6 0x00000006 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_CONFIG_7 0x00000007 /* RW--V */ #define NV_PFB_NISO_PRI_DEBUG1_DEBUG_BUS_EN 31:31 /* RWIVF */ #define NV_PFB_NISO_PRI_DEBUG1_DEBUG_BUS_EN_OFF 0x00000000 /* RWI-V */ #define NV_PFB_NISO_PRI_DEBUG1_DEBUG_BUS_EN_ON 0x00000001 /* RW--V */ #define NV_PFB_NISO_DEBUG 0x00100D78 /* R--4R */ #define NV_PFB_NISO_DEBUG_BUS 31:0 /* R-IVF */ #define NV_PFB_NISO_DEBUG_BUS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_NISO_PRI_LIMITS 0x00100D7C /* RW-4R */ #define NV_PFB_NISO_PRI_LIMITS__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_PRI_LIMITS_NISO_RT 3:0 /* RWIVF */ #define NV_PFB_NISO_PRI_LIMITS_NISO_RT_INIT 0 /* RWI-V */ #define NV_PFB_NISO_PRI_LIMITS_NISO_RRRB 7:4 /* RWIVF */ #define NV_PFB_NISO_PRI_LIMITS_NISO_RRRB_INIT 0 /* RWI-V */ #define NV_PFB_NISO_PRI_LIMITS_ISO_RT 11:8 /* RWIVF */ #define NV_PFB_NISO_PRI_LIMITS_ISO_RT_INIT 0 /* RWI-V */ #define NV_PFB_NISO_PRI_LIMITS_ISO_RRRB 15:12 /* RWIVF */ #define NV_PFB_NISO_PRI_LIMITS_ISO_RRRB_INIT 0 /* RWI-V */ #define NV_PFB_NISO_PRI_LIMITS_NISO_FAM 19:16 /* RWIVF */ #define NV_PFB_NISO_PRI_LIMITS_NISO_FAM_INIT 0 /* RWI-V */ #define NV_PFB_NISO_PRI_LIMITS_NISO_QUIESCENT 23:20 /* RWIVF */ #define NV_PFB_NISO_PRI_LIMITS_NISO_QUIESCENT_INIT 0xa /* RWI-V */ #define NV_PFB_NISO_PRI_LIMITS_QUIESCENT_SYSMEM_READ 28:28 /* RWIVF */ #define NV_PFB_NISO_PRI_LIMITS_QUIESCENT_SYSMEM_READ_EN 1 /* RWI-V */ #define NV_PFB_NISO_PRI_LIMITS_QUIESCENT_SYSMEM_READ_DIS 0 /* RW--V */ #define NV_PFB_NISO_PRI_LIMITS_CYA_RESERVED 31:29 /* RWIVF */ #define NV_PFB_NISO_PRI_LIMITS_CYA_RESERVED_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0 0x00100040 /* RW-4R */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0_CE 7:0 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0_CE_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0_CESHIM 15:8 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0_CESHIM_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0_FE 23:16 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0_FE_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0_PD 31:24 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT0_PD_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1 0x00100044 /* RW-4R */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1_HOST_CPU 7:0 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1_HOST_CPU_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1_HOST_CPU_NB 15:8 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1_HOST_CPU_NB_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1_HOST_NONCPU 23:16 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1_HOST_NONCPU_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1_PMU 31:24 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT1_PMU_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2 0x00100048 /* RW-4R */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2_NVDEC 7:0 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2_NVDEC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2_NVENC 15:8 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2_NVENC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2_NVJPG 23:16 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2_NVJPG_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2_SEC 31:24 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT2_SEC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3 0x0010004C /* RW-4R */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3_P2P 7:0 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3_P2P_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3_SCC 15:8 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3_SCC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3_SCC_NB 23:16 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3_SCC_NB_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3_SKED 31:24 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT3_SKED_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4 0x00100050 /* RW-4R */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4_FBFALCON 7:0 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4_FBFALCON_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4_DISPNISO 15:8 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4_DISPNISO_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4_GSP 23:16 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4_GSP_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4_ESC 31:24 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT4_ESC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5 0x00100054 /* RW-4R */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5_OFA 7:0 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5_OFA_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5_RESERVED0 15:8 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5_RESERVED0_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5_RESERVED1 23:16 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5_RESERVED1_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5_RESERVED2 31:24 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT5_RESERVED2_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT6 0x00100058 /* RW-4R */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT6__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT6_MMU 7:0 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT6_MMU_INIT 0 /* RWI-V */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT6_MMU_NB 15:8 /* RWIVF */ #define NV_PFB_NISO_RRRB_CLIENT_LIMIT6_MMU_NB_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0 0x00100060 /* RW-4R */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0_CE 7:0 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0_CE_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0_CESHIM 15:8 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0_CESHIM_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0_FE 23:16 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0_FE_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0_PD 31:24 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT0_PD_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1 0x00100064 /* RW-4R */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1_HOST_CPU 7:0 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1_HOST_CPU_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1_HOST_CPU_NB 15:8 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1_HOST_CPU_NB_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1_HOST_NONCPU 23:16 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1_HOST_NONCPU_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1_PMU 31:24 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT1_PMU_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2 0x00100068 /* RW-4R */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2_NVDEC 7:0 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2_NVDEC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2_NVENC 15:8 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2_NVENC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2_NVJPG 23:16 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2_NVJPG_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2_SEC 31:24 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT2_SEC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3 0x0010006C /* RW-4R */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3_P2P 7:0 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3_P2P_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3_SCC 15:8 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3_SCC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3_SCC_NB 23:16 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3_SCC_NB_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3_SKED 31:24 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT3_SKED_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4 0x00100070 /* RW-4R */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4_FBFALCON 7:0 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4_FBFALCON_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4_DISPNISO 15:8 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4_DISPNISO_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4_GSP 23:16 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4_GSP_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4_ESC 31:24 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT4_ESC_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5 0x00100074 /* RW-4R */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5__PRIV_LEVEL_MASK 0x00100B38 /* */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5_OFA 7:0 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5_OFA_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5_PERF 15:8 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5_PERF_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5_ACTRS 23:16 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5_ACTRS_INIT 0 /* RWI-V */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5_RESERVED 31:24 /* RWIVF */ #define NV_PFB_NISO_ROB_CLIENT_LIMIT5_RESERVED_INIT 0 /* RWI-V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK 0x00100B10 /* RW-4R */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pfb_niso_scrub" /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PFB_NISO_SCRUB_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PFB_NISO_SCRUB_START_ADDR 0x00100B14 /* RW-4R */ #define NV_PFB_NISO_SCRUB_START_ADDR__PRIV_LEVEL_MASK 0x00100B10 /* */ #define NV_PFB_NISO_SCRUB_START_ADDR_B43_12 31:0 /* RWIVF */ #define NV_PFB_NISO_SCRUB_START_ADDR_B43_12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_SCRUB_ADDR_LO 0x00100B14 /* RW-4P */ #define NV_PFB_NISO_SCRUB_ADDR_LO__PRIV_LEVEL_MASK 0x00100B10 /* */ #define NV_PFB_NISO_SCRUB_ADDR_LO_B43_12 31:0 /* RWIVF */ #define NV_PFB_NISO_SCRUB_ADDR_LO_B43_12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_SCRUB_END_ADDR 0x00100B18 /* RW-4R */ #define NV_PFB_NISO_SCRUB_END_ADDR__PRIV_LEVEL_MASK 0x00100B10 /* */ #define NV_PFB_NISO_SCRUB_END_ADDR_B43_12 31:0 /* RWIVF */ #define NV_PFB_NISO_SCRUB_END_ADDR_B43_12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_SCRUB_ADDR_HI 0x00100B18 /* RW-4P */ #define NV_PFB_NISO_SCRUB_ADDR_HI__PRIV_LEVEL_MASK 0x00100B10 /* */ #define NV_PFB_NISO_SCRUB_ADDR_HI_B43_12 31:0 /* RWIVF */ #define NV_PFB_NISO_SCRUB_ADDR_HI_B43_12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_SCRUB_TRIGGER 0x00100B1C /* RW-4R */ #define NV_PFB_NISO_SCRUB_TRIGGER__PRIV_LEVEL_MASK 0x00100B10 /* */ #define NV_PFB_NISO_SCRUB_TRIGGER_FLAG 0:0 /* RWIVF */ #define NV_PFB_NISO_SCRUB_TRIGGER_FLAG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_NISO_SCRUB_TRIGGER_FLAG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_NISO_SCRUB_TRIGGER_DIRECTION 1:1 /* RWIVF */ #define NV_PFB_NISO_SCRUB_TRIGGER_DIRECTION_LOW_TO_HIGH 0x0 /* RWI-V */ #define NV_PFB_NISO_SCRUB_TRIGGER_DIRECTION_HIGH_TO_LOW 0x1 /* RW--V */ #define NV_PFB_NISO_SCRUB_STATUS 0x00100B20 /* R--4R */ #define NV_PFB_NISO_SCRUB_STATUS__PRIV_LEVEL_MASK 0x00100B10 /* */ #define NV_PFB_NISO_SCRUB_STATUS_FLAG 0:0 /* R-IVF */ #define NV_PFB_NISO_SCRUB_STATUS_FLAG_DONE 0x00000001 /* R-I-V */ #define NV_PFB_NISO_SCRUB_STATUS_FLAG_PENDING 0x00000000 /* R---V */ #define NV_PFB_NISO_SCRUB_LAST_ADDR_STATUS 0x00100B24 /* R--4R */ #define NV_PFB_NISO_SCRUB_LAST_ADDR_STATUS_B43_12 31:0 /* R-IVF */ #define NV_PFB_NISO_SCRUB_LAST_ADDR_STATUS_B43_12_INIT 0x00000000 /* R-I-V */ #define NV_PFB_NISO_SCRUB_MAX_PENDING_REQUEST_SIZE 0x00200000 /* */ #define NV_PFB_NISO_SCRUB_ADDR_HI_STATUS 0x00100B24 /* R--4P */ #define NV_PFB_NISO_SCRUB_ADDR_HI_STATUS_B43_12 31:0 /* R-IVF */ #define NV_PFB_NISO_SCRUB_ADDR_HI_STATUS_B43_12_INIT 0x00000000 /* R-I-V */ #define NV_PFB_NISO_SCRUB_PATTERN 0x00100B28 /* RW-4R */ #define NV_PFB_NISO_SCRUB_PATTERN__PRIV_LEVEL_MASK 0x00100B10 /* */ #define NV_PFB_NISO_SCRUB_PATTERN_FIELD 31:0 /* RWIVF */ #define NV_PFB_NISO_SCRUB_PATTERN_FIELD_ALL_ZEROS 0x00000000 /* RWI-V */ #define NV_PFB_NISO_SCRUB_PATTERN_FIELD_ALL_ONES 0xFFFFFFFF /* RW--V */ #define NV_PFB_NISO_SCRUB_START_ADDR_STATUS 0x00100B2C /* R--4R */ #define NV_PFB_NISO_SCRUB_START_ADDR_STATUS_B43_12 31:0 /* R-IVF */ #define NV_PFB_NISO_SCRUB_START_ADDR_STATUS_B43_12_INIT 0x00000000 /* R-I-V */ #define NV_PFB_NISO_SCRUB_ADDR_LO_STATUS 0x00100B2C /* R--4P */ #define NV_PFB_NISO_SCRUB_ADDR_LO_STATUS_B43_12 31:0 /* R-IVF */ #define NV_PFB_NISO_SCRUB_ADDR_LO_STATUS_B43_12_INIT 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_HW_CFG_ACR 0x00100B50 /* R--4R */ #define NV_PFB_NISO_ENCRYPTION_HW_CFG_ACR_FIELD 31:0 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_HW_CFG_ACR_FIELD_INIT 0x0000000E /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_HW_CFG_ACR_IS_VPR 0x00100B54 /* R--4R */ #define NV_PFB_NISO_ENCRYPTION_HW_CFG_ACR_IS_VPR_FIELD 31:0 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_HW_CFG_ACR_IS_VPR_FIELD_INIT 0x00000008 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID 0x00100B58 /* R--4R */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG1 1:1 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG1_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG1_TRUE 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG2 2:2 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG2_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG2_TRUE 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG3 3:3 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG3_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG3_TRUE 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG(i) (i):(i) /* */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG__SIZE_1 32 /* */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG_FALSE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG_TRUE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID 0x00100B5C /* R--4R */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG1 1:1 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG1_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG1_TRUE 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG2 2:2 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG2_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG2_TRUE 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG3 3:3 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG3_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG3_TRUE 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG(i) (i):(i) /* */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG__SIZE_1 32 /* */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG_FALSE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG_TRUE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_REGION_SUBCOUNTER(i) (0x00100900+(i)*4) /* R--4A */ #define NV_PFB_NISO_ENCRYPTION_REGION_SUBCOUNTER__SIZE_1 8 /* */ #define NV_PFB_NISO_ENCRYPTION_REGION_SUBCOUNTER_FIELD 31:0 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_REGION_SUBCOUNTER_FIELD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CLIENT(i) (0x00100940+(i)*4) /* R--4A */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CLIENT__SIZE_1 8 /* */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CLIENT_FIELD 31:0 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CLIENT_FIELD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE 0x00100B68 /* R--4R */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_GC_OVERFLOW 0:0 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_GC_OVERFLOW_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_GC_OVERFLOW_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_INVALID_READ 1:1 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_INVALID_READ_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_INVALID_READ_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_INVALID_WRITE 2:2 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_INVALID_WRITE_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_INVALID_WRITE_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_ENCRYPTION_DISABLED 3:3 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_ENCRYPTION_DISABLED_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_ENCRYPTION_DISABLED_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_KEY_IS_ZERO 4:4 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_KEY_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_KEY_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_NONCE_IS_ZERO 5:5 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_NONCE_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_NONCE_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_INVALID_VPR_PAGEIN_GC 6:6 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0 0x00100B6C /* R--4R */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_GC_OVERFLOW 0:0 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_GC_OVERFLOW_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_GC_OVERFLOW_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_READ 1:1 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_READ_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_READ_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_WRITE 2:2 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_WRITE_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_WRITE_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_ENCRYPTION_DISABLED 3:3 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_ENCRYPTION_DISABLED_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_ENCRYPTION_DISABLED_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_KEY_IS_ZERO 4:4 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_KEY_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_KEY_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_NONCE_IS_ZERO 5:5 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_NONCE_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_NONCE_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_VPR_PAGEIN_GC 6:6 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1 0x00100B70 /* R--4R */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_GC_OVERFLOW 0:0 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_GC_OVERFLOW_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_GC_OVERFLOW_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_READ 1:1 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_READ_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_READ_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_WRITE 2:2 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_WRITE_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_WRITE_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_ENCRYPTION_DISABLED 3:3 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_ENCRYPTION_DISABLED_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_ENCRYPTION_DISABLED_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_KEY_IS_ZERO 4:4 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_KEY_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_KEY_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_NONCE_IS_ZERO 5:5 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_NONCE_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_NONCE_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_VPR_PAGEIN_GC 6:6 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0 0x00100B74 /* R--4R */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_GC_OVERFLOW 0:0 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_GC_OVERFLOW_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_GC_OVERFLOW_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_READ 1:1 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_READ_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_READ_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_WRITE 2:2 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_WRITE_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_WRITE_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_ENCRYPTION_DISABLED 3:3 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_ENCRYPTION_DISABLED_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_ENCRYPTION_DISABLED_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_KEY_IS_ZERO 4:4 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_KEY_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_KEY_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_NONCE_IS_ZERO 5:5 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_NONCE_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_NONCE_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_VPR_PAGEIN_GC 6:6 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1 0x00100B78 /* R--4R */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_GC_OVERFLOW 0:0 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_GC_OVERFLOW_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_GC_OVERFLOW_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_READ 1:1 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_READ_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_READ_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_WRITE 2:2 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_WRITE_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_WRITE_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_ENCRYPTION_DISABLED 3:3 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_ENCRYPTION_DISABLED_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_ENCRYPTION_DISABLED_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_KEY_IS_ZERO 4:4 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_KEY_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_KEY_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_NONCE_IS_ZERO 5:5 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_NONCE_IS_ZERO_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_NONCE_IS_ZERO_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_VPR_PAGEIN_GC 6:6 /* R-IVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* R---V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK 0x00100B84 /* RW-4R */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PFB_NISO_ENCRYPTION_SET_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0 0x00100B7C /* -W-4R */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0__PRIV_LEVEL_MASK 0x00100B84 /* */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_GC_OVERFLOW 0:0 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_GC_OVERFLOW_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_GC_OVERFLOW_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_INVALID_READ 1:1 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_INVALID_READ_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_INVALID_READ_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_INVALID_WRITE 2:2 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_INVALID_WRITE_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_INVALID_WRITE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_ENCRYPTION_DISABLED 3:3 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_ENCRYPTION_DISABLED_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_ENCRYPTION_DISABLED_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_KEY_IS_ZERO 4:4 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_KEY_IS_ZERO_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_KEY_IS_ZERO_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_NONCE_IS_ZERO 5:5 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_NONCE_IS_ZERO_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_NONCE_IS_ZERO_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_INVALID_VPR_PAGEIN_GC 6:6 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ0_INVALID_VPR_PAGEIN_GC_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1 0x00100B80 /* -W-4R */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1__PRIV_LEVEL_MASK 0x00100B84 /* */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_GC_OVERFLOW 0:0 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_GC_OVERFLOW_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_GC_OVERFLOW_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_INVALID_READ 1:1 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_INVALID_READ_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_INVALID_READ_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_INVALID_WRITE 2:2 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_INVALID_WRITE_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_INVALID_WRITE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_ENCRYPTION_DISABLED 3:3 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_ENCRYPTION_DISABLED_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_ENCRYPTION_DISABLED_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_KEY_IS_ZERO 4:4 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_KEY_IS_ZERO_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_KEY_IS_ZERO_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_NONCE_IS_ZERO 5:5 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_NONCE_IS_ZERO_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_NONCE_IS_ZERO_INIT 0x00000000 /* -WI-V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_INVALID_VPR_PAGEIN_GC 6:6 /* -WIVF */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* -W--V */ #define NV_PFB_NISO_ENCRYPTION_ERROR_SET_IRQ1_INVALID_VPR_PAGEIN_GC_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBHUB_MEM_PARTITION_BOTTOM 0x00100B88 /* RW-4R */ #define NV_PFB_FBHUB_MEM_PARTITION_BOTTOM_PER_SLICE 19:0 /* RWIVF */ #define NV_PFB_FBHUB_MEM_PARTITION_BOTTOM_PER_SLICE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_MEM_PARTITION_MIDDLE 0x00100B8C /* RW-4R */ #define NV_PFB_FBHUB_MEM_PARTITION_MIDDLE_PER_SLICE 19:0 /* RWIVF */ #define NV_PFB_FBHUB_MEM_PARTITION_MIDDLE_PER_SLICE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_MEM_PARTITION_ATOM_SIZE 4096 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_ATOM_SIZE_LG2 0xC /* */ #define NV_PFB_FBHUB_MEM_PARTITION_BOUNDARY_CFG0 0x00100B90 /* RW-4R */ #define NV_PFB_FBHUB_MEM_PARTITION_BOUNDARY_CFG0_VAL 10:0 /* RWIVF */ #define NV_PFB_FBHUB_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT 0x00000603 /* RWI-V */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_0 0x603 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_1 0x423 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_2 0x621 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_3 0x40B /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_4 0x429 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_5 0x4A1 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_6 0x681 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_7 0x407 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_8 0x40D /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_9 0x419 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_10 0x431 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_11 0x461 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_12 0x4C1 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_13 0x581 /* */ #define NV_PFB_FBHUB_MEM_PARTITION_SWIZID_MASK_14 0x701 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK 0x00100B9C /* RW-4R */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RWI-V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000C /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PFB_FBHUB_SYSPIPE_HALT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_ENTRY(i) (0x00100BA0+(i)*4) /* RW-4A */ #define NV_PFB_FBHUB_SYSPIPE_HALT_ENTRY__SIZE_1 8 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_ENTRY__PRIV_LEVEL_MASK 0x00100B9C /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_ENTRY_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBHUB_SYSPIPE_HALT_ENTRY_TRIGGER_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_ENTRY_TRIGGER_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_READY(i) (0x00100BC0+(i)*4) /* R--4A */ #define NV_PFB_FBHUB_SYSPIPE_HALT_READY__SIZE_1 8 /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_READY__PRIV_LEVEL_MASK 0x00100B9C /* */ #define NV_PFB_FBHUB_SYSPIPE_HALT_READY_STATUS 0:0 /* R-IVF */ #define NV_PFB_FBHUB_SYSPIPE_HALT_READY_STATUS_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBHUB_SYSPIPE_HALT_READY_STATUS_DONE 0x00000001 /* R---V */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG 0x00100B94 /* RW-4R */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER(i) (((i)*4)+1):((i)*4) /* */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x00000000 /* */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x00000000 /* */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x00000001 /* */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x00000002 /* */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x00000003 /* */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 1 /* */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWIUF */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWIUF */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWIUF */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWIUF */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWIUF */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWIUF */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWIUF */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWIUF */ #define NV_PFB_FBHUB_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_SYSMEM_HSHUB_CONNECTION_CFG 0x00100B98 /* RW-4R */ #define NV_PFB_FBHUB_SYSMEM_HSHUB_CONNECTION_CFG_SYS 1:0 /* RWIUF */ #define NV_PFB_FBHUB_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0 0x00000001 /* RW--V */ #define NV_PFB_FBHUB_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1 0x00000002 /* RW--V */ #define NV_PFB_FBHUB_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS 0x00000003 /* RW--V */ #define NV_PFB_FBHUB_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE 0x00000003 /* RW--V */ #define NV_PFB_FBHUB_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG(i) (0x0011A000+(i)*4) /* RW-4A */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG__SIZE_1 64 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_THRESHOLD 15:0 /* RWIVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_THRESHOLD_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY 17:16 /* RWIVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_64K 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_2M 0x00000001 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16M 0x00000002 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16G 0x00000003 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY 19:18 /* RWIVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_64K 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_2M 0x00000001 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16M 0x00000002 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16G 0x00000003 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_GVA_NOTIFY 20:20 /* RWIVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_GVA_NOTIFY_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_GVA_NOTIFY_FALSE 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_COUNT_PD 30:30 /* RWIVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_COUNT_PD_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_COUNT_PD_FALSE 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_COUNT_PCIE 31:31 /* RWIVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_COUNT_PCIE_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_CONFIG_COUNT_PCIE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG 0x00100A00 /* RW-4R */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_THRESHOLD 15:0 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_THRESHOLD_INIT 0x00000080 /* RWI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY 17:16 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_64K 0x00000000 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_2M 0x00000001 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16M 0x00000002 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16G 0x00000003 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY 19:18 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_64K 0x00000000 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_2M 0x00000001 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16M 0x00000002 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16G 0x00000003 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_USE_LIMIT 29:28 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_USE_LIMIT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_USE_LIMIT_NONE 0x00000000 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_USE_LIMIT_QTR 0x00000001 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_USE_LIMIT_HALF 0x00000002 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MIMC_USE_LIMIT_FULL 0x00000003 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_USE_LIMIT 31:30 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_USE_LIMIT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_USE_LIMIT_NONE 0x00000000 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_USE_LIMIT_QTR 0x00000001 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_USE_LIMIT_HALF 0x00000002 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG_MOMC_USE_LIMIT_FULL 0x00000003 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2 0x00100A3C /* RW-4R */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2_COUNT_PD 0:0 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2_COUNT_PD_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2_COUNT_PD_FALSE 0x00000000 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2_COUNT_PCIE 1:1 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2_COUNT_PCIE_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2_COUNT_PCIE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2_DROP_PCIE 2:2 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2_DROP_PCIE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_CONFIG2_DROP_PCIE_FALSE 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_LO(i) (0x0011A400+(i)*4) /* RW-4A */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_LO__SIZE_1 64 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN 0:0 /* RWIVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_FALSE 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_TRUE 0x00000001 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE_RESET 0x00000000 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00100A04 /* RW-4R */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN 0:0 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_FALSE 0x00000000 /* RWI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_TRUE 0x00000001 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE_RESET 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_HI(i) (0x0011A800+(i)*4) /* RW-4A */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_HI__SIZE_1 64 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE 31:0 /* RWXVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE_RESET 0x00000000 /* RW--V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x00100A08 /* RW-4R */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE 31:0 /* RWXVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE_RESET 0x00000000 /* RW--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE(i) (0x0011AC00+(i)*4) /* R--4A */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE__SIZE_1 64 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_FIELD 31:0 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW 12:0 /* R-IUF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW_ENTRIES 4096 /* R-I-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE 0x00100A0C /* R--4R */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_FIELD 31:0 /* */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW 12:0 /* R-IUF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW_ENTRIES 4096 /* R-I-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_GET(i) (0x0011B000+(i)*4) /* RW-4A */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_GET__SIZE_1 64 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET 31:0 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW 11:0 /* RWIVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_GET 0x00100A10 /* RW-4R */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET 31:0 /* */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW 11:0 /* RWIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_PUT(i) (0x0011B400+(i)*4) /* R--4A */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_PUT__SIZE_1 64 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET 31:0 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW 11:0 /* R-IVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_PUT 0x00100A14 /* R--4R */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET 31:0 /* */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW 11:0 /* R-IVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO(i) (0x0011B800+(i)*4) /* R--4A */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO__SIZE_1 64 /* */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL 0:0 /* R-IVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_FALSE 0x0 /* R-I-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE 0x1 /* R---V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED 1:1 /* R-IVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_FALSE 0x0 /* R---V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_TRUE 0x1 /* R-I-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK 24:24 /* R-IVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_FALSE 0x0 /* R-I-V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE 0x1 /* R---V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO 0x00100A18 /* R--4R */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL 0:0 /* R-IVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_FALSE 0x0 /* R-I-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE 0x1 /* R---V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED 1:1 /* R-IVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_FALSE 0x0 /* R---V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_TRUE 0x1 /* R-I-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK 24:24 /* R-IVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_FALSE 0x0 /* R-I-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE 0x1 /* R---V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR 0x00100A1C /* -W-4R */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_MIMC 0:0 /* -WIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_MIMC_INIT 0x0 /* -WI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_MIMC_CLR 0x1 /* -W--V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_MOMC 1:1 /* -WIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_MOMC_INIT 0x0 /* -WI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_MOMC_CLR 0x1 /* -W--V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_ALL_COUNTERS 2:2 /* -WIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_ALL_COUNTERS_INIT 0x0 /* -WI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_ALL_COUNTERS_CLR 0x1 /* -W--V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK 31:31 /* -WIVF */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK_INIT 0x0 /* -WI-V */ #define NV_PFB_NISO_ACCESS_COUNTER_NOTIFY_BUFFER_CLR_WRITE_NACK_CLR 0x1 /* -W--V */ #define NV_PFB_FBHUB_ACCESS_COUNTER_INTR_VECTOR 0x00100A20 /* R--4R */ #define NV_PFB_FBHUB_ACCESS_COUNTER_INTR_VECTOR_HW 7:0 /* R-IVF */ #define NV_PFB_FBHUB_ACCESS_COUNTER_INTR_VECTOR_HW_INIT 72 /* R-I-V */ #define NV_PFB_FBHUB_POISON_INTR_VECTOR 0x00100A24 /* R--4R */ #define NV_PFB_FBHUB_POISON_INTR_VECTOR_HW 7:0 /* R-IVF */ #define NV_PFB_FBHUB_POISON_INTR_VECTOR_HW_INIT 135 /* R-I-V */ #define NV_PFB_FBHUB_PEER_SUPPORT 0x00100A40 /* RW-4R */ #define NV_PFB_FBHUB_PEER_SUPPORT_GFID 7:0 /* RWIVF */ #define NV_PFB_FBHUB_PEER_SUPPORT_GFID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_PRI_MMU_CTRL 0x00100C80 /* RWE4R */ #define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE_64KB 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_COMP_FAULT 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_COMP_FAULT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_COMP_FAULT_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_MISS_GRAN 4:3 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_FULL 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_HALF 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_QUARTER 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_CACHE_MODE 6:5 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_ON 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_CACHE_MODE_OFF 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE 8:7 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_ON 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_EVICT_SMPG_PARTIALS 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_EVICT_ALL_PARTIALS 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_PDE_CACHE_MODE_OFF 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_L2_SEND_MODE 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_WORK_CREATION_DISABLE 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_WORK_CREATION_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_WORK_CREATION_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_CLEAR 13:13 /* -WEVF */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_CLEAR_FALSE 0x00000000 /* -WE-V */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_CLEAR_TRUE 0x00000001 /* -W--T */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR 14:14 /* R-EVF */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_FALSE 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_ERROR_TRUE 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY 15:15 /* R-EVF */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY_FALSE 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_EMPTY_TRUE 0x00000001 /* R-E-V */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE 23:16 /* R-EVF */ #define NV_PFB_PRI_MMU_CTRL_PRI_FIFO_SPACE_INIT 32 /* R-E-V */ #define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE 25:24 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA 26:26 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE 27:27 /* RWEVF */ #define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PM 0x00100C84 /* RWE4R */ #define NV_PFB_PRI_MMU_PM_SELECT 8:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_00 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_01 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_02 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_03 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_04 0x00000004 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_05 0x00000005 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_06 0x00000006 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_07 0x00000007 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_08 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_09 0x00000009 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_0A 0x0000000A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_0B 0x0000000B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_0C 0x0000000C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_0D 0x0000000D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_0E 0x0000000E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_0F 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_10 0x00000010 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_11 0x00000011 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_12 0x00000012 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_13 0x00000013 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_14 0x00000014 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_15 0x00000015 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_16 0x00000016 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_17 0x00000017 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_18 0x00000018 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_19 0x00000019 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A 0x0000001A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B 0x0000001B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C 0x0000001C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D 0x0000001D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E 0x0000001E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F 0x0000001F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_20 0x00000020 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_21 0x00000021 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_22 0x00000022 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_23 0x00000023 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_24 0x00000024 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_25 0x00000025 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_26 0x00000026 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_27 0x00000027 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_28 0x00000028 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_29 0x00000029 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_2A 0x0000002A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_2B 0x0000002B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_2C 0x0000002C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_2D 0x0000002D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_2E 0x0000002E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_2F 0x0000002F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_30 0x00000030 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_31 0x00000031 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_32 0x00000032 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_33 0x00000033 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_34 0x00000034 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_35 0x00000035 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_36 0x00000036 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_37 0x00000037 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_38 0x00000038 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_39 0x00000039 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_3A 0x0000003A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_3B 0x0000003B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_3C 0x0000003C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_3D 0x0000003D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_3E 0x0000003E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_3F 0x0000003F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_40 0x00000040 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_41 0x00000041 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_42 0x00000042 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_43 0x00000043 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_44 0x00000044 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_45 0x00000045 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_46 0x00000046 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_47 0x00000047 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_48 0x00000048 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_49 0x00000049 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_4A 0x0000004A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_4B 0x0000004B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_4C 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_4D 0x0000004D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_4E 0x0000004E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_4F 0x0000004F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_50 0x00000050 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_51 0x00000051 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_52 0x00000052 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_53 0x00000053 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_54 0x00000054 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_55 0x00000055 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_56 0x00000056 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_57 0x00000057 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_58 0x00000058 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_59 0x00000059 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_5A 0x0000005A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_5B 0x0000005B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_5C 0x0000005C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_5D 0x0000005D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_5E 0x0000005E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_5F 0x0000005F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_60 0x00000060 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_61 0x00000061 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_62 0x00000062 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_63 0x00000063 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_64 0x00000064 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_65 0x00000065 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_66 0x00000066 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_67 0x00000067 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_68 0x00000068 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_69 0x00000069 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_6A 0x0000006A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_6B 0x0000006B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_6C 0x0000006C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_6D 0x0000006D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_6E 0x0000006E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_6F 0x0000006F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_70 0x00000070 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_71 0x00000071 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_72 0x00000072 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_73 0x00000073 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_74 0x00000074 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_75 0x00000075 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_76 0x00000076 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_77 0x00000077 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_78 0x00000078 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_79 0x00000079 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_7A 0x0000007A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_7B 0x0000007B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_7C 0x0000007C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_7D 0x0000007D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_7E 0x0000007E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_7F 0x0000007F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_80 0x00000080 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_81 0x00000081 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_82 0x00000082 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_83 0x00000083 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_84 0x00000084 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_85 0x00000085 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_86 0x00000086 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_87 0x00000087 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_88 0x00000088 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_89 0x00000089 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_8A 0x0000008A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_8B 0x0000008B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_8C 0x0000008C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_8D 0x0000008D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_8E 0x0000008E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_8F 0x0000008F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_90 0x00000090 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_91 0x00000091 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_92 0x00000092 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_93 0x00000093 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_94 0x00000094 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_95 0x00000095 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_96 0x00000096 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_97 0x00000097 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_98 0x00000098 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_99 0x00000099 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_9A 0x0000009A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_9B 0x0000009B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_9C 0x0000009C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_9D 0x0000009D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_9E 0x0000009E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_9F 0x0000009F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A0 0x000000A0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A1 0x000000A1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A2 0x000000A2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A3 0x000000A3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A4 0x000000A4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A5 0x000000A5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A6 0x000000A6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A7 0x000000A7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A8 0x000000A8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_A9 0x000000A9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_AA 0x000000AA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_AB 0x000000AB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_AC 0x000000AC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_AD 0x000000AD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_AE 0x000000AE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_AF 0x000000AF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B0 0x000000B0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B1 0x000000B1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B2 0x000000B2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B3 0x000000B3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B4 0x000000B4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B5 0x000000B5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B6 0x000000B6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B7 0x000000B7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B8 0x000000B8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_B9 0x000000B9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_BA 0x000000BA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_BB 0x000000BB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_BC 0x000000BC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_BD 0x000000BD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_BE 0x000000BE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_BF 0x000000BF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C0 0x000000C0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C1 0x000000C1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C2 0x000000C2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C3 0x000000C3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C4 0x000000C4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C5 0x000000C5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C6 0x000000C6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C7 0x000000C7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C8 0x000000C8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_C9 0x000000C9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_CA 0x000000CA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_CB 0x000000CB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_CC 0x000000CC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_CD 0x000000CD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_CE 0x000000CE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_CF 0x000000CF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D0 0x000000D0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D1 0x000000D1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D2 0x000000D2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D3 0x000000D3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D4 0x000000D4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D5 0x000000D5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D6 0x000000D6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D7 0x000000D7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D8 0x000000D8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_D9 0x000000D9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_DA 0x000000DA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_DB 0x000000DB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_DC 0x000000DC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_DD 0x000000DD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_DE 0x000000DE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_DF 0x000000DF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E0 0x000000E0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E1 0x000000E1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E2 0x000000E2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E3 0x000000E3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E4 0x000000E4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E5 0x000000E5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E6 0x000000E6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E7 0x000000E7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E8 0x000000E8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_E9 0x000000E9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_EA 0x000000EA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_EB 0x000000EB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_EC 0x000000EC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_ED 0x000000ED /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_EE 0x000000EE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_EF 0x000000EF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F0 0x000000F0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F1 0x000000F1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F2 0x000000F2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F3 0x000000F3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F4 0x000000F4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F5 0x000000F5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F6 0x000000F6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F7 0x000000F7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F8 0x000000F8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_F9 0x000000F9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_FA 0x000000FA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_FB 0x000000FB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_FC 0x000000FC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_FD 0x000000FD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x000000FE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x000000FF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_100 0x00000100 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_101 0x00000101 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_102 0x00000102 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_103 0x00000103 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_104 0x00000104 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_105 0x00000105 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_106 0x00000106 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_107 0x00000107 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_108 0x00000108 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_109 0x00000109 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_10A 0x0000010A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_10B 0x0000010B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_10C 0x0000010C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_10D 0x0000010D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_10E 0x0000010E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_10F 0x0000010F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_110 0x00000110 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_111 0x00000111 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_112 0x00000112 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_113 0x00000113 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_114 0x00000114 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_115 0x00000115 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_116 0x00000116 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_117 0x00000117 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_118 0x00000118 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_119 0x00000119 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_11A 0x0000011A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_11B 0x0000011B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_11C 0x0000011C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_11D 0x0000011D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_11E 0x0000011E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_11F 0x0000011F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_120 0x00000120 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_121 0x00000121 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_122 0x00000122 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_123 0x00000123 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_124 0x00000124 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_125 0x00000125 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_126 0x00000126 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_127 0x00000127 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_128 0x00000128 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_129 0x00000129 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_12A 0x0000012A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_12B 0x0000012B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_12C 0x0000012C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_12D 0x0000012D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_12E 0x0000012E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_12F 0x0000012F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_130 0x00000130 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_131 0x00000131 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_132 0x00000132 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_133 0x00000133 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_134 0x00000134 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_135 0x00000135 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_136 0x00000136 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_137 0x00000137 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_138 0x00000138 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_139 0x00000139 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_13A 0x0000013A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_13B 0x0000013B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_13C 0x0000013C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_13D 0x0000013D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_13E 0x0000013E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_13F 0x0000013F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_140 0x00000140 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_141 0x00000141 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_142 0x00000142 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_143 0x00000143 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_144 0x00000144 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_145 0x00000145 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_146 0x00000146 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_147 0x00000147 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_148 0x00000148 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_149 0x00000149 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_14A 0x0000014A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_14B 0x0000014B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_14C 0x0000014C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_14D 0x0000014D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_14E 0x0000014E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_14F 0x0000014F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_150 0x00000150 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_151 0x00000151 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_152 0x00000152 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_153 0x00000153 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_154 0x00000154 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_155 0x00000155 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_156 0x00000156 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_157 0x00000157 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_158 0x00000158 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_159 0x00000159 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_15A 0x0000015A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_15B 0x0000015B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_15C 0x0000015C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_15D 0x0000015D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_15E 0x0000015E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_15F 0x0000015F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_160 0x00000160 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_161 0x00000161 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_162 0x00000162 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_163 0x00000163 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_164 0x00000164 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_165 0x00000165 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_166 0x00000166 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_167 0x00000167 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_168 0x00000168 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_169 0x00000169 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_16A 0x0000016A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_16B 0x0000016B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_16C 0x0000016C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_16D 0x0000016D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_16E 0x0000016E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_16F 0x0000016F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_170 0x00000170 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_171 0x00000171 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_172 0x00000172 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_173 0x00000173 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_174 0x00000174 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_175 0x00000175 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_176 0x00000176 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_177 0x00000177 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_178 0x00000178 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_179 0x00000179 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_17A 0x0000017A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_17B 0x0000017B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_17C 0x0000017C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_17D 0x0000017D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_17E 0x0000017E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_17F 0x0000017F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_180 0x00000180 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_181 0x00000181 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_182 0x00000182 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_183 0x00000183 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_184 0x00000184 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_185 0x00000185 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_186 0x00000186 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_187 0x00000187 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_188 0x00000188 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_189 0x00000189 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_18A 0x0000018A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_18B 0x0000018B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_18C 0x0000018C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_18D 0x0000018D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_18E 0x0000018E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_18F 0x0000018F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_190 0x00000190 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_191 0x00000191 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_192 0x00000192 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_193 0x00000193 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_194 0x00000194 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_195 0x00000195 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_196 0x00000196 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_197 0x00000197 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_198 0x00000198 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_199 0x00000199 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_19A 0x0000019A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_19B 0x0000019B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_19C 0x0000019C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_19D 0x0000019D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_19E 0x0000019E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_19F 0x0000019F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A0 0x000001A0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A1 0x000001A1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A2 0x000001A2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A3 0x000001A3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A4 0x000001A4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A5 0x000001A5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A6 0x000001A6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A7 0x000001A7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A8 0x000001A8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1A9 0x000001A9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AA 0x000001AA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AB 0x000001AB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AC 0x000001AC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AD 0x000001AD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AE 0x000001AE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1AF 0x000001AF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B0 0x000001B0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B1 0x000001B1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B2 0x000001B2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B3 0x000001B3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B4 0x000001B4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B5 0x000001B5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B6 0x000001B6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B7 0x000001B7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B8 0x000001B8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1B9 0x000001B9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BA 0x000001BA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BB 0x000001BB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BC 0x000001BC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BD 0x000001BD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BE 0x000001BE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1BF 0x000001BF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C0 0x000001C0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C1 0x000001C1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C2 0x000001C2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C3 0x000001C3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C4 0x000001C4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C5 0x000001C5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C6 0x000001C6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C7 0x000001C7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C8 0x000001C8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1C9 0x000001C9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CA 0x000001CA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CB 0x000001CB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CC 0x000001CC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CD 0x000001CD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CE 0x000001CE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1CF 0x000001CF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D0 0x000001D0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D1 0x000001D1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D2 0x000001D2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D3 0x000001D3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D4 0x000001D4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D5 0x000001D5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D6 0x000001D6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D7 0x000001D7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D8 0x000001D8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1D9 0x000001D9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DA 0x000001DA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DB 0x000001DB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DC 0x000001DC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DD 0x000001DD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DE 0x000001DE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1DF 0x000001DF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E0 0x000001E0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E1 0x000001E1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E2 0x000001E2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E3 0x000001E3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E4 0x000001E4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E5 0x000001E5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E6 0x000001E6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E7 0x000001E7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E8 0x000001E8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1E9 0x000001E9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EA 0x000001EA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EB 0x000001EB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EC 0x000001EC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1ED 0x000001ED /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EE 0x000001EE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1EF 0x000001EF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F0 0x000001F0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F1 0x000001F1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F2 0x000001F2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F3 0x000001F3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F4 0x000001F4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F5 0x000001F5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F6 0x000001F6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F7 0x000001F7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F8 0x000001F8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1F9 0x000001F9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FA 0x000001FA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FB 0x000001FB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FC 0x000001FC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FD 0x000001FD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FE 0x000001FE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_GRP_1FF 0x000001FF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1 24:16 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_00 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_01 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_02 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_03 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_04 0x00000004 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_05 0x00000005 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_06 0x00000006 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_07 0x00000007 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_08 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_09 0x00000009 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0A 0x0000000A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0B 0x0000000B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0C 0x0000000C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0D 0x0000000D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0E 0x0000000E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_0F 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10 0x00000010 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11 0x00000011 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12 0x00000012 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13 0x00000013 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14 0x00000014 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15 0x00000015 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16 0x00000016 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17 0x00000017 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18 0x00000018 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19 0x00000019 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A 0x0000001A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B 0x0000001B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C 0x0000001C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D 0x0000001D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E 0x0000001E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F 0x0000001F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_20 0x00000020 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_21 0x00000021 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_22 0x00000022 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_23 0x00000023 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_24 0x00000024 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_25 0x00000025 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_26 0x00000026 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_27 0x00000027 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_28 0x00000028 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_29 0x00000029 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2A 0x0000002A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2B 0x0000002B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2C 0x0000002C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2D 0x0000002D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2E 0x0000002E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_2F 0x0000002F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_30 0x00000030 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_31 0x00000031 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_32 0x00000032 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_33 0x00000033 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_34 0x00000034 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_35 0x00000035 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_36 0x00000036 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_37 0x00000037 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_38 0x00000038 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_39 0x00000039 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3A 0x0000003A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3B 0x0000003B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3C 0x0000003C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3D 0x0000003D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3E 0x0000003E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_3F 0x0000003F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_40 0x00000040 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_41 0x00000041 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_42 0x00000042 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_43 0x00000043 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_44 0x00000044 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_45 0x00000045 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_46 0x00000046 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_47 0x00000047 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_48 0x00000048 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_49 0x00000049 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4A 0x0000004A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4B 0x0000004B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4C 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4D 0x0000004D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4E 0x0000004E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_4F 0x0000004F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_50 0x00000050 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_51 0x00000051 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_52 0x00000052 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_53 0x00000053 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_54 0x00000054 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_55 0x00000055 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_56 0x00000056 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_57 0x00000057 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_58 0x00000058 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_59 0x00000059 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5A 0x0000005A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5B 0x0000005B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5C 0x0000005C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5D 0x0000005D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5E 0x0000005E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_5F 0x0000005F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_60 0x00000060 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_61 0x00000061 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_62 0x00000062 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_63 0x00000063 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_64 0x00000064 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_65 0x00000065 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_66 0x00000066 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_67 0x00000067 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_68 0x00000068 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_69 0x00000069 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6A 0x0000006A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6B 0x0000006B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6C 0x0000006C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6D 0x0000006D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6E 0x0000006E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_6F 0x0000006F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_70 0x00000070 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_71 0x00000071 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_72 0x00000072 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_73 0x00000073 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_74 0x00000074 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_75 0x00000075 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_76 0x00000076 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_77 0x00000077 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_78 0x00000078 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_79 0x00000079 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7A 0x0000007A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7B 0x0000007B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7C 0x0000007C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7D 0x0000007D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7E 0x0000007E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_7F 0x0000007F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_80 0x00000080 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_81 0x00000081 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_82 0x00000082 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_83 0x00000083 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_84 0x00000084 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_85 0x00000085 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_86 0x00000086 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_87 0x00000087 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_88 0x00000088 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_89 0x00000089 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8A 0x0000008A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8B 0x0000008B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8C 0x0000008C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8D 0x0000008D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8E 0x0000008E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_8F 0x0000008F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_90 0x00000090 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_91 0x00000091 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_92 0x00000092 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_93 0x00000093 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_94 0x00000094 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_95 0x00000095 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_96 0x00000096 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_97 0x00000097 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_98 0x00000098 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_99 0x00000099 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9A 0x0000009A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9B 0x0000009B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9C 0x0000009C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9D 0x0000009D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9E 0x0000009E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_9F 0x0000009F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A0 0x000000A0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A1 0x000000A1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A2 0x000000A2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A3 0x000000A3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A4 0x000000A4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A5 0x000000A5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A6 0x000000A6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A7 0x000000A7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A8 0x000000A8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_A9 0x000000A9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AA 0x000000AA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AB 0x000000AB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AC 0x000000AC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AD 0x000000AD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AE 0x000000AE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_AF 0x000000AF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B0 0x000000B0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B1 0x000000B1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B2 0x000000B2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B3 0x000000B3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B4 0x000000B4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B5 0x000000B5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B6 0x000000B6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B7 0x000000B7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B8 0x000000B8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_B9 0x000000B9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BA 0x000000BA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BB 0x000000BB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BC 0x000000BC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BD 0x000000BD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BE 0x000000BE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_BF 0x000000BF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C0 0x000000C0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C1 0x000000C1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C2 0x000000C2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C3 0x000000C3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C4 0x000000C4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C5 0x000000C5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C6 0x000000C6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C7 0x000000C7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C8 0x000000C8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_C9 0x000000C9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CA 0x000000CA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CB 0x000000CB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CC 0x000000CC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CD 0x000000CD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CE 0x000000CE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_CF 0x000000CF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D0 0x000000D0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D1 0x000000D1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D2 0x000000D2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D3 0x000000D3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D4 0x000000D4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D5 0x000000D5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D6 0x000000D6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D7 0x000000D7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D8 0x000000D8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_D9 0x000000D9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DA 0x000000DA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DB 0x000000DB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DC 0x000000DC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DD 0x000000DD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DE 0x000000DE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_DF 0x000000DF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E0 0x000000E0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E1 0x000000E1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E2 0x000000E2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E3 0x000000E3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E4 0x000000E4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E5 0x000000E5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E6 0x000000E6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E7 0x000000E7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E8 0x000000E8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_E9 0x000000E9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EA 0x000000EA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EB 0x000000EB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EC 0x000000EC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_ED 0x000000ED /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EE 0x000000EE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_EF 0x000000EF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F0 0x000000F0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F1 0x000000F1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F2 0x000000F2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F3 0x000000F3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F4 0x000000F4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F5 0x000000F5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F6 0x000000F6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F7 0x000000F7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F8 0x000000F8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_F9 0x000000F9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FA 0x000000FA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FB 0x000000FB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FC 0x000000FC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_FD 0x000000FD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP 0x000000FE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP 0x000000FF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_100 0x00000100 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_101 0x00000101 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_102 0x00000102 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_103 0x00000103 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_104 0x00000104 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_105 0x00000105 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_106 0x00000106 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_107 0x00000107 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_108 0x00000108 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_109 0x00000109 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10A 0x0000010A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10B 0x0000010B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10C 0x0000010C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10D 0x0000010D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10E 0x0000010E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_10F 0x0000010F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_110 0x00000110 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_111 0x00000111 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_112 0x00000112 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_113 0x00000113 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_114 0x00000114 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_115 0x00000115 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_116 0x00000116 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_117 0x00000117 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_118 0x00000118 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_119 0x00000119 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11A 0x0000011A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11B 0x0000011B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11C 0x0000011C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11D 0x0000011D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11E 0x0000011E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_11F 0x0000011F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_120 0x00000120 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_121 0x00000121 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_122 0x00000122 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_123 0x00000123 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_124 0x00000124 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_125 0x00000125 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_126 0x00000126 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_127 0x00000127 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_128 0x00000128 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_129 0x00000129 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12A 0x0000012A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12B 0x0000012B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12C 0x0000012C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12D 0x0000012D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12E 0x0000012E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_12F 0x0000012F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_130 0x00000130 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_131 0x00000131 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_132 0x00000132 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_133 0x00000133 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_134 0x00000134 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_135 0x00000135 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_136 0x00000136 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_137 0x00000137 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_138 0x00000138 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_139 0x00000139 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13A 0x0000013A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13B 0x0000013B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13C 0x0000013C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13D 0x0000013D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13E 0x0000013E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_13F 0x0000013F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_140 0x00000140 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_141 0x00000141 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_142 0x00000142 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_143 0x00000143 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_144 0x00000144 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_145 0x00000145 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_146 0x00000146 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_147 0x00000147 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_148 0x00000148 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_149 0x00000149 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14A 0x0000014A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14B 0x0000014B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14C 0x0000014C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14D 0x0000014D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14E 0x0000014E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_14F 0x0000014F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_150 0x00000150 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_151 0x00000151 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_152 0x00000152 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_153 0x00000153 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_154 0x00000154 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_155 0x00000155 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_156 0x00000156 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_157 0x00000157 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_158 0x00000158 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_159 0x00000159 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15A 0x0000015A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15B 0x0000015B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15C 0x0000015C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15D 0x0000015D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15E 0x0000015E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_15F 0x0000015F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_160 0x00000160 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_161 0x00000161 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_162 0x00000162 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_163 0x00000163 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_164 0x00000164 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_165 0x00000165 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_166 0x00000166 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_167 0x00000167 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_168 0x00000168 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_169 0x00000169 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16A 0x0000016A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16B 0x0000016B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16C 0x0000016C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16D 0x0000016D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16E 0x0000016E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_16F 0x0000016F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_170 0x00000170 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_171 0x00000171 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_172 0x00000172 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_173 0x00000173 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_174 0x00000174 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_175 0x00000175 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_176 0x00000176 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_177 0x00000177 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_178 0x00000178 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_179 0x00000179 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17A 0x0000017A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17B 0x0000017B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17C 0x0000017C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17D 0x0000017D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17E 0x0000017E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_17F 0x0000017F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_180 0x00000180 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_181 0x00000181 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_182 0x00000182 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_183 0x00000183 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_184 0x00000184 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_185 0x00000185 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_186 0x00000186 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_187 0x00000187 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_188 0x00000188 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_189 0x00000189 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18A 0x0000018A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18B 0x0000018B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18C 0x0000018C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18D 0x0000018D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18E 0x0000018E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_18F 0x0000018F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_190 0x00000190 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_191 0x00000191 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_192 0x00000192 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_193 0x00000193 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_194 0x00000194 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_195 0x00000195 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_196 0x00000196 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_197 0x00000197 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_198 0x00000198 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_199 0x00000199 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19A 0x0000019A /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19B 0x0000019B /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19C 0x0000019C /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19D 0x0000019D /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19E 0x0000019E /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_19F 0x0000019F /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A0 0x000001A0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A1 0x000001A1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A2 0x000001A2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A3 0x000001A3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A4 0x000001A4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A5 0x000001A5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A6 0x000001A6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A7 0x000001A7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A8 0x000001A8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1A9 0x000001A9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AA 0x000001AA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AB 0x000001AB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AC 0x000001AC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AD 0x000001AD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AE 0x000001AE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1AF 0x000001AF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B0 0x000001B0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B1 0x000001B1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B2 0x000001B2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B3 0x000001B3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B4 0x000001B4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B5 0x000001B5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B6 0x000001B6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B7 0x000001B7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B8 0x000001B8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1B9 0x000001B9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BA 0x000001BA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BB 0x000001BB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BC 0x000001BC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BD 0x000001BD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BE 0x000001BE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1BF 0x000001BF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C0 0x000001C0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C1 0x000001C1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C2 0x000001C2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C3 0x000001C3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C4 0x000001C4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C5 0x000001C5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C6 0x000001C6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C7 0x000001C7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C8 0x000001C8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1C9 0x000001C9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CA 0x000001CA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CB 0x000001CB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CC 0x000001CC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CD 0x000001CD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CE 0x000001CE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1CF 0x000001CF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D0 0x000001D0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D1 0x000001D1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D2 0x000001D2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D3 0x000001D3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D4 0x000001D4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D5 0x000001D5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D6 0x000001D6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D7 0x000001D7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D8 0x000001D8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1D9 0x000001D9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DA 0x000001DA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DB 0x000001DB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DC 0x000001DC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DD 0x000001DD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DE 0x000001DE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1DF 0x000001DF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E0 0x000001E0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E1 0x000001E1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E2 0x000001E2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E3 0x000001E3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E4 0x000001E4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E5 0x000001E5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E6 0x000001E6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E7 0x000001E7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E8 0x000001E8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1E9 0x000001E9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EA 0x000001EA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EB 0x000001EB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EC 0x000001EC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1ED 0x000001ED /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EE 0x000001EE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1EF 0x000001EF /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F0 0x000001F0 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F1 0x000001F1 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F2 0x000001F2 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F3 0x000001F3 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F4 0x000001F4 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F5 0x000001F5 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F6 0x000001F6 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F7 0x000001F7 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F8 0x000001F8 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1F9 0x000001F9 /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FA 0x000001FA /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FB 0x000001FB /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FC 0x000001FC /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FD 0x000001FD /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FE 0x000001FE /* RW--V */ #define NV_PFB_PRI_MMU_PM_SELECT_MUX1_GRP_1FF 0x000001FF /* RW--V */ #define NV_PFB_PRI_MMU_PM_ALT_INPUT 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_ALT_INPUT_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PM_ALT_INPUT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_ALT_INPUT_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_BLK_ACT 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_BLK_ACT_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PM_BLK_ACT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_BLK_ACT_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_ENABLE 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PM_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_ADDR_LOW 0x00100C88 /* RWE4R */ #define NV_PFB_PRI_MMU_PM_ADDR_LOW_BITS 31:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_ADDR_LOW_ALIGNMENT 0x00000008 /* */ #define NV_PFB_PRI_MMU_PM_ADDR_HIGH 0x00100C8C /* RWE4R */ #define NV_PFB_PRI_MMU_PM_ADDR_HIGH_BITS 31:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_ADDR_HIGH_ALIGNMENT 0x00000008 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK 0x001FA7C0 /* RWE4R */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0000005C /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK 0x001FA7D0 /* RW-4R */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0000005C /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK 0x001FA7CC /* RW-4R */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK 0x001FA7C8 /* RW-4R */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK 0x001FA7C4 /* RW-4R */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK 0x001FA7D4 /* RW-4R */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_OFA_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK 0x001FA7D8 /* RW-4R */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK 0x001FA7DC /* RW-4R */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK 0x001FA7E0 /* RW-4R */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_NVDEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK 0x001FA7E4 /* RW-4R */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_NVENC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK 0x001FA7E8 /* RW-4R */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_NVJPG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK 0x001FA7EC /* RW-4R */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_GSP_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK 0x001FA7F0 /* RW-4R */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FECS_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK 0x001FA7F4 /* RW-4R */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_GPCCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK 0x001FA7F8 /* RW-4R */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FBFALCON_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_TLB_CTRL 0x00100CA4 /* RW-4R */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_SIZE 1:0 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_FA_SIZE 3:2 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_FA_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_RB_SIZE 5:4 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SIZE 7:6 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_FA_SIZE 9:8 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_FA_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_RB_SIZE 11:10 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_PTE 13:12 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_PTE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_PDE 15:14 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_PDE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_RB 17:16 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_FILL_SIZE_RB_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_SET_INDEX_BIG_PG 19:18 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_SET_INDEX_BIG_PG_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SET_INDEX_BIG_PG 21:20 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SET_INDEX_BIG_PG_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_SET_INDEX_SMALL_PG 23:22 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_L2_SET_INDEX_SMALL_PG_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SET_INDEX_SMALL_PG 25:24 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_HUB_SET_INDEX_SMALL_PG_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_ATSD_PROP_FLUSH 26:26 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_ATSD_PROP_FLUSH_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_ATSD_PROP_FLUSH_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_TLB_CTRL_INVAL_PROP_FLUSH 27:27 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_INVAL_PROP_FLUSH_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_INVAL_PROP_FLUSH_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_TLB_CTRL_BIND_PROP_FLUSH 28:28 /* RWEVF */ #define NV_PFB_PRI_MMU_TLB_CTRL_BIND_PROP_FLUSH_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_TLB_CTRL_BIND_PROP_FLUSH_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_RSRVD 0x00100CA8 /* RW-4R */ #define NV_PFB_PRI_MMU_RSRVD_FILL_PTE_CL_VC_B 2:0 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_FILL_PTE_CL_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_FILL_PTE_CL_VC_NB 5:3 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_FILL_PTE_CL_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_FILL_RB_VC_B 8:6 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_FILL_RB_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_FILL_RB_VC_NB 11:9 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_FILL_RB_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_CL_VC_B 14:12 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_CL_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_CL_VC_NB 17:15 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_CL_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_RB_VC_B 20:18 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_RB_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_RB_VC_NB 23:21 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_RB_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_FAST_BIG_PG_FAULT_DISABLE 26:26 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_FAST_BIG_PG_FAULT_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_RSRVD_FAST_BIG_PG_FAULT_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_FAST_PATH_DISABLE 28:28 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_HUBTLB_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_RSRVD_L2TLB_FAST_PATH_DISABLE 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_L2TLB_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_L2TLB_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_RSRVD_FILL_FAST_PATH_DISABLE 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_FILL_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_FILL_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_RSRVD_IGNORE_INVALIDATES 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_RSRVD_IGNORE_INVALIDATES_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_RSRVD_IGNORE_INVALIDATES_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL 0x00100CF8 /* RW-4R */ #define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER 1:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_ALL 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_NONE 0x00000003 /* RWE-V */ #define NV_PFB_PRI_MMU_BIND_IMB 0x00100CAC /* RW-4R */ #define NV_PFB_PRI_MMU_BIND_IMB_APERTURE 1:0 /* RWXVF */ #define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_VID_MEM 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_INVALID 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_SYS_MEM_C 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_IMB_APERTURE_SYS_MEM_NC 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_IMB_VOL 2:2 /* RWXVF */ #define NV_PFB_PRI_MMU_BIND_IMB_VOL_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_IMB_VOL_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_IMB_ADDR 31:4 /* RWXVF */ #define NV_PFB_PRI_MMU_BIND_IMB_ADDR_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_BIND 0x00100CB0 /* RW-4R */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID 7:0 /* RWEVF */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_GRAPHICS 64 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_RESERVED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_DISPLAY 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_GSP 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_FLA 0x00000004 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_BAR1 128 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_BAR2 192 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PMU 0x00000006 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_AUDIO 0x00000007 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_PM 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_IFB 0x00000009 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVDEC 0x0000000a /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVENC 0x0000000b /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVENC0 0x0000000b /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVENC1 0x0000000c /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_NVENC2 0x0000000d /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_SEC 0x0000000e /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE0 0x0000000f /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE1 0x00000010 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE2 0x00000011 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE3 0x00000012 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE4 0x00000013 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE5 0x00000014 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE6 0x00000015 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE7 0x00000016 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_CE8 0x00000017 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST0 0x00000020 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST1 0x00000021 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST2 0x00000022 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST3 0x00000023 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST4 0x00000024 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST5 0x00000025 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST6 0x00000026 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST7 0x00000027 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST8 0x00000028 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST9 0x00000029 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST10 0x0000002a /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST11 0x0000002b /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST12 0x0000002c /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST13 0x0000002d /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST14 0x0000002e /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST15 0x0000002f /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_HOST16 0x00000020 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID0 0x00000040 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID1 0x00000041 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID2 0x00000042 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID3 0x00000043 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID4 0x00000044 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID5 0x00000045 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID6 0x00000046 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID7 0x00000047 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID8 0x00000048 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID9 0x00000049 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID10 0x0000004a /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID11 0x0000004b /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID12 0x0000004c /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID13 0x0000004d /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID14 0x0000004e /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID15 0x0000004f /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID16 0x00000050 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID17 0x00000051 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID18 0x00000052 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID19 0x00000053 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID20 0x00000054 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID21 0x00000055 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID22 0x00000056 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID23 0x00000057 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID24 0x00000058 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID25 0x00000059 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID26 0x0000005a /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID27 0x0000005b /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID28 0x0000005c /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID29 0x0000005d /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID30 0x0000005e /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID31 0x0000005f /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID32 0x00000060 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID33 0x00000061 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID34 0x00000062 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID35 0x00000063 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID36 0x00000064 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID37 0x00000065 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID38 0x00000066 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID39 0x00000067 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID40 0x00000068 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID41 0x00000069 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID42 0x0000006a /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID43 0x0000006b /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID44 0x0000006c /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID45 0x0000006d /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID46 0x0000006e /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID47 0x0000006f /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID48 0x00000070 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID49 0x00000071 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID50 0x00000072 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID51 0x00000073 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID52 0x00000074 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID53 0x00000075 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID54 0x00000076 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID55 0x00000077 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID56 0x00000078 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID57 0x00000079 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID58 0x0000007a /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID59 0x0000007b /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID60 0x0000007c /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID61 0x0000007d /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID62 0x0000007e /* RW--V */ #define NV_PFB_PRI_MMU_BIND_ENGINE_ID_VEID63 0x0000007f /* RW--V */ #define NV_PFB_PRI_MMU_BIND_UPPER_IMB_ADDR 25:8 /* RWEVF */ #define NV_PFB_PRI_MMU_BIND_UPPER_IMB_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_BIND_UNBIND_TYPE 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_BIND_UNBIND_TYPE_ALL 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_BIND_UNBIND_TYPE_SMC_LOCAL 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_TRIGGER 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_BIND_TRIGGER_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_BIND_TRIGGER_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_BIND_EXT 0x00100ED8 /* RW-4R */ #define NV_PFB_PRI_MMU_BIND_EXT_GFID 5:0 /* RWEVF */ #define NV_PFB_PRI_MMU_BIND_EXT_GFID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_BIND_EXT_SMC_ID 30:28 /* RWEVF */ #define NV_PFB_PRI_MMU_BIND_EXT_SMC_ID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VADDR 0x00100CB4 /* RW-4R */ #define NV_PFB_PRI_MMU_INVALIDATE_VADDR_BITS 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VADDR_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VADDR_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR 0x00100CE8 /* RW-4R */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_BITS 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB 0x00100CB8 /* RW-4R */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_ADDR_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB 0x00100CEC /* RW-4R */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_ADDR 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_PASID 0x00100E64 /* RW-4R */ #define NV_PFB_PRI_MMU_INVALIDATE_PASID_VAL 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_PASID_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE 0x00100E68 /* RW-4R */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VAL 5:0 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_GFID 31:26 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_GFID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE 0x00100CBC /* RW-4R */ #define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_REPLAY 5:3 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_NONE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR 6:6 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_ACK 8:7 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_ACK_INTRANODE 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_ACK_GLOBALLY 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_ID 14:9 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_INVAL_SCOPE 16:15 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_INVAL_SCOPE_LINK_TLBS 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE 20:20 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_USE_PASID 21:21 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_USE_PASID_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_USE_PASID_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_USE_SIZE 22:22 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_USE_SIZE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_USE_SIZE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_PROP_FLUSH 23:23 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_PROP_FLUSH_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_PROP_FLUSH_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL 26:24 /* RWXVF */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 0x00000004 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 0x00000005 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 0x00000006 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 0x00000007 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_READ 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_STRONG 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_RSVRVD 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_WEAK 0x00000004 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_ALL 0x00000005 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE_AND_ATOMIC 0x00000006 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ALL 0x00000007 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_MAX_CACHELINE_SIZE 0x00000010 /* */ #define NV_PFB_PRI_MMU_PREFETCH 0x00100CC0 /* RW-4R */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_DISABLE 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_BIG_DISABLE 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_BIG_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_BIG_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_UNFILLED_DISABLE 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_UNFILLED_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_UNFILLED_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_ENGINE 5:3 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_ENGINE_ALL 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_ENGINE_CE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_ENGINE_VID 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_ENGINE_PB 0x00000004 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE0 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE0_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE0_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE1 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE1_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE1_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE2 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE2_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_SA_FILL_CE2_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_ENABLE 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE 14:13 /* RWEVF */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_1 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_2 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_4 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_8 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_CTRL 0x00100CC4 /* RW-4R */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_WR_KIND 7:0 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_RD_KIND 15:8 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE 18:17 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_128KB 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_1MB 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_WR 0x00100CC8 /* RW-4R */ #define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE 1:0 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_PEER_MEM 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_WR_VOL 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_WR_VOL_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_WR_VOL_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_WR_ADDR 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_APERTURE 1:0 /* */ #define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_APERTURE_VID_MEM 0x00000000 /* */ #define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_APERTURE_SYS_MEM_C 0x00000002 /* */ #define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_APERTURE_SYS_MEM_NC 0x00000003 /* */ #define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_VOL 2:2 /* */ #define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_VOL_FALSE 0x00000000 /* */ #define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_VOL_TRUE 0x00000001 /* */ #define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_ADDR 31:4 /* */ #define NV_PFB_PRI_MMU_DEBUG_WR_FLA_IMB_ADDR_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_DEBUG_RD 0x00100CCC /* RW-4R */ #define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE 1:0 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_PEER_MEM 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_RD_VOL 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_RD_VOL_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_RD_VOL_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_DEBUG_RD_ADDR 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_DEBUG_RD_FLA_UPPER_IMB_ADDR 25:8 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK 0x00100EF4 /* RW-4R */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST 0x00100EF0 /* RW-4R */ #define NV_PFB_PRI_MMU_ADDR_INTEREST__PRIV_LEVEL_MASK 0x00100EF4 /* */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_ENABLE 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_ENABLE_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_SEC_REQ 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_SEC_REQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_ADDR_INTEREST_SEC_REQ_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UPPER_ADDR_LOW 0x00100CF0 /* RW-4R */ #define NV_PFB_PRI_MMU_PM_UPPER_ADDR_LOW_BITS 23:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UPPER_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UPPER_ADDR_HIGH 0x00100CF4 /* RW-4R */ #define NV_PFB_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS 23:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_STATE 0x001FA834 /* RWE4R */ #define NV_PFB_PRI_MMU_VPR_STATE__PRIV_LEVEL_MASK 0x001FA7C0 /* */ #define NV_PFB_PRI_MMU_VPR_STATE_PROTECTED_MODE 0:0 /* RWXVF */ #define NV_PFB_PRI_MMU_VPR_STATE_PROTECTED_MODE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_STATE_PROTECTED_MODE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE 0x001FA800 /* RW-4R */ #define NV_PFB_PRI_MMU_VPR_MODE__PRIV_LEVEL_MASK 0x001FA7D0 /* */ #define NV_PFB_PRI_MMU_VPR_MODE_FETCH 2:2 /* RWXVF */ #define NV_PFB_PRI_MMU_VPR_MODE_FETCH_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_FETCH_INIT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_FETCH_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_UPDATE_MODE 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_UPDATE_MODE_FALSE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_UPDATE_MODE_TRUE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_UPDATE_MODE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_PROTECTED_MODE 4:4 /* RWXVF */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_PROTECTED_MODE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_PROTECTED_MODE_INIT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_PROTECTED_MODE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_MEMORY_LOCKED 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_MEMORY_LOCKED_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_MEMORY_LOCKED_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_MEMORY_LOCKED_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_NON_COMPRESSIBLE 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_NON_COMPRESSIBLE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_NON_COMPRESSIBLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_NON_COMPRESSIBLE_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_SYSWR_WHEN_MEMORY_LOCKED 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_SYSWR_WHEN_MEMORY_LOCKED_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_SYSWR_WHEN_MEMORY_LOCKED_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_SYSWR_WHEN_MEMORY_LOCKED_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_MEMORY_LOCK_FUSE 8:8 /* R-XVF */ #define NV_PFB_PRI_MMU_VPR_MODE_MEMORY_LOCK_FUSE_FALSE 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_VPR_MODE_MEMORY_LOCK_FUSE_TRUE 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_VPR_MODE_WPR_COMPRESSIBLE 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_WPR_COMPRESSIBLE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_WPR_COMPRESSIBLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_WPR_COMPRESSIBLE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_SECURE_LOCK 12:12 /* R-XVF */ #define NV_PFB_PRI_MMU_VPR_MODE_SECURE_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_VPR_MODE_SECURE_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_VPR_MODE_WPR_WITH_SECURE_LOCK 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_WPR_WITH_SECURE_LOCK_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_WPR_WITH_SECURE_LOCK_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_WPR_WITH_SECURE_LOCK_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_SEC_FAULT_FUSE 14:14 /* R-XVF */ #define NV_PFB_PRI_MMU_VPR_MODE_SEC_FAULT_FUSE_FALSE 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_VPR_MODE_SEC_FAULT_FUSE_TRUE 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_VPR_MODE_FORCE_SPA_EQUAL_GPA 20:20 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_FORCE_SPA_EQUAL_GPA_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_FORCE_SPA_EQUAL_GPA_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_FORCE_SPA_EQUAL_GPA_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_FAULT_REPORT 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_FAULT_REPORT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_FAULT_REPORT_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_FAULT_REPORT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_HWPM 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_HWPM_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_HWPM_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_HWPM_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_MISC 28:28 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_MISC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_MISC_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_MODE_VPR_LOCK_MISC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_ADDR_LO 0x001FA804 /* RW-4R */ #define NV_PFB_PRI_MMU_VPR_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7D0 /* */ #define NV_PFB_PRI_MMU_VPR_ADDR_LO_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_ADDR_LO_VAL_INIT 0x0fffffff /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_ADDR_LO_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_VPR_ADDR_HI 0x001FA808 /* RW-4R */ #define NV_PFB_PRI_MMU_VPR_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7D0 /* */ #define NV_PFB_PRI_MMU_VPR_ADDR_HI_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_ADDR_HI_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_VPR_CYA_UNTRUSTED 0x00000000 /* */ #define NV_PFB_PRI_MMU_VPR_CYA_GRAPHICS 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CYA_VPR_AWARE 0x00000001 /* */ #define NV_PFB_PRI_MMU_VPR_CYA_QUARANTINE 0x00000002 /* */ #define NV_PFB_PRI_MMU_VPR_CYA_TRUSTED 0x00000003 /* */ #define NV_PFB_PRI_MMU_VPR_CYA_LO 0x001FA80C /* RW-4R */ #define NV_PFB_PRI_MMU_VPR_CYA_LO__PRIV_LEVEL_MASK 0x001FA7D0 /* */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_IN_USE_FUSE 3:3 /* R-XVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_IN_USE_FUSE_DISABLED 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_IN_USE_FUSE_ENABLED 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_IN_USE_FUSE_INIT 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_IN_USE 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_IN_USE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_IN_USE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_IN_USE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_DEFAULT 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_DEFAULT_USE_CYA 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_DEFAULT_DEAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_DEFAULT_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CPU 7:6 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CPU_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CPU_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_HOST 9:8 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_HOST_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_HOST_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PERF 11:10 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PERF_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PERF_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PMU 13:12 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PMU_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PMU_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE2 15:14 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE2_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE2_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SEC 17:16 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SEC_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SEC_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_FE 19:18 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_FE_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_FE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PD 21:20 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PD_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PD_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SCC 23:22 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SCC_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SCC_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SKED 25:24 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SKED_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_SKED_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_L1 27:26 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_L1_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_L1_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_TEX 29:28 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_TEX_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_TEX_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PE 31:30 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PE_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_PE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI 0x001FA810 /* RW-4R */ #define NV_PFB_PRI_MMU_VPR_CYA_HI__PRIV_LEVEL_MASK 0x001FA7D0 /* */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_AUTO_FETCH_FUSE 3:3 /* R-XVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_AUTO_FETCH_FUSE_DISABLED 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_AUTO_FETCH_FUSE_ENABLED 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_AUTO_FETCH_FUSE_INIT 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_RASTER 5:4 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_RASTER_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_RASTER_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GCC 7:6 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GCC_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GCC_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GPCCS 9:8 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GPCCS_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GPCCS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP 11:10 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_READ 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_READ_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_WRITE 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_WRITE_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_PROP_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_DNISO 15:14 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_DNISO_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_DNISO_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC 17:16 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC0 17:16 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC0_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC0_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC2 17:16 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC2_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC2_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSENC 17:16 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSENC_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSENC_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVDEC 19:18 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVDEC_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVDEC_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSPDEC 19:18 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSPDEC_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSPDEC_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GSP 21:20 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GSP_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_GSP_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC1 23:22 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC1_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_NVENC1_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSVLD 23:22 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSVLD_DEFAULT 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_MSVLD_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_OFA 25:24 /* RWEVF */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_OFA_DEFAULT 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VPR_CYA_HI_TRUST_OFA_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE0 15:14 #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE0_DEFAULT 0x00000001 #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE0_INIT 0x00000000 #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE1 15:14 #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE1_DEFAULT 0x00000001 #define NV_PFB_PRI_MMU_VPR_CYA_LO_TRUST_CE1_INIT 0x00000000 #define NV_PFB_PRI_MMU_WPR_ALLOW_READ 0x001FA814 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR_OK 27:27 /* RWXVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_ALL 11:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_ALL_DEFAULT 0x000000ff /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR(i) (((i)-1)*4+7):(((i)-1)*4+4) /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR__SIZE_1 3 /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR_SECURE(i,j) (((i)-1)*4+(j)+4):(((i)-1)*4+(j)+4) /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR_SECURE__SIZE_1 3 /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR_SECURE__SIZE_2 4 /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_DEFAULT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE0 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE0_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE0_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE0_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE1 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE1_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE1_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE1_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE2 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE2_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE2_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE2_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE3 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE3_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE3_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR1_SECURE3_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2 11:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_DEFAULT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE0 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE0_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE0_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE0_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE1 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE1_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE1_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE1_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE2 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE2_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE2_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE2_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE3 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE3_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE3_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_WPR2_SECURE3_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH 31:28 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH_BIT(i) ((i)+28):((i)+28) /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH_BIT__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH0 28:28 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH0_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH0_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH0_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH1 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH1_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH1_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH1_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH2 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH2_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH2_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH2_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH3 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH3_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH3_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_READ_MIS_MATCH3_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE 0x001FA818 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR_ENABLE_FUSE 27:27 /* RWXVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_ALL 11:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_ALL_DEFAULT 0x000000cc /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR(i) (((i)-1)*4+7):(((i)-1)*4+4) /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR__SIZE_1 3 /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR_SECURE(i,j) (((i)-1)*4+(j)+4):(((i)-1)*4+(j)+4) /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR_SECURE__SIZE_1 3 /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR_SECURE__SIZE_2 4 /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_DEFAULT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE0 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE0_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE0_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE0_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE1 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE1_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE1_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE1_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE2 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE2_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE2_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE2_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE3 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE3_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE3_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR1_SECURE3_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2 11:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_DEFAULT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE0 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE0_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE0_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE0_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE1 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE1_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE1_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE1_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE2 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE2_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE2_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE2_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE3 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE3_DEFAULT 1 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE3_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_WPR2_SECURE3_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH 31:28 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH_BIT(i) ((i)+28):((i)+28) /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH_BIT__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH0 28:28 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH0_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH0_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH0_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH1 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH1_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH1_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH1_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH2 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH2_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH2_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH2_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH3 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH3_DEFAULT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH3_NO 0 /* RW--V */ #define NV_PFB_PRI_MMU_WPR_ALLOW_WRITE_MIS_MATCH3_YES 1 /* RW--V */ #define NV_PFB_PRI_MMU_WPR1_ADDR_LO 0x001FA81C /* RW-4R */ #define NV_PFB_PRI_MMU_WPR1_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR1_ADDR_LO_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_ADDR_LO_VAL_INIT 0x0fffffff /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_ADDR_LO_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_WPR1_ADDR_HI 0x001FA820 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR1_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR1_ADDR_HI_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_ADDR_HI_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_WPR2_ADDR_LO 0x001FA824 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR2_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR2_ADDR_LO_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_ADDR_LO_VAL_INIT 0x0fffffff /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_ADDR_LO_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI 0x001FA828 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_ADDR_HI_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A 0x001FA940 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NISO 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_ISO 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_ISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_DNISO 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_DNISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_DWBIF 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_DWBIF_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_GSP 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_GSP_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_MMU 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_MMU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVDEC 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVDEC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVENC 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVENC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVJPG 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_NVJPG_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_OFA 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_OFA_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_PMU 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_PMU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_SEC 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_SEC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_XV 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_XV_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_P2P 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_P2P_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_HOST_CPU 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_HOST_CPU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_FBFALCON 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_A_FBFALCON_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B 0x001FA944 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PERF 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PERF_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GPM 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GPM_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_CE 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_CE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_FE 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_FE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_FECS 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_FECS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GCC 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GCC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GPCCS 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_GPCCS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PD 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PD_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PE 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PROP 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_PROP_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_RAST 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_RAST_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_RASTERTWOD 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_RASTERTWOD_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_SCC 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_SCC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_SKED 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_SKED_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_TEX 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_TEX_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_TPCCS 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_TPCCS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_HOST 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_HOST_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_ESC 17:17 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_RD_B_ESC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A 0x001FA948 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NISO 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_ISO 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_ISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_DNISO 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_DNISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_DWBIF 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_DWBIF_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_GSP 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_GSP_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_MMU 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_MMU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVDEC 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVDEC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVENC 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVENC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVJPG 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_NVJPG_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_OFA 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_OFA_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_PMU 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_PMU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_SEC 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_SEC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_XV 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_XV_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_P2P 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_P2P_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_HOST_CPU 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_HOST_CPU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_FBFALCON 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_A_FBFALCON_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B 0x001FA94C /* RW-4R */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PERF 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PERF_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GPM 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GPM_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_CE 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_CE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_FE 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_FE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_FECS 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_FECS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GCC 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GCC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GPCCS 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_GPCCS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PD 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PD_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PE 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PROP 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_PROP_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_RAST 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_RAST_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_RASTERTWOD 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_RASTERTWOD_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_SCC 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_SCC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_SKED 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_SKED_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_TEX 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_TEX_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_TPCCS 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_TPCCS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_HOST 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_HOST_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_ESC 17:17 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR1_NS_ALLOW_WR_B_ESC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A 0x001FA7B0 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NISO 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_ISO 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_ISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_DNISO 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_DNISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_DWBIF 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_DWBIF_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_GSP 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_GSP_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_MMU 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_MMU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVDEC 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVDEC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVENC 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVENC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVJPG 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_NVJPG_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_OFA 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_OFA_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_PMU 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_PMU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_SEC 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_SEC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_XV 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_XV_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_P2P 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_P2P_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_HOST_CPU 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_HOST_CPU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_FBFALCON 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_A_FBFALCON_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B 0x001FA7B4 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PERF 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PERF_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GPM 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GPM_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_CE 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_CE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_FE 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_FE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_FECS 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_FECS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GCC 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GCC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GPCCS 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_GPCCS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PD 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PD_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PE 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PROP 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_PROP_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_RAST 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_RAST_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_RASTERTWOD 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_RASTERTWOD_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_SCC 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_SCC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_SKED 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_SKED_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_TEX 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_TEX_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_TPCCS 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_TPCCS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_HOST 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_HOST_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_ESC 17:17 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_RD_B_ESC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A 0x001FA7B8 /* RW-4R */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NISO 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_ISO 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_ISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_DNISO 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_DNISO_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_DWBIF 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_DWBIF_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_GSP 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_GSP_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_MMU 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_MMU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVDEC 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVDEC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVENC 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVENC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVJPG 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_NVJPG_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_OFA 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_OFA_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_PMU 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_PMU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_SEC 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_SEC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_XV 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_XV_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_P2P 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_P2P_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_HOST_CPU 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_HOST_CPU_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_FBFALCON 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_A_FBFALCON_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B 0x001FA7BC /* RW-4R */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B__PRIV_LEVEL_MASK 0x001FA7CC /* */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PERF 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PERF_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GPM 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GPM_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_CE 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_CE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_FE 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_FE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_FECS 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_FECS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GCC 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GCC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GPCCS 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_GPCCS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PD 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PD_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PE 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PROP 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_PROP_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_RAST 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_RAST_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_RASTERTWOD 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_RASTERTWOD_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_SCC 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_SCC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_SKED 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_SKED_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_TEX 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_TEX_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_TPCCS 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_TPCCS_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_HOST 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_HOST_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_ESC 17:17 /* RWEVF */ #define NV_PFB_PRI_MMU_WPR2_NS_ALLOW_WR_B_ESC_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_ADDR_LO 0x001FA82C /* RW-4R */ #define NV_PFB_PRI_MMU_LOCK_ADDR_LO__PRIV_LEVEL_MASK 0x001FA7C8 /* */ #define NV_PFB_PRI_MMU_LOCK_ADDR_LO_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCK_ADDR_LO_VAL_INIT 0x0fffffff /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_ADDR_LO_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_LOCK_ADDR_HI 0x001FA830 /* RW-4R */ #define NV_PFB_PRI_MMU_LOCK_ADDR_HI__PRIV_LEVEL_MASK 0x001FA7C8 /* */ #define NV_PFB_PRI_MMU_LOCK_ADDR_HI_VAL 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCK_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCK_ADDR_HI_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_VPR_WPR_VAL 31:4 /* */ #define NV_PFB_PRI_MMU_WPR_ADDR_LO(i) (((i)-1)*(0x001FA824-0x001FA81C)+0x001FA81C) /* */ #define NV_PFB_PRI_MMU_WPR_ADDR_LO__SIZE_1 3 /* */ #define NV_PFB_PRI_MMU_WPR_ADDR_HI(i) (((i)-1)*(0x001FA828-0x001FA820)+0x001FA820) /* */ #define NV_PFB_PRI_MMU_WPR_ADDR_HI__SIZE_1 3 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE 0x00100CE0 /* RW-4R */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE__PRIV_LEVEL_MASK 0x001FA7C4 /* */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_SCALE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_SCALE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_MAG 9:4 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_LOWER_MAG_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_MIDDLE_SCALE 13:10 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_MIDDLE_SCALE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_MIDDLE_MAG 19:14 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_MIDDLE_MAG_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_UPPER_SCALE 23:20 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_UPPER_SCALE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_UPPER_MAG 29:24 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_UPPER_MAG_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_ECC_MODE 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_ECC_MODE_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE_ECC_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK 0x00100EFC /* RW-4R */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_PHYS_SECURE 0x00100CE4 /* RW-4R */ #define NV_PFB_PRI_MMU_PHYS_SECURE__PRIV_LEVEL_MASK 0x00100EFC /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_FECS 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_FECS_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PMU 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PMU_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_SEC 11:8 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_SEC_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_DFALCON 15:12 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_DFALCON_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_GSP 15:12 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_GSP_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_AFALCON 19:16 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_AFALCON_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_NVDEC 23:20 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_NVDEC_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_NVENC 27:24 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_NVENC_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_MSPPP 31:28 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_MSPPP_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_FBFALCON 31:28 /* RWEVF */ #define NV_PFB_PRI_MMU_PHYS_SECURE_FBFALCON_INIT 0x0000000F /* RWE-V */ #define NV_PFB_PRI_MMU_PHYS_SECURE_FECS_SECURE(i) ((i)+0):((i)+0) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_FECS_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PMU_SECURE(i) ((i)+4):((i)+4) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_PMU_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_SEC_SECURE(i) ((i)+8):((i)+8) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_SEC_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_DFALCON_SECURE(i) ((i)+12):((i)+12) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_DFALCON_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_GSP_SECURE(i) ((i)+12):((i)+12) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_GSP_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_AFALCON_SECURE(i) ((i)+16):((i)+16) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_AFALCON_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_NVDEC_SECURE(i) ((i)+20):((i)+20) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_NVDEC_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_NVENC_SECURE(i) ((i)+24):((i)+24) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_NVENC_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_MSPPP_SECURE(i) ((i)+28):((i)+28) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_MSPPP_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_FBFALCON_SECURE(i) ((i)+28):((i)+28) /* */ #define NV_PFB_PRI_MMU_PHYS_SECURE_FBFALCON_SECURE__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL 0x00100E00 /* RW-4R */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_MASK 15:0 /* RWEVF */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_MASK_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_ADDR 31:16 /* RWEVF */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_LOCAL_TGT_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER(i) (0x00100E04+(i)*4) /* RW-4A */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER__SIZE_1 8 /* */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_MASK 15:0 /* RWEVF */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_MASK_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_ADDR 31:16 /* RWEVF */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_PEER_TGT_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_ATS_ADDR_RANGE_GRANULARITY 37 /* */ #define NV_PFB_PRI_MMU_NON_REPLAY_FAULT_BUFFER 0 #define NV_PFB_PRI_MMU_REPLAY_FAULT_BUFFER 1 #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO(i) (0x00100E24+(i)*20) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO__SIZE_1 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE 0:0 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE_VIRTUAL 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE_PHYSICAL 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE 2:1 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_LOCAL 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_COH 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_NCOH 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_VOL 3:3 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR 31:12 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_HI(i) (0x00100E28+(i)*20) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_HI__SIZE_1 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_ADDR 31:0 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET(i) (0x00100E2C+(i)*20) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET__SIZE_1 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_NO 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_YES 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_NO 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_YES 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT(i) (0x00100E30+(i)*20) /* R--4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT__SIZE_1 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR 19:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED 30:30 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_NO 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_YES 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW 31:31 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE(i) (0x00100E34+(i)*20) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE__SIZE_1 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO 0x00100E4C /* R--4R */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE 1:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_LOCAL 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_PEER 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_COH 0x00000002 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_NCOH 0x00000003 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR 31:12 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_ADDR_HI 0x00100E50 /* R--4R */ #define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR 31:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INST_LO 0x00100E54 /* R--4R */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID 8:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE 11:10 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_VID_MEM 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_COHERENT 0x00000002 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR 31:12 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INST_HI 0x00100E58 /* R--4R */ #define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR 31:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO 0x00100E5C /* R--4R */ #define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE 4:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_FAULT_TYPE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT 7:7 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT 14:8 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE 19:16 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_READ 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_WRITE 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_ATOMIC 0x00000002 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PREFETCH 0x00000003 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_READ 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_READ 0x00000008 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* R---V */ #define NV_PFB_PRI_MMU_FAULT_INFO_ACCESS_TYPE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE 20:20 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_CLIENT_TYPE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID 28:24 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_GPC_ID_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE 29:29 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_PROTECTED_MODE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN 30:30 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VALID 31:31 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VALID_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS 0x00100E60 /* RW-4R */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE 8:8 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_SET 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE 9:9 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_SET 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR 10:10 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_ERROR_SET 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR 11:11 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_SET 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW 12:12 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_SET 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW 13:13 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_SET 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED 14:14 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_SET 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED 15:15 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_SET 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VAB_ERROR 16:16 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VAB_ERROR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VAB_ERROR_SET 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TYPE 29:28 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TYPE_REPLAYABLE 1 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TYPE_NON_REPLAYABLE 0 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TYPE_INIT 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY 30:30 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_FALSE 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_BUSY_TRUE 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VALID 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_CLEAR 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VALID_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK 0x00100EAC /* RW-4R */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 12 /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL 0x00100E6C /* RW-4R */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x00100EAC /* */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS 0x00100E70 /* RW-4R */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB0_SA_DATA 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB0_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB0_SA_DATA 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB0_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB0_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB1_SA_DATA 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_L2TLB1_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB1_SA_DATA 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB1_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_L2TLB1_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT 0x00100E74 /* R--4R */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* R-E-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* R-E-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E78 /* RW-4R */ #define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS 0x00100E7C /* R--4R */ #define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_RAM_ID_L2TLB0_SA_DATA 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_L2TLB_ECC_ADDRESS_RAM_ID_L2TLB1_SA_DATA 0x2 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL 0x00100E80 /* RW-4R */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x00100EAC /* */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS 0x00100E84 /* RW-4R */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_HUBTLB_SA_DATA 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_HUBTLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_HUBTLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_HUBTLB_SA_DATA 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_HUBTLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_HUBTLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT 0x00100E88 /* R--4R */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* R-E-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* R-E-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT 0x00100E8C /* RW-4R */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS 0x00100E90 /* R--4R */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PFB_PRI_MMU_HUBTLB_ECC_ADDRESS_RAM_ID_HUBTLB_SA_DATA 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL 0x00100E94 /* RW-4R */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL__PRIV_LEVEL_MASK 0x00100EAC /* */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS 0x00100E98 /* RW-4R */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PTE_DATA 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PTE_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PTE_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PTE_DATA 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PTE_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PTE_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PDE0_DATA 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PDE0_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_FILLUNIT_PDE0_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PDE0_DATA 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PDE0_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_FILLUNIT_PDE0_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT 0x00100E9C /* R--4R */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* R-E-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* R-E-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT 0x00100EA0 /* RW-4R */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS 0x00100EA4 /* R--4R */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_RAM_ID_FILLUNIT_PTE_DATA 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_FILLUNIT_ECC_ADDRESS_RAM_ID_FILLUNIT_PDE0_DATA 0x2 /* RW--V */ #define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR 0x00100EA8 /* R-E4R */ #define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR 0:0 /* R-EVF */ #define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR 1:1 /* R-EVF */ #define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PFB_PRI_MMU_HUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK 0x00100EB8 /* RW-4R */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 8 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ 0x00100EB4 /* RW-4R */ #define NV_PFB_PRI_MMU_CBC_ADJ__PRIV_LEVEL_MASK 0x00100EB8 /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_START_P2 1:0 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_START_P2_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_START_NP2 3:2 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_START_NP2_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_END_P2 5:4 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_END_P2_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_END_NP2 7:6 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_END_NP2_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_SIZE_P2 9:8 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_SIZE_P2_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_SIZE_NP2 11:10 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_SIZE_NP2_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_COMPTAGLINE 23:12 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_COMPTAGLINE_INIT 0x00000fff /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_COMPTAGLINE_ALIGNMENT 0x0000000c /* */ #define NV_PFB_PRI_MMU_CBC_ADJ_BEG_MEM_CHK 28:28 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_BEG_MEM_CHK_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_BEG_MEM_CHK_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_BEG_MEM_CHK_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_END_MEM_CHK 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_END_MEM_CHK_INIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_END_MEM_CHK_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_END_MEM_CHK_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_ALWAYS_SAFE 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_ALWAYS_SAFE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_ADJ_ALWAYS_SAFE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_ALWAYS_SAFE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_ADJ_SAFE 31:31 /* R-XVF */ #define NV_PFB_PRI_MMU_CBC_ADJ_SAFE_FALSE 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_CBC_ADJ_SAFE_TRUE 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK 0x00100EBC /* RW-4R */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS 0x00100EC0 /* R--4R */ #define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_V 4:0 /* R--VF */ #define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_COUNT 4:0 /* R--VF */ #define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_HALF_LTC 7:7 /* R--VF */ #define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_HALF_LTC_DISABLED 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_HALF_LTC_ENABLED 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_COMPTAGLINE_BITS 13:8 /* R--VF */ #define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_BYTES_PER_COMPTAGLINE 27:16 /* R--VF */ #define NV_PFB_PRI_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC 30:28 /* R--VF */ #define NV_PFB_PRI_MMU_CBC_BASE 0x00100EC4 /* RW-4R */ #define NV_PFB_PRI_MMU_CBC_BASE__PRIV_LEVEL_MASK 0x00100EBC /* */ #define NV_PFB_PRI_MMU_CBC_BASE_ADDRESS 25:0 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_BASE_ADDRESS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_BASE_ALIGNMENT_SHIFT 11 /* */ #define NV_PFB_PRI_MMU_CBC_TOP 0x00100EC8 /* RW-4R */ #define NV_PFB_PRI_MMU_CBC_TOP__PRIV_LEVEL_MASK 0x00100EBC /* */ #define NV_PFB_PRI_MMU_CBC_TOP_SIZE 14:0 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_TOP_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_TOP_ALIGNMENT_SHIFT 11 /* */ #define NV_PFB_PRI_MMU_CBC_MAX 0x00100ECC /* RW-4R */ #define NV_PFB_PRI_MMU_CBC_MAX__PRIV_LEVEL_MASK 0x00100EBC /* */ #define NV_PFB_PRI_MMU_CBC_MAX_COMPTAGLINE 23:0 /* RWEVF */ #define NV_PFB_PRI_MMU_CBC_MAX_COMPTAGLINE_INIT 0x00ffffff /* RWE-V */ #define NV_PFB_PRI_MMU_CBC_MAX_SAFE 31:31 /* R-XVF */ #define NV_PFB_PRI_MMU_CBC_MAX_SAFE_FALSE 0x00000000 /* R---V */ #define NV_PFB_PRI_MMU_CBC_MAX_SAFE_TRUE 0x00000001 /* R---V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL 0x00100ED0 /* RW-4R */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_SRIOV 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_SRIOV_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_SRIOV_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_ATS 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_ATS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_ATS_ENABLED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FAULT_SYS_BAR_PT_ON_NB_CPU_ACCESS 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FAULT_SYS_BAR_PT_ON_NB_CPU_ACCESS_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FAULT_SYS_BAR_PT_ON_NB_CPU_ACCESS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_USE_SMC_VEID_TABLES 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_USE_SMC_VEID_TABLES_DISABLE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_USE_SMC_VEID_TABLES_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FORCE_SWIZID_0_VOL 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FORCE_SWIZID_0_VOL_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FORCE_SWIZID_0_VOL_ENABLE 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FORCE_CBC_RAW_MODE 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FORCE_CBC_RAW_MODE_DISABLE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_FORCE_CBC_RAW_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PAGE_TABLE_V3 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PAGE_TABLE_V3_DISABLE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_HYPERVISOR_CTL_PAGE_TABLE_V3_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INT_VECTOR_ECC_ERROR 0x00100EDC /* R--4R */ #define NV_PFB_PRI_MMU_INT_VECTOR_ECC_ERROR__PRIV_LEVEL_MASK 0x00100EAC /* */ #define NV_PFB_PRI_MMU_INT_VECTOR_ECC_ERROR_VECTOR 15:0 /* R-EVF */ #define NV_PFB_PRI_MMU_INT_VECTOR_ECC_ERROR_VECTOR_INIT 128 /* R-E-V */ #define NV_PFB_PRI_MMU_INT_VECTOR_INFO_FAULT 0x00100EE0 /* R--4R */ #define NV_PFB_PRI_MMU_INT_VECTOR_INFO_FAULT_VECTOR 15:0 /* R-EVF */ #define NV_PFB_PRI_MMU_INT_VECTOR_INFO_FAULT_VECTOR_INIT 134 /* R-E-V */ #define NV_PFB_PRI_MMU_INT_VECTOR_FAULT(i) (0x00100EE4+(i)*4) /* R--4A */ #define NV_PFB_PRI_MMU_INT_VECTOR_FAULT__SIZE_1 2 /* */ #define NV_PFB_PRI_MMU_INT_VECTOR_FAULT_ERROR 15:0 /* R--VF */ #define NV_PFB_PRI_MMU_INT_VECTOR_FAULT_ERROR_REPLAYABLE 131 /* R---V */ #define NV_PFB_PRI_MMU_INT_VECTOR_FAULT_ERROR_NON_REPLAYABLE 133 /* R---V */ #define NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY 31:16 /* R--VF */ #define NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_REPLAYABLE 64 /* R---V */ #define NV_PFB_PRI_MMU_INT_VECTOR_FAULT_NOTIFY_NON_REPLAYABLE 132 /* R---V */ #define NV_PFB_PRI_MMU_VMMU_CFG0 0x00100EF8 /* RW-4R */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE 2:0 /* RWEVF */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_32MB 0x0 /* RW--V */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_64MB 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_128MB 0x2 /* RW--V */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_256MB 0x3 /* RW--V */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_512MB 0x4 /* RW--V */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_INIT 3 /* RWE-V */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_ALIGN 25 /* */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID 31:22 /* R-EVF */ #define NV_PFB_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID_INIT 384 /* R-E-V */ #define NV_PFB_PRI_MMU_SRIOV_VMMU_TABLE(i) (0x001F0000+(i)*4) /* RW-4A */ #define NV_PFB_PRI_MMU_SRIOV_VMMU_TABLE__SIZE_1 768 /* */ #define NV_PFB_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP 31:0 /* RWEVF */ #define NV_PFB_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT(i,j) (0x1F2000+((i)*128)+((j)*20)) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT__SIZE_2 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT_ADDR_MODE 0:0 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT_PHYS_APERTURE 2:1 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT_PHYS_VOL 3:3 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT_ADDR 31:12 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT(i,j) (0x1F2004+((i)*128)+((j)*20)) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT__SIZE_2 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT_ADDR 31:0 /* RW-VF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT(i,j) (0x1F2008+((i)*128)+((j)*20)) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT__SIZE_2 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_PTR 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_PTR_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_GETPTR_CORRUPTED 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_GETPTR_CORRUPTED_NO 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_OVERFLOW 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT_OVERFLOW_NO 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT(i,j) (0x1F200C+((i)*128)+((j)*20)) /* R--4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT__SIZE_2 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_PTR 19:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_PTR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_GETPTR_CORRUPTED 30:30 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_GETPTR_CORRUPTED_NO 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_OVERFLOW 31:31 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT_OVERFLOW_NO 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT(i,j) (0x1F2010+((i)*128)+((j)*20)) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT__SIZE_2 2 /* */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_VAL 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_VAL_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_OVERFLOW_INTR 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_SET_DEFAULT 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_SET_DEFAULT_NO 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_ENABLE 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT(i) (0x1F203C+((i)*128)) /* R--4A */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT_PHYS_APERTURE 1:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT_PHYS_APERTURE_LOCAL 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT_ADDR 31:12 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT_ADDR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT(i) (0x1F2040+((i)*128)) /* R--4A */ #define NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT_ADDR 31:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT_ADDR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT(i) (0x1F2044+((i)*128)) /* R--4A */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_ENGINE_ID 8:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_ENGINE_ID_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_APERTURE 11:10 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_APERTURE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_ADDR 31:12 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT_ADDR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT(i) (0x1F2048+((i)*128)) /* R--4A */ #define NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT_ADDR 31:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT_ADDR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT(i) (0x1F204C+((i)*128)) /* R--4A */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_FAULT_TYPE 4:0 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_FAULT_TYPE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_REPLAYABLE_FAULT 7:7 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_REPLAYABLE_FAULT_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_CLIENT 14:8 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_CLIENT_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_ACCESS_TYPE 19:16 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_ACCESS_TYPE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_CLIENT_TYPE 20:20 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_CLIENT_TYPE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_GPC_ID 28:24 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_GPC_ID_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_PROTECTED_MODE 29:29 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_PROTECTED_MODE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_REPLAYABLE_FAULT_EN 30:30 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_REPLAYABLE_FAULT_EN_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_VALID 31:31 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_INFO_VIRT_VALID_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT(i) (0x1F2050+((i)*128)) /* RW-4A */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR1_PHYS 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR1_PHYS_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR1_VIRT 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR1_VIRT_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR2_PHYS 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR2_PHYS_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR2_VIRT 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_BAR2_VIRT_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_IFB_PHYS 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_IFB_PHYS_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_IFB_VIRT 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_IFB_VIRT_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_OTHER_PHYS 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_OTHER_PHYS_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_OTHER_VIRT 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_DROPPED_OTHER_VIRT_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE 8:8 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE 9:9 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_ERROR 10:10 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_ERROR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_ERROR 11:11 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_ERROR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_OVERFLOW 12:12 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_OVERFLOW_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_OVERFLOW 13:13 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_OVERFLOW_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_GETPTR_CORRUPTED 14:14 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_REPLAYABLE_GETPTR_CORRUPTED_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_GETPTR_CORRUPTED 15:15 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_NON_REPLAYABLE_GETPTR_CORRUPTED_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_VAB_ERROR 16:16 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_VAB_ERROR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_BUSY_TYPE 29:28 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_BUSY_TYPE_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_BUSY 30:30 /* R-EVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_BUSY_FALSE 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_VALID 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_FAULT_STATUS_VIRT_VALID_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VADDR_VIRT(i) (0x1F2054+((i)*128)) /* RW-4A */ #define NV_PFB_PRI_MMU_INVALIDATE_VADDR_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_INVALIDATE_VADDR_VIRT_BITS 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VADDR_VIRT_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_VIRT(i) (0x1F2058+((i)*128)) /* RW-4A */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_VIRT_BITS 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_VADDR_VIRT_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT(i) (0x1F205C+((i)*128)) /* RW-4A */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT_APERTURE 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT_APERTURE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT_ADDR 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT(i) (0x1F2060+((i)*128)) /* RW-4A */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT_ADDR 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_PASID_VIRT(i) (0x1F2064+((i)*128)) /* RW-4A */ #define NV_PFB_PRI_MMU_INVALIDATE_PASID_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_INVALIDATE_PASID_VIRT_VAL 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_PASID_VIRT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT(i) (0x1F2068+((i)*128)) /* RW-4A */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT_VAL 5:0 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT_GFID 31:26 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_SIZE_VIRT_GFID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT(i) (0x1F206C+((i)*128)) /* RW-4A */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ALL_VA 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ALL_VA_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ALL_PDB 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ALL_PDB_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_HUBTLB_ONLY 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_HUBTLB_ONLY_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_REPLAY 5:3 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_REPLAY_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_SYS_MEMBAR 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_SYS_MEMBAR_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ACK 8:7 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_ACK_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_CLIENT_ID 14:9 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_CLIENT_ID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_GPC_ID 19:15 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_GPC_ID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_INVAL_SCOPE 16:15 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_INVAL_SCOPE_ALL_TLBS 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_INVAL_SCOPE_LINK_TLBS 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_INVAL_SCOPE_NON_LINK_TLBS 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_CLIENT_TYPE 20:20 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CANCEL_CLIENT_TYPE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_USE_PASID 21:21 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_USE_PASID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_USE_SIZE 22:22 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_USE_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_PROP_FLUSH 23:23 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_PROP_FLUSH_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CACHE_LEVEL 26:24 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_CACHE_LEVEL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_TRIGGER 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_TRIGGER_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_INVALIDATE_VIRT_TRIGGER_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT(i) (0x1F207C+((i)*128)) /* RW-4A */ #define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT_PRF_FILTER 1:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT_PRF_FILTER_SEND_ALL 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT_PRF_FILTER_SEND_NONE 0x00000003 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_SUPPORT 0x00100ED4 /* RW-4R */ #define NV_PFB_PRI_MMU_PEER_SUPPORT_GFID 7:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PEER_SUPPORT_GFID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_SUPPORT_MAX_PEER_ID 10:8 /* RWEVF */ #define NV_PFB_PRI_MMU_PEER_SUPPORT_MAX_PEER_ID_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_SUPPORT_FLA 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_PEER_SUPPORT_FLA_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PEER_SUPPORT_FLA_ENABLED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA(i) (0x001F8F00+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA__PRIV_LEVEL_MASK 0x001FA7D4 /* */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB(i) (0x001F8F04+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB__PRIV_LEVEL_MASK 0x001FA7D4 /* */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_OFA0_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGA(i) (0x001F9000+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGA__SIZE_1 8 /* */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGA__PRIV_LEVEL_MASK 0x001FA7D8 /* */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGB(i) (0x001F9004+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGB__SIZE_1 8 /* */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGB__PRIV_LEVEL_MASK 0x001FA7D8 /* */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_PMU_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGA(i) (0x001F9040+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGA__SIZE_1 8 /* */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGA__PRIV_LEVEL_MASK 0x001FA7DC /* */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGB(i) (0x001F9044+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGB__SIZE_1 8 /* */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGB__PRIV_LEVEL_MASK 0x001FA7DC /* */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_SEC_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGA(i) (0x001F9080+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGA__SIZE_1 8 /* */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGA__PRIV_LEVEL_MASK 0x001FA7EC /* */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGB(i) (0x001F9084+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGB__SIZE_1 8 /* */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGB__PRIV_LEVEL_MASK 0x001FA7EC /* */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_GSP_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGA(i) (0x001F90C0+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGA__PRIV_LEVEL_MASK 0x001FA7F0 /* */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGB(i) (0x001F90C4+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGB__PRIV_LEVEL_MASK 0x001FA7F0 /* */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_FECS_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA(i) (0x001F9100+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA__PRIV_LEVEL_MASK 0x001FA7F4 /* */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB(i) (0x001F9104+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB__PRIV_LEVEL_MASK 0x001FA7F4 /* */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_GPCCS_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA(i) (0x001F9140+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA__PRIV_LEVEL_MASK 0x001FA7F8 /* */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB(i) (0x001F9144+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB__PRIV_LEVEL_MASK 0x001FA7F8 /* */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_FBFALCON_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA(i) (0x001F91C0+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB(i) (0x001F91C4+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC0_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA(i) (0x001F9200+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB(i) (0x001F9204+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC1_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA(i) (0x001F9240+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB(i) (0x001F9244+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC2_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA(i) (0x001F9280+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB(i) (0x001F9284+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC3_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA(i) (0x001F92A0+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB(i) (0x001F92A4+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB__PRIV_LEVEL_MASK 0x001FA7E0 /* */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVDEC4_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA(i) (0x001F92C0+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA__PRIV_LEVEL_MASK 0x001FA7E4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB(i) (0x001F92C4+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB__PRIV_LEVEL_MASK 0x001FA7E4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC0_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA(i) (0x001F9300+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA__PRIV_LEVEL_MASK 0x001FA7E4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB(i) (0x001F9304+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB__PRIV_LEVEL_MASK 0x001FA7E4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC1_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA(i) (0x001F9340+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA__PRIV_LEVEL_MASK 0x001FA7E4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB(i) (0x001F9344+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB__PRIV_LEVEL_MASK 0x001FA7E4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC2_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA(i) (0x001F9380+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA__PRIV_LEVEL_MASK 0x001FA7E4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB(i) (0x001F9384+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB__PRIV_LEVEL_MASK 0x001FA7E4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVENC3_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA(i) (0x001F93C0+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA__PRIV_LEVEL_MASK 0x001FA7E8 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB(i) (0x001F93C4+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB__PRIV_LEVEL_MASK 0x001FA7E8 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG0_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA(i) (0x001F9400+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA__PRIV_LEVEL_MASK 0x001FA7E8 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB(i) (0x001F9404+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB__PRIV_LEVEL_MASK 0x001FA7E8 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG1_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA(i) (0x001F9440+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA__PRIV_LEVEL_MASK 0x001FA7E8 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB(i) (0x001F9444+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB__PRIV_LEVEL_MASK 0x001FA7E8 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG2_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA(i) (0x001F9480+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA__PRIV_LEVEL_MASK 0x001FA7E8 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA_ALLOW_READ 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA_ALLOW_READ_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA_ADDR_LO 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGA_ADDR_LO_INIT 0x0FFFFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB(i) (0x001F9484+(i)*8) /* RW-4A */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB__SIZE_1 4 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB__PRIV_LEVEL_MASK 0x001FA7E8 /* */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB_ALLOW_WRITE 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB_ALLOW_WRITE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB_ADDR_HI 31:4 /* RWEVF */ #define NV_PFB_PRI_MMU_FALCON_NVJPG3_CFGB_ADDR_HI_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_0(i) (0x001F94C0+(i)*4) /* RW-4A */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_0__SIZE_1 1 /* */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_REMOTE_SWIZID 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_REMOTE_SWIZID_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_ENG_VEID_OFFSET 21:16 /* RWEVF */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_MMU_ENG_VEID_OFFSET_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_VEID_MAX 29:24 /* RWEVF */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_0_VEID_MAX_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_1(i) (0x001F94E0+(i)*4) /* RW-4A */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_1__SIZE_1 1 /* */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_GPC_MASK 15:0 /* RWEVF */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_GPC_MASK_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_GPC_MASK_HW 7:0 /* RWEVF */ #define NV_PFB_PRI_MMU_SMC_ENG_CFG_1_GPC_MASK_HW_INIT 0 /* RWE-V */ #define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG(i) (0x001F9500+(i)*4) /* RW-4A */ #define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_GUEST_VEID_OFFSET 5:0 /* RWEVF */ #define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_GUEST_VEID_OFFSET_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_BAR_REMOTE_SWIZID 11:8 /* RWEVF */ #define NV_PFB_PRI_MMU_GFID_GR_FAULT_ID_CFG_BAR_REMOTE_SWIZID_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG(i) (0x001F9600+(i)*4) /* RW-4A */ #define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG__SIZE_1 64 /* */ #define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_REMOTE_SWIZID 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_REMOTE_SWIZID_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_MMU_ENG_ID_CFG_FAULT_ID 21:16 /* RWXUF */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOTTOM 0x001F9800 /* RW-4R */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE 0x001F9804 /* RW-4R */ #define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE 4096 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2 0xC /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_ATOM_SIZE 4096 #define NV_PFB_PRI_MMU_MEM_PARTITION_ATOM_SIZE_LG2 0xC #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK 0x001F9814 /* RW-4R */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_SECURE_TOP_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP 0x001F9808 /* RW-4R */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP__PRIV_LEVEL_MASK 0x001F9814 /* */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_ADDR 20:0 /* RWEVF */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_ADDR_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_MODE 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_MODE_INIT 0x0 /* RWE-V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_MODE_RELATIVE 0x0 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_MODE_ABSOLUTE 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SECURE_TOP_ADDR_ALIGNMENT 0x10 #define NV_PFB_PRI_MMU_MEM_PARTITION_ACTUAL_TOP 0x001F9818 /* R--4R */ #define NV_PFB_PRI_MMU_MEM_PARTITION_ACTUAL_TOP_ADDR 20:0 /* R--VF */ #define NV_PFB_PRI_MMU_MEM_PARTITION_ACTUAL_TOP_ACTIVE 31:31 /* R--VF */ #define NV_PFB_PRI_MMU_MEM_PARTITION_ACTUAL_TOP_ADDR_ALIGNMENT 0x10 #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0 0x001F980C /* RW-4R */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL 10:0 /* RWEVF */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT 0x00000603 /* RWE-V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_0 0x603 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_1 0x423 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_2 0x621 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_3 0x40B /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_4 0x429 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_5 0x4A1 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_6 0x681 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_7 0x407 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_8 0x40D /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_9 0x419 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_10 0x431 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_11 0x461 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_12 0x4C1 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_13 0x581 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_MASK_14 0x701 /* RW--V */ #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_0 0x603 #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_1 0x623 #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_2 0x623 #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_3 0x62B #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_4 0x62B #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_5 0x6A3 #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_6 0x6A3 #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_7 0x62F #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_8 0x62F #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_9 0x63B #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_10 0x63B #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_11 0x6E3 #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_12 0x6E3 #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_13 0x7A3 #define NV_PFB_PRI_MMU_MEM_PARTITION_SWIZID_MASK_14 0x7A3 #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG 0x001F9810 /* RWE4R */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i) (((i)*4)+1):((i)*4) /* */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x00000000 /* */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x00000000 /* */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x00000001 /* */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x00000002 /* */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x00000003 /* */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 1 /* */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWEUF */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWEUF */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWEUF */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWEUF */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWEUF */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWEUF */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWEUF */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWEUF */ #define NV_PFB_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT 0x001FA840 /* RW-4R */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE 3:0 /* R-EVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT 1 /* R-E-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_GRANULARITY 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_GRANULARITY_INIT 0x00000005 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_MODE 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO 0x001FA85C /* RW-4R */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL 31:27 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI 0x001FA860 /* RW-4R */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL 31:0 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP 0x001FA844 /* RW-4R */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP_TRIGGER 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP_TRIGGER_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_DUMP_TRIGGER_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_LO 0x001FA848 /* RW-4R */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_LO_ADDR 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_LO_ADDR_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_HI 0x001FA84C /* RW-4R */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_HI_ADDR 31:0 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_HI_ADDR_RESET 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE 0x001FA850 /* RW-4R */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_VAL 19:0 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_VAL_RESET 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_PUT 0x001FA854 /* R--4R */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_PUT_PTR 19:0 /* R-EVF */ #define NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_PUT_PTR_RESET 0x00000000 /* R-E-V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR 0x001FA858 /* RW-4R */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR__PRIV_LEVEL_MASK 0x001FA7D0 /* */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM 1:0 /* RWEVF */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM_IN_USE_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM_PROTECTED_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM_ENABLED 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_VIDMEM_DISABLED 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER 5:4 /* RWEVF */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER_IN_USE_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER_PROTECTED_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER_ENABLED 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_ACCESS_COUNTER_DISABLED 0x00000003 /* RW--V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_SECURE_REQUEST 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_SECURE_REQUEST_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_SECURE_REQUEST_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_ACCESS_LOGGING_VPR_SECURE_REQUEST_INIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK 0x001F981C /* RW-4R */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 12 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_PMU_ENABLED_FUSE1 0x0000004E /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG 0x001F9820 /* RW-4R */ #define NV_PFB_PRI_MMU_POWERGATE_CFG__PRIV_LEVEL_MASK 0x001F981C /* */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_DISABLED 0x0 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_ENABLED 0x1 /* RW--V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_INIT 0x1 /* RWE-V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_STATUS 1:1 /* R-EVF */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_STATUS_DISABLED 0x0 /* R---V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_STATUS_ENABLED 0x1 /* R---V */ #define NV_PFB_PRI_MMU_POWERGATE_CFG_GPCMMU_STATUS_INIT 0x0 /* R-E-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK 0x00100C90 /* RWE4R */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_DNISO 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_DNISO_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_DNISO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_FE 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_FE_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_FE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_FECS 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_FECS_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_FECS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_CPU 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_CPU_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_HOST_CPU_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_MMU 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_MMU_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_MMU_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVDEC 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVDEC_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVDEC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_UNUSED 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_UNUSED_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_UNUSED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NISO 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NISO_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NISO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_P2P 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_P2P_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_P2P_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_PD 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_PD_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_PD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_PERF 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_PERF_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_PERF_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_PMU 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_PMU_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_PMU_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_RASTERTWOD 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_RASTERTWOD_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_RASTERTWOD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SCC 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SCC_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SCC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SEC 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SEC_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SEC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SSYNC 17:17 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SSYNC_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SSYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_XV 18:18 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_XV_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_XV_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVENC 19:19 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVENC_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVENC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SKED 21:21 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SKED_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_SKED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_HSHUB 23:23 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_HSHUB_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_HSHUB_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_DWBIF 24:24 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_DWBIF_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_DWBIF_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_FBFALCON 25:25 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_FBFALCON_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_FBFALCON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_SHIM 26:26 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_SHIM_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_CE_SHIM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_GSP 27:27 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_GSP_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_GSP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVJPG 28:28 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVJPG_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_NVJPG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_OFA 29:29 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_OFA_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_OFA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_ESC 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_ESC_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_UNIT_MASK_ESC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK 0x00100C94 /* RWE4R */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_RD 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_RD_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_WR 1:1 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_WR_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_GATOM 2:2 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_GATOM_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_GATOM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_GRED 3:3 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_GRED_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_GRED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CACHE_MGMT 4:4 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PREFETCH 5:5 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PREFETCH_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PREFETCH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_MEMBAR 7:7 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_MEMBAR_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_MEMBAR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_RD 8:8 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_RD_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_WR 9:9 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_WR_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GRED 10:10 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GATOM 11:11 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PACK_RD 12:12 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PACK_RD_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PACK_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_WR 13:13 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GRED 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM 15:15 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS 22:22 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS 23:23 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_VIDMEM 24:24 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_VIDMEM_ENABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_VIDMEM_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PEER 25:25 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PEER_ENABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_PEER_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_C 26:26 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_NC 27:27 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_TYPE 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_TYPE_VIRTUAL 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_TYPE_PHYSICAL 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_EXCLUSIVE 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CG 0x00100C98 /* RWE4R */ #define NV_PFB_PRI_MMU_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_PRI_MMU_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PFB_PRI_MMU_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_PRI_MMU_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_PRI_MMU_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_MMU_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_PRI_MMU_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PFB_PRI_MMU_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_PRI_MMU_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_PRI_MMU_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_MMU_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_PRI_MMU_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_PRI_MMU_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_PRI_MMU_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_MMU_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_PRI_MMU_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_PRI_MMU_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_PRI_MMU_CG1 0x00100C9C /* RWE4R */ #define NV_PFB_PRI_MMU_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_PRI_MMU_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CG1_SLCG 8:1 /* RWEVF */ #define NV_PFB_PRI_MMU_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_CG1_SLCG_DISABLED 0x000000FF /* RWE-V */ #define NV_PFB_PRI_MMU_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PG 0x00100CA0 /* RWE4R */ #define NV_PFB_PRI_MMU_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0000000A /* RWE-V */ #define NV_PFB_PRI_MMU_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0000000A /* RWE-V */ #define NV_PFB_PRI_MMU_PG_IDLE_BLPG_EN 16:16 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_IDLE_BLPG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PG_IDLE_BLPG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PG_DIS_EARLY_WUP 17:17 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_DIS_EARLY_WUP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PG_DIS_EARLY_WUP_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PG_DEEP_ELPG_EN 18:18 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_DEEP_ELPG_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PG_DEEP_ELPG_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_PRI_MMU_PG_IDLE_ELPG_EN 19:19 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_IDLE_ELPG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PG_IDLE_ELPG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PG_DIDT_DELAY 23:20 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_DIDT_DELAY_HWINIT 0x0000000A /* RWE-V */ #define NV_PFB_PRI_MMU_PG_RESET_DURATION 26:24 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_RESET_DURATION_HWINIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PG_CLAMP_DELAY 29:27 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_CLAMP_DELAY_HWINIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PG_ZONE_OFF_MASK 30:30 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_ZONE_OFF_MASK_HWINIT 0x00000001 /* RWE-V */ #define NV_PFB_PRI_MMU_PG_SOFT_GATING_EN 31:31 /* RWEVF */ #define NV_PFB_PRI_MMU_PG_SOFT_GATING_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_PRI_MMU_PG_SOFT_GATING_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_PRI_MMU_PG1 0x00100CFC /* RWE4R */ #define NV_PFB_PRI_MMU_PG1_ZONE_SEQ 23:0 /* RWEVF */ #define NV_PFB_PRI_MMU_PG1_ZONE_SEQ_HWINIT 0x00053977 /* RWE-V */ #define NV_PFB_PRI_MMU_PG1_ZONE_MASK 31:24 /* RWEVF */ #define NV_PFB_PRI_MMU_PG1_ZONE_MASK_HWINIT 0x000000FF /* RWE-V */ #define NV_PFB_HSMMU0 0x0000a3ff:0x0000a000 /* RW--D */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL 0x0000a080 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_VM_PG_SIZE 0:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_VM_PG_SIZE_64KB 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_COMP_FAULT 2:2 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_COMP_FAULT_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_COMP_FAULT_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN 4:3 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN_FULL 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN_HALF 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN_QUARTER 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP 0x3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE 6:5 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_ON 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_CACHE_MODE_OFF 0x3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_L2_SEND_MODE 9:9 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE 25:24 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER 0x3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA 26:26 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL 0x0000a0a0 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_SIZE 1:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE 3:2 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE 5:4 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE 7:6 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_FA_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE 9:8 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG 11:10 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_BIG_PG_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG 13:12 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_L1TLB_SET_INDEX_SMALL_PG_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE 15:14 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_UTLB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SIZE 17:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE 19:18 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FA_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE 21:20 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG 23:22 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_BIG_PG_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG 25:24 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_SET_INDEX_SMALL_PG_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE 26:26 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_L1TLB_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE 27:27 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_UTLB_FAST_PATH_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE 29:28 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_NVL_UTLB_RB_SIZE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_SECURE_LOCK 30:30 /* R-XVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_SECURE_LOCK_FALSE 0x0 /* R---V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_SECURE_LOCK_INIT 0x0 /* R---V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_SECURE_LOCK_TRUE 0x1 /* R---V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE 31:31 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_TLB_CTRL_FAST_BIG_PG_FAULT_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH 0x0000a0a4 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_DISABLE 0:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_BIG_DISABLE 1:1 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_BIG_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_BIG_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_UNFILLED_DISABLE 2:2 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_UNFILLED_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_UNFILLED_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_ENABLE 3:3 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_ENABLE_TRUE 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH 12:12 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_DISABLE 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_REFETCH_ENABLE 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE 14:13 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_1 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_2 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_4 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_SMALL_PAGE_STEP_SIZE_8 0x3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE 16:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_BIG_DISABLE 17:17 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_BIG_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE 18:18 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_UNFILLED_DISABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_ENABLE 19:19 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_ENABLE_TRUE 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH 28:28 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_DISABLE 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_REFETCH_ENABLE 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE 30:29 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_1 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_2 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_4 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PREFETCH_NVL_SMALL_PAGE_STEP_SIZE_8 0x3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL 0x0000a0c4 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_WR_KIND 7:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT 0x00 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_RD_KIND 15:8 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT 0x00 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_DEBUG 16:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE 18:17 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_128KB 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_1MB 0x3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR 0x0000a0c8 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE 1:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_VOL 2:2 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_VOL_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_VOL_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_ADDR 31:4 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD 0x0000a0cc /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE 1:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE_PEER_MEM 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC 0x3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_VOL 2:2 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_VOL_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_VOL_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_ADDR 31:4 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_ADDR_INIT 0x0000000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT 0x000000c /* */ #define NV_PFB_HSMMU0_PRI_MMU_PM 0x0000a084 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT 7:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_00 0x00 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_01 0x01 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_02 0x02 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_03 0x03 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_04 0x04 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_05 0x05 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_06 0x06 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_07 0x07 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_08 0x08 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_09 0x09 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0A 0x0a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0B 0x0b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0C 0x0c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0D 0x0d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0E 0x0e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_0F 0x0f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_10 0x10 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_11 0x11 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_12 0x12 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_13 0x13 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_14 0x14 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_15 0x15 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_16 0x16 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_17 0x17 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_18 0x18 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_19 0x19 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1A 0x1a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1B 0x1b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1C 0x1c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1D 0x1d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1E 0x1e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_1F 0x1f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_20 0x20 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_21 0x21 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_22 0x22 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_23 0x23 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_24 0x24 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_25 0x25 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_26 0x26 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_27 0x27 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_28 0x28 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_29 0x29 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2A 0x2a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2B 0x2b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2C 0x2c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2D 0x2d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2E 0x2e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_2F 0x2f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_30 0x30 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_31 0x31 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_32 0x32 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_33 0x33 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_34 0x34 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_35 0x35 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_36 0x36 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_37 0x37 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_38 0x38 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_39 0x39 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3A 0x3a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3B 0x3b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3C 0x3c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3D 0x3d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3E 0x3e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_3F 0x3f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_40 0x40 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_41 0x41 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_42 0x42 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_43 0x43 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_44 0x44 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_45 0x45 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_46 0x46 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_47 0x47 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_48 0x48 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_49 0x49 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4A 0x4a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4B 0x4b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4C 0x4c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4D 0x4d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4E 0x4e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_4F 0x4f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_50 0x50 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_51 0x51 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_52 0x52 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_53 0x53 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_54 0x54 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_55 0x55 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_56 0x56 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_57 0x57 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_58 0x58 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_59 0x59 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5A 0x5a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5B 0x5b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5C 0x5c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5D 0x5d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5E 0x5e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_5F 0x5f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_60 0x60 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_61 0x61 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_62 0x62 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_63 0x63 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_64 0x64 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_65 0x65 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_66 0x66 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_67 0x67 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_68 0x68 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_69 0x69 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6A 0x6a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6B 0x6b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6C 0x6c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6D 0x6d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6E 0x6e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_6F 0x6f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_70 0x70 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_71 0x71 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_72 0x72 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_73 0x73 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_74 0x74 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_75 0x75 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_76 0x76 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_77 0x77 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_78 0x78 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_79 0x79 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7A 0x7a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7B 0x7b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7C 0x7c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_7D 0x7d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x7e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x7f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_80 0x80 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_81 0x81 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_82 0x82 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_83 0x83 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_84 0x84 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_85 0x85 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_86 0x86 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_87 0x87 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_88 0x88 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_89 0x89 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8A 0x8a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8B 0x8b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8C 0x8c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8D 0x8d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8E 0x8e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_8F 0x8f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_90 0x90 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_91 0x91 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_92 0x92 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_93 0x93 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_94 0x94 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_95 0x95 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_96 0x96 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_97 0x97 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_98 0x98 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_99 0x99 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9A 0x9a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9B 0x9b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9C 0x9c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9D 0x9d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9E 0x9e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_9F 0x9f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A0 0xa0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A1 0xa1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A2 0xa2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A3 0xa3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A4 0xa4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A5 0xa5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A6 0xa6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A7 0xa7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A8 0xa8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_A9 0xa9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AA 0xaa /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AB 0xab /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AC 0xac /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AD 0xad /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AE 0xae /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_AF 0xaf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B0 0xb0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B1 0xb1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B2 0xb2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B3 0xb3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B4 0xb4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B5 0xb5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B6 0xb6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B7 0xb7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B8 0xb8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_B9 0xb9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BA 0xba /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BB 0xbb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BC 0xbc /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BD 0xbd /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BE 0xbe /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_BF 0xbf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C0 0xc0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C1 0xc1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C2 0xc2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C3 0xc3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C4 0xc4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C5 0xc5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C6 0xc6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C7 0xc7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C8 0xc8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_C9 0xc9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CA 0xca /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CB 0xcb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CC 0xcc /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CD 0xcd /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CE 0xce /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_CF 0xcf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D0 0xd0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D1 0xd1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D2 0xd2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D3 0xd3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D4 0xd4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D5 0xd5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D6 0xd6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D7 0xd7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D8 0xd8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_D9 0xd9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DA 0xda /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DB 0xdb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DC 0xdc /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DD 0xdd /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DE 0xde /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_DF 0xdf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E0 0xe0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E1 0xe1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E2 0xe2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E3 0xe3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E4 0xe4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E5 0xe5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E6 0xe6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E7 0xe7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E8 0xe8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_E9 0xe9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EA 0xea /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EB 0xeb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EC 0xec /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_ED 0xed /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EE 0xee /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_EF 0xef /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F0 0xf0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F1 0xf1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F2 0xf2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F3 0xf3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F4 0xf4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F5 0xf5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F6 0xf6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F7 0xf7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F8 0xf8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_F9 0xf9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_FA 0xfa /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_FB 0xfb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_FC 0xfc /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_GRP_FD 0xfd /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1 15:8 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_00 0x00 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_01 0x01 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_02 0x02 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_03 0x03 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_04 0x04 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_05 0x05 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_06 0x06 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_07 0x07 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_08 0x08 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_09 0x09 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0A 0x0a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0B 0x0b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0C 0x0c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0D 0x0d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0E 0x0e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_0F 0x0f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_10 0x10 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_11 0x11 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_12 0x12 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_13 0x13 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_14 0x14 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_15 0x15 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_16 0x16 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_17 0x17 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_18 0x18 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_19 0x19 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1A 0x1a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1B 0x1b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1C 0x1c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1D 0x1d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1E 0x1e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_1F 0x1f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_20 0x20 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_21 0x21 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_22 0x22 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_23 0x23 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_24 0x24 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_25 0x25 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_26 0x26 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_27 0x27 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_28 0x28 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_29 0x29 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2A 0x2a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2B 0x2b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2C 0x2c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2D 0x2d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2E 0x2e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_2F 0x2f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_30 0x30 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_31 0x31 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_32 0x32 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_33 0x33 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_34 0x34 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_35 0x35 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_36 0x36 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_37 0x37 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_38 0x38 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_39 0x39 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3A 0x3a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3B 0x3b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3C 0x3c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3D 0x3d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3E 0x3e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_3F 0x3f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_40 0x40 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_41 0x41 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_42 0x42 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_43 0x43 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_44 0x44 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_45 0x45 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_46 0x46 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_47 0x47 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_48 0x48 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_49 0x49 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4A 0x4a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4B 0x4b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4C 0x4c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4D 0x4d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4E 0x4e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_4F 0x4f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_50 0x50 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_51 0x51 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_52 0x52 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_53 0x53 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_54 0x54 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_55 0x55 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_56 0x56 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_57 0x57 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_58 0x58 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_59 0x59 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5A 0x5a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5B 0x5b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5C 0x5c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5D 0x5d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5E 0x5e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_5F 0x5f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_60 0x60 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_61 0x61 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_62 0x62 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_63 0x63 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_64 0x64 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_65 0x65 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_66 0x66 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_67 0x67 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_68 0x68 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_69 0x69 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6A 0x6a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6B 0x6b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6C 0x6c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6D 0x6d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6E 0x6e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_6F 0x6f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_70 0x70 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_71 0x71 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_72 0x72 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_73 0x73 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_74 0x74 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_75 0x75 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_76 0x76 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_77 0x77 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_78 0x78 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_79 0x79 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7A 0x7a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7B 0x7b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7C 0x7c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_7D 0x7d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP 0x7e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP 0x7f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_80 0x80 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_81 0x81 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_82 0x82 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_83 0x83 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_84 0x84 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_85 0x85 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_86 0x86 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_87 0x87 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_88 0x88 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_89 0x89 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8A 0x8a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8B 0x8b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8C 0x8c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8D 0x8d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8E 0x8e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_8F 0x8f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_90 0x90 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_91 0x91 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_92 0x92 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_93 0x93 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_94 0x94 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_95 0x95 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_96 0x96 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_97 0x97 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_98 0x98 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_99 0x99 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9A 0x9a /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9B 0x9b /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9C 0x9c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9D 0x9d /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9E 0x9e /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_9F 0x9f /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A0 0xa0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A1 0xa1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A2 0xa2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A3 0xa3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A4 0xa4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A5 0xa5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A6 0xa6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A7 0xa7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A8 0xa8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_A9 0xa9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AA 0xaa /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AB 0xab /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AC 0xac /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AD 0xad /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AE 0xae /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_AF 0xaf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B0 0xb0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B1 0xb1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B2 0xb2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B3 0xb3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B4 0xb4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B5 0xb5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B6 0xb6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B7 0xb7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B8 0xb8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_B9 0xb9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BA 0xba /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BB 0xbb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BC 0xbc /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BD 0xbd /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BE 0xbe /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_BF 0xbf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C0 0xc0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C1 0xc1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C2 0xc2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C3 0xc3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C4 0xc4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C5 0xc5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C6 0xc6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C7 0xc7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C8 0xc8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_C9 0xc9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CA 0xca /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CB 0xcb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CC 0xcc /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CD 0xcd /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CE 0xce /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_CF 0xcf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D0 0xd0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D1 0xd1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D2 0xd2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D3 0xd3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D4 0xd4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D5 0xd5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D6 0xd6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D7 0xd7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D8 0xd8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_D9 0xd9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DA 0xda /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DB 0xdb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DC 0xdc /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DD 0xdd /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DE 0xde /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_DF 0xdf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E0 0xe0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E1 0xe1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E2 0xe2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E3 0xe3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E4 0xe4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E5 0xe5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E6 0xe6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E7 0xe7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E8 0xe8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_E9 0xe9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EA 0xea /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EB 0xeb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EC 0xec /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_ED 0xed /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EE 0xee /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_EF 0xef /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F0 0xf0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F1 0xf1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F2 0xf2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F3 0xf3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F4 0xf4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F5 0xf5 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F6 0xf6 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F7 0xf7 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F8 0xf8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_F9 0xf9 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_FA 0xfa /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_FB 0xfb /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_FC 0xfc /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_SELECT_MUX1_GRP_FD 0xfd /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_BLK_ACT 30:30 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_BLK_ACT_DISABLE 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_BLK_ACT_ENABLE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_BLK_ACT_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ENABLE 31:31 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ENABLE_DISABLE 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ENABLE_ENABLE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_LOW 0x0000a088 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_LOW_ALIGNMENT 0x00000008 /* */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_LOW_BITS 31:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_LOW 0x0000a08c /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_LOW_BITS 23:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_LOW_BITS_INIT 0x000000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_HIGH 0x0000a090 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_HIGH_ALIGNMENT 0x00000008 /* */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_HIGH_BITS 31:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_HIGH 0x0000a094 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS 23:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT 0x000000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK 0x0000a098 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE0 0:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE0_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE0_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE1 1:1 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE1_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE1_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE2 2:2 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE2_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE2_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE3 3:3 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE3_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE3_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE4 4:4 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE4_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE4_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE5 5:5 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE5_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE5_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE6 6:6 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE6_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE6_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE7 7:7 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE7_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE7_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE8 8:8 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE8_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE8_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE9 9:9 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE9_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE9_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE10 10:10 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE10_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE10_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE11 11:11 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE11_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE11_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE12 12:12 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE12_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE12_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE13 13:13 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE13_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE13_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE14 14:14 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE14_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE14_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE15 15:15 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE15_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_CE15_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL0 16:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL0_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL0_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL1 17:17 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL1_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL1_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL2 18:18 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL2_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL2_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL3 19:19 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL3_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL3_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL4 20:20 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL4_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL4_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL5 21:21 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL5_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL5_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL6 22:22 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL6_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL6_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL7 23:23 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL7_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL7_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL8 24:24 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL8_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL8_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL9 25:25 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL9_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL9_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL10 26:26 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL10_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL10_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL11 27:27 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL11_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL11_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL12 28:28 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL12_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL12_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL13 29:29 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL13_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL13_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL14 30:30 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL14_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL14_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL15 31:31 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL15_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_UNIT_MASK_NVL15_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK 0x0000a09c /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_RD 0:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_RD_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_WR 1:1 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_WR_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_WR_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GATOM 2:2 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GRED 3:3 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_GRED_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CACHE_MGMT 4:4 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PREFETCH 5:5 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH 6:6 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_MEMBAR 7:7 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_MEMBAR_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_MEMBAR_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_RD 8:8 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_RD_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_RD_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_WR 9:9 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_WR_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_WR_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GRED 10:10 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GATOM 11:11 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PACK_RD 12:12 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PACK_RD_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PACK_RD_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_WR 13:13 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GRED 14:14 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM 15:15 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS 22:22 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS 23:23 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_VIDMEM 24:24 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_VIDMEM_ENABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_VIDMEM_DISABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PEER 25:25 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PEER_ENABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_PEER_DISABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_C 26:26 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_NC 27:27 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_TYPE 30:30 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_TYPE_VIRTUAL 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_TYPE_PHYSICAL 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_EXCLUSIVE 31:31 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0 0x0000a0d4 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE 2:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_32MB 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_64MB 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_128MB 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_256MB 0x3 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_512MB 0x4 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENT_SIZE_INIT 0x3 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID 31:22 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_VMMU_CFG0_SEGMENTS_PER_GFID_INIT 0x180 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_TABLE(i) (0x0000a0d8+(i)*4) /* RW-4A */ #define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_TABLE__SIZE_1 12 /* */ #define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP 31:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_SRIOV_VMMU_TABLE_BITMAP_INIT 0x00000000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK 0x0000a3fc /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0xf /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0xc /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0xfffff /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0004c /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL 0x0000a3f8 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x0000a3fc /* */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS 0x0000a3f4 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT 0x0000a3f0 /* R--4R */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* R-E-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* R-E-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT 0x0000a3ec /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS 0x0000a3e8 /* R--4R */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_LINK_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL 0x0000a3e4 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x0000a3fc /* */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS 0x0000a3e0 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT 0x0000a3dc /* R--4R */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* R-E-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* R-E-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT 0x0000a3d8 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS 0x0000a3d4 /* R--4R */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSCE_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR 0x0000a3d0 /* R-E4R */ #define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR 0:0 /* R-EVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR 1:1 /* R-EVF */ #define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PFB_HSMMU0_PRI_MMU_HSHUBMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG 0x0000a3cc /* RWE4R */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i) ((i)*4+1):((i)*4) /* */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x2 /* */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x3 /* */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWEUF */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWEUF */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWEUF */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWEUF */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWEUF */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWEUF */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWEUF */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWEUF */ #define NV_PFB_HSMMU0_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT 0x0000a110 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE 3:0 /* R-EVF */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT 0x1 /* R-E-V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_GRANULARITY 7:4 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_GRANULARITY_INIT 0x5 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE 29:29 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_MODE 30:30 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE 31:31 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO 0x0000a114 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL 31:27 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT 0x00 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI 0x0000a118 /* RW-4R */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL 31:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CG 0x0000a0b0 /* RWE4R */ #define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STATE_CG_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STATE_CG_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STATE_CG_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_DLY_CNT__PROD 0x02 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_STALL_CG_EN__PROD 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_QUIESCENT_CG_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_CNT__PROD 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_SW_OVER_EN 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_PAUSE_CG_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_PAUSE_CG_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_PAUSE_CG_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_HALT_CG_EN_ENABLED 0x1 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_HALT_CG_EN_DISABLED 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG_HALT_CG_EN__PROD 0x0 /* */ #define NV_PFB_HSMMU0_PRI_MMU_CG1 0x0000a0b4 /* RWE4R */ #define NV_PFB_HSMMU0_PRI_MMU_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CG1_SLCG 8:1 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_CG1_SLCG_ENABLED 0x00 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_CG1_SLCG_DISABLED 0xff /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_CG1_SLCG__PROD 0x00 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PG 0x0000a0b8 /* RWE4R */ #define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_EN 16:16 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_DIS_EARLY_WUP 17:17 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_DEEP_ELPG_EN 18:18 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_ELPG_EN 19:19 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_DIDT_DELAY 23:20 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_DIDT_DELAY_HWINIT 0xa /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_RESET_DURATION 26:24 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_RESET_DURATION_HWINIT 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_CLAMP_DELAY 29:27 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_CLAMP_DELAY_HWINIT 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_ZONE_OFF_MASK 30:30 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_SOFT_GATING_EN 31:31 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_HSMMU0_PRI_MMU_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG1 0x0000a0c0 /* RWE4R */ #define NV_PFB_HSMMU0_PRI_MMU_PG1_ZONE_SEQ 23:0 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWE-V */ #define NV_PFB_HSMMU0_PRI_MMU_PG1_ZONE_MASK 31:24 /* RWEVF */ #define NV_PFB_HSMMU0_PRI_MMU_PG1_ZONE_MASK_HWINIT 0xff /* RWE-V */ #endif // __ga102_dev_fb_h__