/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_ctxsw_firmware_h__ #define __ga102_dev_ctxsw_firmware_h__ /* This file is autogenerated. Do not edit */ #define NV_CTXSW_FALCON 0x0003FFFF:0x00000000 /* RW--D */ #define NV_CTXSW_FIRMWARE 0x0003FFFF:0x00000000 /* RW--D */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK 0x0000a000 /* RWI4R */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK 0x0000a100 /* RWI4R */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x0000a200 /* RWI4R */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK 0x0000a300 /* RWI4R */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x0000a400 /* RWI4R */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x0000a500 /* RWI4R */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK 0x00003a00 /* RWI4R */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK 0x0000a600 /* RWI4R */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x00000008 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0000a700 /* RWI4R */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x0000f400 /* RWI4R */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x0000fc00 /* RWI4R */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x0000fd00 /* RWI4R */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x0000fe00 /* RWI4R */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x0000ff00 /* RWI4R */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x00006300+(i)*1024) /* RW-4A */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x0000ac00+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK 0x00006400 /* RW-4R */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x00006500 /* RW-4R */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK 0x00006600 /* RW-4R */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x00006700 /* RW-4R */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK 0x00006800 /* RW-4R */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x00006900 /* RW-4R */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x00006a00 /* RW-4R */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK 0x00006c00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK 0x00006f00 /* RW-4R */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x00007800 /* RW-4R */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x00007900 /* RW-4R */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK 0x00007a00 /* RW-4R */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK 0x00007b00 /* RW-4R */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x00007c00 /* RW-4R */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK 0x00007d00 /* RW-4R */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x00007e00 /* RW-4R */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK 0x00007f00 /* RW-4R */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CTXSW_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK 0x00008800 /* RW-4R */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x00008900 /* RW-4R */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK 0x00008b00 /* RW-4R */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_CTXSW_FALCON_IRQSSET 0x00000000 /* -W-4R */ #define NV_CTXSW_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ1_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ2_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ3_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ4_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ5_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ6_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ7_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */ #define NV_CTXSW_FALCON_IRQSSET_EXT_EXTIRQ8_SET 1 /* */ #define NV_CTXSW_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR 0x00000100 /* -W-4R */ #define NV_CTXSW_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ #define NV_CTXSW_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQSTAT 0x00000200 /* R--4R */ #define NV_CTXSW_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMODE 0x00000300 /* RW-4R */ #define NV_CTXSW_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_MTHD_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_MTHD_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_MTHD_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_HALT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_HALT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXTERR_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_INIT 0x000000fc /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 1 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0 /* */ #define NV_CTXSW_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_IRQMODE_LVL_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_DMA_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQMODE_LVL_DMA_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK 0x00003800 /* RW-4R */ #define NV_CTXSW_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x00006900 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_GPTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_GPTMR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_WDTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_WDTMR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_MTHD_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_MTHD_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_CTXSW_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_CTXSW_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_HALT_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_HALT_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_EXTERR_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXTERR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_ENABLE 0x000000ff /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 1 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0 /* */ #define NV_CTXSW_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_IRQSCMASK_DMA_ENABLE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_IRQSCMASK_DMA_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQMSET 0x00000400 /* -W-4R */ #define NV_CTXSW_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR 0x00000500 /* -W-4R */ #define NV_CTXSW_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_CTXSW_FALCON_IRQMCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_IRQMASK 0x00000600 /* R--4R */ #define NV_CTXSW_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IRQDEST 0x00000700 /* RW-4R */ #define NV_CTXSW_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT 15:8 /* */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT 31:24 /* */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2 0x00000f00 /* RW-4R */ #define NV_CTXSW_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x0000a400 /* */ #define NV_CTXSW_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST2_HOST_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST2_HOST_DMA_FALCON 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_HOST_DMA_HOST 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_GPTMRINT 0x00000800 /* RW-4R */ #define NV_CTXSW_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x00006800 /* */ #define NV_CTXSW_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_GPTMRVAL 0x00000900 /* RW-4R */ #define NV_CTXSW_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x00006800 /* */ #define NV_CTXSW_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_GPTMRCTL 0x00000a00 /* RW-4R */ #define NV_CTXSW_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x00006800 /* */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMREN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PTIMER0 0x00000b00 /* R--4R */ #define NV_CTXSW_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x00006f00 /* */ #define NV_CTXSW_FALCON_PTIMER0_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_PTIMER1 0x00000c00 /* R--4R */ #define NV_CTXSW_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x00006f00 /* */ #define NV_CTXSW_FALCON_PTIMER1_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_WDTMRVAL 0x00000d00 /* RW-4R */ #define NV_CTXSW_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0000a700 /* */ #define NV_CTXSW_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMRCTL 0x00000e00 /* RW-4R */ #define NV_CTXSW_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0000a700 /* */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMREN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_MTHDDATA 0x00001900 /* R--4R */ #define NV_CTXSW_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */ #define NV_CTXSW_FALCON_MTHDID 0x00001a00 /* RW-4R */ #define NV_CTXSW_FALCON_MTHDID__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDID_ID 11:0 /* RWXVF */ #define NV_CTXSW_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */ #define NV_CTXSW_FALCON_MTHDID_PRIV 15:15 /* RWXVF */ #define NV_CTXSW_FALCON_MTHDID_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_MTHDID_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_MTHDID_WPEND 16:16 /* R-XVF */ #define NV_CTXSW_FALCON_MTHDID_WPEND_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_MTHDID_WPEND_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_MTHDWDAT 0x00001b00 /* RW-4R */ #define NV_CTXSW_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_MTHDCOUNT 0x00001c00 /* R--4R */ #define NV_CTXSW_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */ #define NV_CTXSW_FALCON_MTHDCOUNT_COUNT_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_MTHDPOP 0x00001d00 /* -W-4R */ #define NV_CTXSW_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDPOP_POP 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_MTHDPOP_POP_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_MTHDPOP_POP_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_MTHDRAMSZ 0x00001e00 /* RW-4R */ #define NV_CTXSW_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */ #define NV_CTXSW_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CURCTX 0x00001400 /* RW-4R */ #define NV_CTXSW_FALCON_CURCTX__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_CURCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CURCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */ #define NV_CTXSW_FALCON_CURCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_NXTCTX 0x00001500 /* RW-4R */ #define NV_CTXSW_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_NXTCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_NXTCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */ #define NV_CTXSW_FALCON_NXTCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CTXACK 0x00001600 /* -W-4R */ #define NV_CTXSW_FALCON_CTXACK__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_CTXACK_SAVE_ACK_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CTXACK_SAVE_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_CTXACK_REST_ACK_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CTXACK_REST_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_MAILBOX0 0x00001000 /* RW-4R */ #define NV_CTXSW_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_MAILBOX1 0x00001100 /* RW-4R */ #define NV_CTXSW_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN 0x00001200 /* RW-4R */ #define NV_CTXSW_FALCON_ITFEN__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_ITFEN_CTXEN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN_CTXEN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_CTXEN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_ITFEN_MTHDEN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN_MTHDEN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_MTHDEN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_ITFEN_PRIV_POSTWR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_ITFEN_CTXSW_NACK_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ITFEN_CTXSW_NACK_FALSE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */ #define NV_CTXSW_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IDLESTATE 0x00001300 /* RW-4R */ #define NV_CTXSW_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x00007800 /* */ #define NV_CTXSW_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */ #define NV_CTXSW_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_FHSTATE 0x00001700 /* R--4R */ #define NV_CTXSW_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x00007900 /* */ #define NV_CTXSW_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */ #define NV_CTXSW_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */ #define NV_CTXSW_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */ #define NV_CTXSW_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */ #define NV_CTXSW_FALCON_FHSTATE_STALL_REQ_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_FHSTATE_STALL_REQ_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_PRIVSTATE 0x00001800 /* RW-4R */ #define NV_CTXSW_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x0000f400 /* */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_PRIVSTATE_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SFTRESET 0x00001f00 /* RW-4R */ #define NV_CTXSW_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_SFTRESET_EXT 0:0 /* RWXVF */ #define NV_CTXSW_FALCON_SFTRESET_EXT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SFTRESET_EXT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL 0x00002900 /* RW-4R */ #define NV_CTXSW_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */ #define NV_CTXSW_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */ #define NV_CTXSW_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */ #define NV_CTXSW_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */ #define NV_CTXSW_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */ #define NV_CTXSW_FALCON_ENGCTL_STALLREQ_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ENGCTL_STALLREQ_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */ #define NV_CTXSW_FALCON_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ENGCTL_STALLACK_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ADDR 0x00002b00 /* RW-4R */ #define NV_CTXSW_FALCON_ADDR__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_ADDR_LSB 5:0 /* RWIVF */ #define NV_CTXSW_FALCON_ADDR_LSB_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ADDR_MSB 11:6 /* RWIVF */ #define NV_CTXSW_FALCON_ADDR_MSB_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_ADDR_EXT 11:0 /* */ #define NV_CTXSW_FALCON_DMACTL 0x00004300 /* RW-4R */ #define NV_CTXSW_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */ #define NV_CTXSW_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */ #define NV_CTXSW_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */ #define NV_CTXSW_FALCON_DMATRFBASE 0x00004400 /* RW-4R */ #define NV_CTXSW_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMATRFMOFFS 0x00004500 /* RW-4R */ #define NV_CTXSW_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMATRFCMD 0x00004600 /* RW-4R */ #define NV_CTXSW_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */ #define NV_CTXSW_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */ #define NV_CTXSW_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_NOTIFY_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_NOTIFY_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_4B 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_8B 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_16B 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_32B 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_64B 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_128B 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */ #define NV_CTXSW_FALCON_DMATRFCMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMATRFCMD_ERROR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMATRFFBOFFS 0x00004700 /* RW-4R */ #define NV_CTXSW_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_FB 0x00004800 /* RW-4R */ #define NV_CTXSW_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_CP 0x00004900 /* RW-4R */ #define NV_CTXSW_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x0000b000 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x0000b100 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x0000b200 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x0000b300 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x0000b400 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x0000b500 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x0000b600 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x0000b700 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CTL 0x0000b800 /* RW-4R */ #define NV_CTXSW_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_HIGH 0x0000b900 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_LOW 0x0000ba00 /* R--4R */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x00006400 /* */ #define NV_CTXSW_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_IMEMC(i) (0x00006000+(i)*1024) /* RW-4A */ #define NV_CTXSW_FALCON_IMEMC__SIZE_1 1 /* */ #define NV_CTXSW_FALCON_IMEMC__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_IMEMC_OFFS 7:2 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_BLK 23:8 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_AINCW 24:24 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEMC_AINCR 25:25 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMEMC_SECURE 28:28 /* RWIVF */ #define NV_CTXSW_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEMD(i) (0x00006100+(i)*1024) /* RW-4A */ #define NV_CTXSW_FALCON_IMEMD__SIZE_1 1 /* */ #define NV_CTXSW_FALCON_IMEMD__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_IMEMD_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMEMT(i) (0x00006200+(i)*1024) /* RW-4A */ #define NV_CTXSW_FALCON_IMEMT__SIZE_1 1 /* */ #define NV_CTXSW_FALCON_IMEMT__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_IMEMT_TAG 15:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMEMT_FAULT_CORRECTED 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMT_FAULT_CORRECTED_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEMT_FAULT_UNCORRECTED 17:17 /* R-IVF */ #define NV_CTXSW_FALCON_IMEMT_FAULT_UNCORRECTED_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEMC(i) (0x00007000+(i)*512) /* RW-4A */ #define NV_CTXSW_FALCON_DMEMC__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_DMEMC__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_OFFS 7:2 /* */ #define NV_CTXSW_FALCON_DMEMC_OFFS_INIT 0 /* */ #define NV_CTXSW_FALCON_DMEMC_BLK 23:8 /* */ #define NV_CTXSW_FALCON_DMEMC_BLK_INIT 0 /* */ #define NV_CTXSW_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_VA 28:28 /* RWIVF */ #define NV_CTXSW_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMEMC_MISS 29:29 /* R-IVF */ #define NV_CTXSW_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ #define NV_CTXSW_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ #define NV_CTXSW_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEMD(i) (0x00007100+(i)*512) /* RW-4A */ #define NV_CTXSW_FALCON_DMEMD__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_DMEMD__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_DMEMD_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_DMEMT(i) (0x00008400+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_DMEMT__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_DMEMT__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_DMEMT_TAG 15:0 /* -WXVF */ #define NV_CTXSW_FALCON_DMEMT_FAULTED 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_DMEMT_FAULTED_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEML(i) (0x0000a800+(i)*256) /* -W-4A */ #define NV_CTXSW_FALCON_DMEML__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_DMEML__PRIV_LEVEL_MASK NV_CTXSW_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FALCON_DMEML_LVL 2:0 /* -WXVF */ #define NV_CTXSW_FALCON_DMEM_DUMMY 0x00009600 /* R--4R */ #define NV_CTXSW_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_CTXSW_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x0000a100 /* */ #define NV_CTXSW_FALCON_IMEM_DUMMY 0x00006d00 /* R--4R */ #define NV_CTXSW_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_CTXSW_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x0000a000 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x0000c000+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x0000fc00 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x0000c400+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x0000fd00 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x0000c800+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x0000fe00 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x0000cc00+(i)*256) /* RW-4A */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x0000ff00 /* */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PRGNVER 0x0000f500 /* R-I4R */ #define NV_CTXSW_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */ #define NV_CTXSW_FALCON_PRGNVER_MAJOR_DEFT 0x00000002 /* R-I-V */ #define NV_CTXSW_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */ #define NV_CTXSW_FALCON_PRGNVER_MINOR_DEFT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */ #define NV_CTXSW_FALCON_PRGNVER_BUGFIX_DEFT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG 0x00004200 /* R--4R */ #define NV_CTXSW_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */ #define NV_CTXSW_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */ #define NV_CTXSW_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG1 0x00004b00 /* R--4R */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000002 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000004 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2 0x00003d00 /* R--4R */ #define NV_CTXSW_FALCON_HWCFG2_SHA 0:0 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_VHR 7:7 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_HS 8:8 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_HWCFG3 0x00009e00 /* R--4R */ #define NV_CTXSW_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ #define NV_CTXSW_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ #define NV_CTXSW_FALCON_CGCTL 0x00002800 /* RW-4R */ #define NV_CTXSW_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CG2 0x00004d00 /* RWI4R */ #define NV_CTXSW_FALCON_CG2__PRIV_LEVEL_MASK 0x00007a00 /* */ #define NV_CTXSW_FALCON_CG2_SLCG 17:1 /* */ #define NV_CTXSW_FALCON_CG2_SLCG_ENABLED 0 /* */ #define NV_CTXSW_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */ #define NV_CTXSW_FALCON_CG2_SLCG__PROD 0x000A0 /* */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ #define NV_CTXSW_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL 0x00009000 /* RW-4R */ #define NV_CTXSW_FALCON_SCTL__PRIV_LEVEL_MASK 0x0000a600 /* */ #define NV_CTXSW_FALCON_SCTL_LSMODE 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_HSMODE 1:1 /* R--VF */ #define NV_CTXSW_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_UCODE_LEVEL 5:4 /* */ #define NV_CTXSW_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */ #define NV_CTXSW_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL1 0x00009400 /* RW-4R */ #define NV_CTXSW_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_CTXSW_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */ #define NV_CTXSW_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL 0x00003900 /* RW-4R */ #define NV_CTXSW_FALCON_HSCTL__PRIV_LEVEL_MASK 0x00003a00 /* */ #define NV_CTXSW_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_TRACEPC_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_TRACEPC_DISABLE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_HSCTL_SP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_HSCTL_SP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_ERB 0x0000bb00 /* -W-4R */ #define NV_CTXSW_FALCON_SAFETY_ERB_DATA 31:0 /* -WXVF */ #define NV_CTXSW_FALCON_SAFETY_ERB_DATA_CORRECTED_ERR 0xeafe0c00 /* -W--V */ #define NV_CTXSW_FALCON_SAFETY_ERB_DATA_UNCORRECTED_ERR 0xeafe1cff /* -W--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX 0x0000bc00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_DATA 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRADDR 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRADDR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE 31:24 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PF 0x000000f0 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PF 0x000000f1 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_SCP 0x000000f2 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_SCP 0x000000f3 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_SCP 0x000000f3 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_DMA 0x000000f4 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_DMA 0x000000f5 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_DMA 0x000000f5 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PMB 0x000000f6 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PMB 0x000000f7 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_PMB 0x000000f7 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_LDST 0x000000f8 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_PMB 0x000000f9 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_DMA 0x000000fa /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_SCP 0x000000fb /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_SHA 0x000000fc /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_SHA 0x000000fd /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_RISCV 0x000000fe /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_RISCV 0x000000ff /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IROM 0x000000e0 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IROM 0x000000e1 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL 0x0000bd00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_CTRL__PRIV_LEVEL_MASK 0x00006c00 /* */ #define NV_CTXSW_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN 16:16 /* R-IVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS 5:4 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_INIT 0x00000002 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_IMEM_ECC_DIS 1:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_INIT 0x00000002 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR 0x0000be00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_VALUE 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_HI 0x0000bf00 /* RW-4R */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_HI_VALUE 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_SAFETY_ERR_ADDR_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_OS 0x00002000 /* RW-4R */ #define NV_CTXSW_FALCON_OS_VERSION 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_RM 0x00002100 /* RW-4R */ #define NV_CTXSW_FALCON_RM_CONFIG 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SOFT_PM 0x00002200 /* RW-4R */ #define NV_CTXSW_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x00007b00 /* */ #define NV_CTXSW_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */ #define NV_CTXSW_FALCON_SOFT_PM_TRIGGER_START_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_SOFT_PM_TRIGGER_END_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */ #define NV_CTXSW_FALCON_SOFT_PM_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_SOFT_MODE 0x00002300 /* RW-4R */ #define NV_CTXSW_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x00007b00 /* */ #define NV_CTXSW_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */ #define NV_CTXSW_FALCON_SOFT_MODE_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM 0x00002a00 /* RW-4R */ #define NV_CTXSW_FALCON_PMM__PRIV_LEVEL_MASK 0x00007b00 /* */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_CODE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_IPND 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_SB 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0000000d /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0000000e /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x00000010 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x00000011 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0x0000000d /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0x0000000e /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */ #define NV_CTXSW_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1 0x00002400 /* RW-4R */ #define NV_CTXSW_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x0000a500 /* */ #define NV_CTXSW_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */ #define NV_CTXSW_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x00000040 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */ #define NV_CTXSW_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DEBUGINFO 0x00002500 /* RW-4R */ #define NV_CTXSW_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_SP_MIN 0x00009c00 /* RW-4R */ #define NV_CTXSW_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x00007c00 /* */ #define NV_CTXSW_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_SP_MIN_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_EXCI 0x00003400 /* R--4R */ #define NV_CTXSW_FALCON_EXCI__PRIV_LEVEL_MASK 0x00007d00 /* */ #define NV_CTXSW_FALCON_EXCI_EXPC 19:0 /* R-XVF */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_TRAP0 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_TRAP1 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_TRAP2 0x00000002 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_TRAP3 0x00000003 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_ILL_INS 0x00000008 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_INV_INS 0x00000009 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_MISS_INS 0x0000000a /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0000000b /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0000000d /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0000000f /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x00000010 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x00000011 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x00000012 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x00000013 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXCAUSE_DMEM_FAULT_INS 0x00000014 /* R---V */ #define NV_CTXSW_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */ #define NV_CTXSW_FALCON_EXCI2 0x00002f00 /* R--4R */ #define NV_CTXSW_FALCON_EXCI2__PRIV_LEVEL_MASK 0x00007d00 /* */ #define NV_CTXSW_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */ #define NV_CTXSW_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_SVEC_SPR 0x00003500 /* R--4R */ #define NV_CTXSW_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x00007e00 /* */ #define NV_CTXSW_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */ #define NV_CTXSW_FALCON_SVEC_SPR_SIGPASS_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_SVEC_SPR_SIGPASS_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL 0x00004000 /* RW-4R */ #define NV_CTXSW_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x0000a200 /* */ #define NV_CTXSW_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ #define NV_CTXSW_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ #define NV_CTXSW_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS 0x00004c00 /* -W-4R */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_CTXSW_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_CTXSW_FALCON_STACKCFG 0x00004e00 /* RW-4R */ #define NV_CTXSW_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */ #define NV_CTXSW_FALCON_STACKCFG_BOTTOM_INIT 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_STACKCFG_SPEXC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_STACKCFG_SPEXC_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_STACKCFG_SPEXC_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_BOOTVEC 0x00004100 /* RW-4R */ #define NV_CTXSW_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x00006500 /* */ #define NV_CTXSW_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL 0x00009500 /* RW-4R */ #define NV_CTXSW_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x00006a00 /* */ #define NV_CTXSW_FALCON_DBGCTL_VAL 9:0 /* */ #define NV_CTXSW_FALCON_DBGCTL_VAL_INIT 0 /* */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_TRACE_MODE_FULL 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_TRACE_MODE_STACK 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_DBGCTL_CYA 31:16 /* RWIVF */ #define NV_CTXSW_FALCON_DBGCTL_CYA_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DBGCTL_CYA_ENABLE 0x00008afe /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1 0x00002600 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT1_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT1_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT1_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT1_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT1_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT1_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT1_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT1_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2 0x00002700 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT2_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT2_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT2_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT2_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT2_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT2_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT2_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT2_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3 0x00002c00 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT3_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT3_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT3_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT3_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT3_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT3_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT3_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT3_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4 0x00002d00 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT4_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT4_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT4_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT4_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT4_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT4_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT4_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT4_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5 0x00002e00 /* RW-4R */ #define NV_CTXSW_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x00007f00 /* */ #define NV_CTXSW_FALCON_IBRKPT5_PC 23:0 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT5_PC_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT5_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT5_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT5_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_EN 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_IBRKPT5_EN_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IBRKPT5_EN_DISABLE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IBRKPT5_EN_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD 0x00008000 /* RW-4R */ #define NV_CTXSW_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CTXSW_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_JRUN 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RUNB 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_JRUNB 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_JSTEP 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RCM 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_WCM 0x0000000d /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_OPC_SBU 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_SZ_B 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_SZ_HW 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_SZ_W 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_IV0 0x00000010 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_IV1 0x00000011 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_EV 0x00000013 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_SP 0x00000014 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_PC 0x00000015 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_IMB 0x00000016 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_DMB 0x00000017 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_CSW 0x00000018 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_CCR 0x00000019 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_SEC 0x0000001a /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_CTX 0x0000001b /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_EXCI 0x0000001c /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_SEC1 0x0000001e /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_IMB1 0x0000001e /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_DMB1 0x0000001f /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT2 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_RSTAT5 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_WB0 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_WB1 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_WB2 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_IDX_WB3 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_FAULTED 13:13 /* R-IVF */ #define NV_CTXSW_FALCON_ICD_CMD_FAULTED_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_ICD_CMD_FAULTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_FAULTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */ #define NV_CTXSW_FALCON_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_ERROR_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */ #define NV_CTXSW_FALCON_ICD_CMD_RDVLD_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_RDVLD_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FALCON_ICD_CMD_PARM 31:16 /* */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK 31:16 /* */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_ADDR 0x00008100 /* RW-4R */ #define NV_CTXSW_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CTXSW_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_WDATA 0x00008200 /* RW-4R */ #define NV_CTXSW_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CTXSW_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_ICD_RDATA 0x00008300 /* R--4R */ #define NV_CTXSW_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x00008800 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 3 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 4 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 5 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 6 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 7 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 3 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 2 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 1 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */ #define NV_CTXSW_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */ #define NV_CTXSW_FALCON_RSTAT0 0x00003600 /* R--4R */ #define NV_CTXSW_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x00008900 /* */ #define NV_CTXSW_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_VALID 28:28 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3 0x00003700 /* R--4R */ #define NV_CTXSW_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */ #define NV_CTXSW_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */ #define NV_CTXSW_FALCON_TRACEIDX 0x00005200 /* RW-4R */ #define NV_CTXSW_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x00006700 /* */ #define NV_CTXSW_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */ #define NV_CTXSW_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_CTXSW_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */ #define NV_CTXSW_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */ #define NV_CTXSW_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_TRACEPC 0x00005300 /* R--4R */ #define NV_CTXSW_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x00006700 /* */ #define NV_CTXSW_FALCON_TRACEPC_PC 23:0 /* R--VF */ #define NV_CTXSW_FALCON_TRACEINFO 0x00005f00 /* R--4R */ #define NV_CTXSW_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x00006700 /* */ #define NV_CTXSW_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */ #define NV_CTXSW_FALCON_IMCTL 0x00005000 /* RW-4R */ #define NV_CTXSW_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMCTL_CMD 26:24 /* RWXVF */ #define NV_CTXSW_FALCON_IMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_CMD_IMINV 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_DEBUG 0x00005700 /* RW-4R */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_CMD_NOP 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_IMSTAT 0x00005100 /* RW-4R */ #define NV_CTXSW_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMSTAT_VAL 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_IMFILLRNG0 0x00005400 /* RW-4R */ #define NV_CTXSW_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLRNG0_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLRNG0_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMFILLRNG1 0x00005500 /* RW-4R */ #define NV_CTXSW_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLRNG1_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLRNG1_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_IMFILLCTL 0x00005600 /* RW-4R */ #define NV_CTXSW_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */ #define NV_CTXSW_FALCON_IMFILLCTL_NBLOCKS_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_DMCTL 0x00009800 /* RW-4R */ #define NV_CTXSW_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_CTXSW_FALCON_DMCTL_CMD 26:24 /* RWXVF */ #define NV_CTXSW_FALCON_DMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMINV 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMBLK 0x00000002 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMTAG 0x00000003 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMCLEAN 0x00000005 /* RW--V */ #define NV_CTXSW_FALCON_DMCTL_CMD_DMLVL 0x00000006 /* RW--V */ #define NV_CTXSW_FALCON_DMSTAT 0x00009900 /* RW-4R */ #define NV_CTXSW_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0000a300 /* */ #define NV_CTXSW_FALCON_DMSTAT_VAL 31:0 /* RWXVF */ #define NV_CTXSW_FALCON_DMVACTL 0x00009a00 /* RW-4R */ #define NV_CTXSW_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x00006600 /* */ #define NV_CTXSW_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */ #define NV_CTXSW_FALCON_DMVACTL_BOUND_INIT 0x00000020 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERRSTAT 0x00009100 /* RW-4R */ #define NV_CTXSW_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x00008b00 /* */ #define NV_CTXSW_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */ #define NV_CTXSW_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERRSTAT_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERRSTAT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_CSBERRSTAT_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */ #define NV_CTXSW_FALCON_CSBERRSTAT_VALID_INIT 0x00000000 /* RWI-V */ #define NV_CTXSW_FALCON_CSBERRSTAT_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FALCON_CSBERRSTAT_VALID_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FALCON_CSBERR_ADDR 0x00009300 /* R--4R */ #define NV_CTXSW_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x00008b00 /* */ #define NV_CTXSW_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */ #define NV_CTXSW_FALCON_CSBERR_INFO 0x00009200 /* R--4R */ #define NV_CTXSW_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x00008b00 /* */ #define NV_CTXSW_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX 0x0002c000 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX_PTR 27:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX_PTR_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX_TARGET 29:28 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX_TARGET_VID_MEM 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX_VALID 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX_VALID_FALSE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CURRENT_CTX_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_NEW_CTX 0x0002c100 /* RW-4R */ #define NV_CTXSW_FIRMWARE_NEW_CTX_PTR 27:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_NEW_CTX_PTR_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_NEW_CTX_TARGET 29:28 /* RWEVF */ #define NV_CTXSW_FIRMWARE_NEW_CTX_TARGET_VID_MEM 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_NEW_CTX_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_NEW_CTX_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_NEW_CTX_VALID 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_NEW_CTX_VALID_FALSE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_NEW_CTX_VALID_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_METHOD_DATA 0x00014000 /* RW-4R */ #define NV_CTXSW_FIRMWARE_METHOD_DATA_V 31:0 /* RWXVF */ #define NV_CTXSW_FIRMWARE_METHOD_DATA_V_ELPG_LIST 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_DATA_V_GPCRG_LIST 0x00000002 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_DATA_A 0x00014300 /* RW-4R */ #define NV_CTXSW_FIRMWARE_METHOD_DATA_A_V 31:0 /* RWXVF */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH 0x00014100 /* -W-4R */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_PRIV 31:31 /* -WXVF */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR 11:0 /* -WEVF */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_NOP 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_WFI_SAVE 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_WFI_RESTORE 0x00000002 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_BIND_POINTER 0x00000003 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_BIND_POINTER_ONLY 0x00000060 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_HALT_PIPELINE 0x00000004 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_HALT_PIPELINE_NEW 0x00000007 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_UNHALT_PIPELINE 0x00000005 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CONTEXT_RESET 0x00000006 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 0x00000010 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_PREPARE_FOR_INITIALIZATION 0x00000011 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_WFI_SAVE_ONLY 0x00000008 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 0x00000009 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_WFI_SAVE_RESTORE 0x0000000a /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_WFI 0x0000000b /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_NOCHSW_MODE 0x0000000c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x0000000d /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_DISABLE_RAMCHAIN_SCRUB 0x0000000e /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x0000000f /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_RESTORE_GOLDEN 0x00000015 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x00000016 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x00000025 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x0000001a /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_INIT_MME_SHADOW_RAM 0x0000002a /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_INIT_BUNDLE_DECODERS 0x0000002b /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x0000002c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x0000002d /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_SMC_LTS_MASK_INDEX 0x0000002e /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_ASSIGN_SMC_LTS_MASK 0x0000002f /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x00000030 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x00000031 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x00000032 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SAVE_REGLIST 0x00000033 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_RESTORE_REGLIST 0x00000034 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_UCODE_RECONFIG 0x00000035 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CHECK_GPCCS_INIT_COMPLETE 0x00000036 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_STOP_CTXSW 0x00000038 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_START_CTXSW 0x00000039 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x0000003a /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_DISABLE_ACCESS_COUNTER 0x0000003c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_INSTANCE 0x0000003d /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_LO 0x0000003e /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_HI 0x0000003f /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_METHOD_INIT 0x00000040 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_BUNDLE_INIT_COMPUTE 0x00000041 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_BUNDLE_INIT_2D 0x00000042 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_BUNDLE_INIT_3D 0x00000043 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_BUNDLE_INIT_MEM2MEM 0x00000044 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x00000054 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x00000055 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x00000056 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CRC_CHECK_CALCULATE 0x00000057 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x00000058 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x00000059 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_INJECT_STACK_CANARY_ERROR 0x00000070 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SHUTDOWN_UCODE 0x00000012 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS 0x00000013 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS_HI 0x0000001e /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_PRIV_OFFSET 0x00000014 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x0000001c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x0000001f /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_GFXP_RC_OFFSET 0x0000001d /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x00000017 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x00000022 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_ZCULL_PRIV_OFFSET 0x00000018 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_ZCULL_MODE 0x00000019 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CBC_CLEAR_ACTIVE 0x0000001b /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_FMODEL_TESTS 0x00000020 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x00000021 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SET_GFID 0x00000024 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS 0x00000026 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x00000023 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_PM_PRIV_OFFSET 0x00000027 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SEND_PM_MODE 0x00000028 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_TEST_MODE 0x00000029 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_CONTROL_ZBC_TABLES_SAVE 0x00000061 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_START 0x00000062 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_END 0x00000063 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_RESTORE_SM_PERF_COUNTERS 0x00000064 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_START 0x00000069 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_STOP 0x0000006a /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_RESTORE_HWPM_CONTROL_REGS 0x00000065 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_PERFORM_PRE_SAVE_TASKS 0x0000006b /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_ADR_PERFORM_PRE_RESTORE_TASKS 0x0000006c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A 0x00014200 /* -W-4R */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_PRIV 31:31 /* -WXVF */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR 11:0 /* -WEVF */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_NOP 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_WFI_SAVE 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_WFI_RESTORE 0x00000002 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_BIND_POINTER 0x00000003 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_BIND_POINTER_ONLY 0x00000060 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_HALT_PIPELINE 0x00000004 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_HALT_PIPELINE_NEW 0x00000007 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_UNHALT_PIPELINE 0x00000005 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CONTEXT_RESET 0x00000006 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_DISCOVER_IMAGE_SIZE 0x00000010 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_PREPARE_FOR_INITIALIZATION 0x00000011 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_WFI_SAVE_ONLY 0x00000008 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_WFI_GOLDEN_SAVE 0x00000009 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_WFI_SAVE_RESTORE 0x0000000a /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_WFI 0x0000000b /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_NOCHSW_MODE 0x0000000c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x0000000d /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_DISABLE_RAMCHAIN_SCRUB 0x0000000e /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x0000000f /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_RESTORE_GOLDEN 0x00000015 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x00000016 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_DISCOVER_PM_IMAGE_SIZE 0x00000025 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x0000001a /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_INIT_MME_SHADOW_RAM 0x0000002a /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_INIT_BUNDLE_DECODERS 0x0000002b /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x0000002c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x0000002d /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SET_SMC_LTS_MASK_INDEX 0x0000002e /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_ASSIGN_SMC_LTS_MASK 0x0000002f /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x00000030 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SET_REGLIST_BIND_INSTANCE 0x00000031 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x00000032 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SAVE_REGLIST 0x00000033 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_RESTORE_REGLIST 0x00000034 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_UCODE_RECONFIG 0x00000035 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CHECK_GPCCS_INIT_COMPLETE 0x00000036 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_STOP_CTXSW 0x00000038 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_START_CTXSW 0x00000039 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x0000003a /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_DISABLE_ACCESS_COUNTER 0x0000003c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x00000054 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x00000055 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x00000056 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CRC_CHECK_CALCULATE 0x00000057 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x00000058 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x00000059 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_READ_PHYS_MEM 0x00000067 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_ENABLE_PHYS_MEM_READS 0x00000068 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SHUTDOWN_UCODE 0x00000012 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS 0x00000013 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS_HI 0x0000001e /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_PRIV_OFFSET 0x00000014 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x0000001c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x0000001f /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_GFXP_RC_OFFSET 0x0000001d /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x00000017 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x00000022 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_ZCULL_PRIV_OFFSET 0x00000018 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_ZCULL_MODE 0x00000019 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CBC_CLEAR_ACTIVE 0x0000001b /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_FMODEL_TESTS 0x00000020 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SET_WATCHDOG_TIMEOUT 0x00000021 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SET_GFID 0x00000024 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS 0x00000026 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x00000023 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_PM_PRIV_OFFSET 0x00000027 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SEND_PM_MODE 0x00000028 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_TEST_MODE 0x00000029 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_PCIE_TRAINING 0x00000050 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_CONTROL_ZBC_TABLES_SAVE 0x00000061 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_START 0x00000062 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_END 0x00000063 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_RESTORE_SM_PERF_COUNTERS 0x00000064 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_RESTORE_HWPM_CONTROL_REGS 0x00000065 /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_PERFORM_PRE_SAVE_TASKS 0x0000006b /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_PERFORM_PRE_RESTORE_TASKS 0x0000006c /* -W--V */ #define NV_CTXSW_FIRMWARE_METHOD_PUSH_A_ADR_INJECT_STACK_CANARY_ERROR 0x00000070 /* -W--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SM_CTL 0x0002c200 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_SM_CTL_TRIVIAL_ACK 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SM_CTL_TRIVIAL_ACK_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SM_CTL_TRIVIAL_ACK_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SM_CTL_TRIVIAL_ACK__PROD 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK 0x0002c300 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK_CTXSW 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK_CTXSW_I 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK_CTXSW_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK_STALL 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK_STALL_I 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK_STALL_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK_FE_INTERVAL_TIMER 3:3 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK_FE_INTERVAL_TIMER_I 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_ACK_FE_INTERVAL_TIMER_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_HOST_ACK 0x0002dc00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_HOST_ACK_PREEMPTED 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_HOST_ACK_PREEMPTED_TRUE 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_HOST_ACK_PREEMPTED_FALSE 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_CURRENT_CTX_ID 0x0002dd00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_CURRENT_CTX_ID_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_CURRENT_CTX_ID_V_ZERO 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_GFID 0x0002de00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_GFID_V 5:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_GFID_V_ZERO 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_DATA 0x00022e00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_DATA_FIELD 31:0 /* RWXVF */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG 0x00022f00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION 7:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_NONE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_ENGINE_RESET 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CONTEXT_RESET 0x00000002 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_INSTANCE_BIND 0x00000003 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_SAVE_ENGINE_REGS 0x00000006 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_RESTORE_ENGINE_REGS 0x00000007 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_SAVE 0x00000008 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE 0x0000000e /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE 0x00000010 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE 0x00000011 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE 0x00000009 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE_ONLY 0x0000000a /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE_ONLY 0x00000005 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE_ONLY 0x00000012 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE_ONLY 0x00000013 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_RESTORE 0x0000000f /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_RESTORE 0x00000014 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_RESTORE 0x00000015 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_RESTORE 0x0000000b /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_RESTORE 0x0000000c /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_PATCH_BUFFER_END 0x0000000d /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_STREAM_TAG_ACTION_CTXSW_END 0x00000004 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_READY 0x0002c400 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_READY_STARTUP 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_READY_STARTUP_COMPLETE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_READY_STARTUP_IN_PROGRESS 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS 0x0002c800 /* -W-4R */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_FORCE_CLKS_ON 0:0 /* -WEVF */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_FORCE_CLKS_ON_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_FORCE_CLKS_ON_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_FORCE_CLKS_OFF 1:1 /* -WEVF */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_FORCE_CLKS_OFF_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_FORCE_CLKS_OFF_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_XBASH 2:2 /* -WEVF */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_XBASH_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_XBASH_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_FAULT_SIM 3:3 /* -WEVF */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_FAULT_SIM_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_FAULT_SIM_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_STOP_SIM_PASS 4:4 /* -WEVF */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_STOP_SIM_PASS_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_STOP_SIM_PASS_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_STOP_HALT_CHECKING 5:5 /* -WEVF */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_STOP_HALT_CHECKING_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_STOP_HALT_CHECKING_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_CONTEXT_RESET_IS_COMING 6:6 /* -WEVF */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_CONTEXT_RESET_IS_COMING_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_TBCS_TRIGGERS_CONTEXT_RESET_IS_COMING_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE 0x0002c500 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE_MODE 1:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE_MODE_AUTO 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE_MODE_SLOW 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE_MODE_FORCE_ON 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE_MODE_FORCE_POWER 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE_REQ 4:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE_REQ_DONE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE_REQ_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_TBCS_PWR_MODE_REQ_SEND 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_RCCLASS 0x0002c900 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_RCCLASS_OVERRIDE 3:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_RCCLASS_OVERRIDE_DEFAULT 0x00000003 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS 0x0002c600 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RESTORE_WAIT 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RESTORE_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RESTORE_WAIT_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RESTART_WAIT 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RESTART_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RESTART_WAIT_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_FORCE_CLKS_ON 2:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_FORCE_CLKS_ON_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_FORCE_CLKS_ON_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SKIP 3:3 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SKIP_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SKIP_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_FC 4:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_FC_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_FC_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_PFS_STOP 5:5 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_PFS_STOP_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_PFS_STOP_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_HALT_ON_WFI 6:6 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_HALT_ON_WFI_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_HALT_ON_WFI_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_NACK_TEST 7:7 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_NACK_TEST_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_NACK_TEST_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_NACK_ASSIST 8:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_NACK_ASSIST_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_NACK_ASSIST_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ZERO_INIT 9:9 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ZERO_INIT_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ZERO_INIT_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ELPG 10:10 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ELPG_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ELPG_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RANDOM 11:11 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RANDOM_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RANDOM_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ELCG 12:12 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ELCG_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ELCG_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_PREEMPT 13:13 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_PREEMPT_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_PREEMPT_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ZCULL_DIRECT_CTXSW 14:14 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ZCULL_DIRECT_CTXSW_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_ZCULL_DIRECT_CTXSW_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_GFX_PREEMPT 15:15 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_GFX_PREEMPT_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_GFX_PREEMPT_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_NO_SAVE_RESTORE 16:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_NO_SAVE_RESTORE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_NO_SAVE_RESTORE_FALSE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW 17:17 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_MODE 20:18 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_MODE_SRR 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_MODE_SSRR 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_MODE_SSSRR 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_MODE_SSCSRR 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_MODE_SCSRR 0x00000004 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_MODE_SRRCR 0x00000005 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_MODE_SCSRRCR 0x00000006 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_SKIP_ALLOWED 21:21 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_SKIP_ALLOWED_FALSE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_SKIP_ALLOWED_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_RESUME_RESTORE 22:22 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_RESUME_RESTORE_FALSE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_SWDX_DIRECT_CTXSW_RESUME_RESTORE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_HALT_DURING_CTXSW 23:23 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_HALT_DURING_CTXSW_FALSE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_HALT_DURING_CTXSW_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_HOLDOFF_FREEZE_DEASSERTION 24:24 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_HOLDOFF_FREEZE_DEASSERTION_FALSE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_HOLDOFF_FREEZE_DEASSERTION_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RND 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RND_PASS 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_OPTIONS_RND_FAIL 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_PARAM 0x0002c700 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_DISABLE 0x0002ca00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_DISABLE_FIELD 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_DISABLE_FIELD_DEFAULT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_ADDRESS 0x0002cb00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_ADDRESS_FIELD 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_ADDRESS_FIELD_D 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_CMD 0x0002cc00 /* -W-4R */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_CMD_PERM 0:0 /* -W-VF */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_CMD_PERM_NONPERMANENT 0x00000000 /* -W--V */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_CMD_PERM_PERMANENT 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_CMD_CMD 5:4 /* -WEVF */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_CMD_CMD_NONE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_CMD_CMD_ALLOCATE 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_CMD_CMD_DEALLOCATE 0x00000002 /* -W--T */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_ID 0x0002cd00 /* R--4R */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_ID_FIELD 7:0 /* R-EVF */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_ID_FIELD_D 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_ID_NEW 28:28 /* R-EVF */ #define NV_CTXSW_FIRMWARE_TBCS_BUF_ID_NEW_D 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_TBCS_BLOCK_BIND 0x0002ce00 /* R--4R */ #define NV_CTXSW_FIRMWARE_TBCS_ELPG 0x0002cf00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_ELPG_GLOBAL_CLAMP_EN 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_ELPG_GLOBAL_CLAMP_EN_D 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_ELPG_DEEP_ELPG_PWR_EN 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_ELPG_DEEP_ELPG_PWR_EN_D 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_ELPG_TBCS_CONTROL 2:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_ELPG_TBCS_CONTROL_D 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_ELCG 0x0002d300 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_ELCG_CLAMP 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_ELCG_CLAMP_EN 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_ELCG_CLAMP_DIS 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_RANDOM 0x0002d000 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_RANDOM_VAL 31:0 /* RWXVF */ #define NV_CTXSW_FIRMWARE_TBCS_PRI_CONTROL 0x0002d400 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_PRI_CONTROL_HOLDOFF_EXTERNAL 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_PRI_CONTROL_HOLDOFF_EXTERNAL_EN 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_PRI_CONTROL_HOLDOFF_EXTERNAL_DIS 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_PIO 0x0002d100 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_RAM_SIZE 0x0002d200 /* R--4R */ #define NV_CTXSW_FIRMWARE_TBCS_ZCULL_CTXSW 0x0002d500 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_ZCULL_CTXSW_FB_MUX 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_ZCULL_CTXSW_FB_MUX_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TBCS_ZCULL_CTXSW_FB_MUX_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TBCS_SWDX_CTXSW 0x0002d600 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TBCS_SWDX_CTXSW_ADDR 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TBCS_SWDX_CTXSW_ADDR_I 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL 0x00030200 /* -W-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_PMU_SLAVE_ACK 0:0 /* -WEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_PMU_SLAVE_ACK_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_PMU_SLAVE_ACK_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_PMU_MASTER_REQ 1:1 /* -WEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_PMU_MASTER_REQ_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_PMU_MASTER_REQ_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_WFI_REQ 2:2 /* -WEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_WFI_REQ_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_WFI_REQ_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_HALT_REQ 3:3 /* -WEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_HALT_REQ_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_HALT_REQ_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_WFF_REQ 5:5 /* -WEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_WFF_REQ_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_WFF_REQ_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_WFF_PREEMPT 6:6 /* -WEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_WFF_PREEMPT_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_WFF_PREEMPT_ENABLED 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_GRAPHICS_PREEMPTION_CONTROL 9:8 /* -W-VF */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_GRAPHICS_PREEMPTION_CONTROL_WFI 0x00000000 /* -W--V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_GRAPHICS_PREEMPTION_CONTROL_GFXP 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_COMPUTE_PREEMPTION_CONTROL 13:12 /* -W-VF */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_COMPUTE_PREEMPTION_CONTROL_WFI 0x00000000 /* -W--V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_COMPUTE_PREEMPTION_CONTROL_CTA 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_CTXSW_INTERFACE_CTL_FE_COMPUTE_PREEMPTION_CONTROL_CILP 0x00000002 /* -W--V */ #define NV_CTXSW_FIRMWARE_CTXSW_FORCE_NONIDLE 0x00010900 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_FORCE_NONIDLE_OVERRIDE 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_FORCE_NONIDLE_OVERRIDE_ACTIVE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_FORCE_NONIDLE_OVERRIDE_INACTIVE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_IDLESTATE 0x00010800 /* R--4R */ #define NV_CTXSW_FIRMWARE_CTXSW_IDLESTATE_FALCON 0:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_IDLESTATE_FORCED 1:1 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_IDLESTATE_RC_LANES 2:2 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_IDLESTATE_PRIV_SEQUENCER 3:3 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_IDLESTATE_GPCCS 15:15 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0 0x00030000 /* R--4R */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_REQ 0:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_REQ_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_REQ_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_VLD 1:1 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_VLD_INVALID 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_VLD_VALID 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_ACK 2:2 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_ACK_NOACK 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_ACK_ACK 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_INT 3:3 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_INT_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CTXSW_INT_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_STALL_REQ 4:4 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_STALL_REQ_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_STALL_REQ_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_STALL_ACK 5:5 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_STALL_ACK_NOACK 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_STALL_ACK_ACK 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CONTEXT_PREEMPTED 6:6 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CONTEXT_PREEMPTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_CONTEXT_PREEMPTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_REQ 7:7 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_REQ_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_REQ_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_ACK 8:8 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_ACK_NOACK 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_SLAVE_INTERRUPT_ACK_ACK 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_REQ 9:9 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_REQ_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_REQ_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_ACK 10:10 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_ACK_NOACK 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_PMU_MASTER_INTERRUPT_ACK_ACK 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FIRMWARE_METHOD_INTERRUPT 11:11 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FIRMWARE_METHOD_INTERRUPT_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FIRMWARE_METHOD_INTERRUPT_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_UNIMPLEMENTED_METHOD_INTERRUPT 12:12 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_UNIMPLEMENTED_METHOD_INTERRUPT_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_UNIMPLEMENTED_METHOD_INTERRUPT_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_WFI_REQ 13:13 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_WFI_REQ_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_WFI_REQ_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_WFI_ACK 14:14 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_WFI_ACK_NOACK 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_WFI_ACK_ACK 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_HALT_REQ 15:15 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_HALT_REQ_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_HALT_REQ_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_HALT_ACK 16:16 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_HALT_ACK_NOACK 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_HALT_ACK_ACK 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_GR_INTR 17:17 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_GR_INTR_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_GR_INTR_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_DFD_INTR 18:18 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_DFD_INTR_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_DFD_INTR_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_INTERVAL_TIMER_INTR 19:19 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_INTERVAL_TIMER_INTR_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_FE_INTERVAL_TIMER_INTR_REQ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_RING_MANAGE_STATUS 23:23 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_RING_MANAGE_STATUS_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_RING_MANAGE_STATUS_SUCCESS 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_ABORT_CTXSW 24:24 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_ABORT_CTXSW_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_ABORT_CTXSW_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_NACK_RECEIVED 25:25 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_NACK_RECEIVED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_NACK_RECEIVED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_NACK_ACTION 26:26 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_NACK_ACTION_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_NACK_ACTION_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_DUT_FAULTED 27:27 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_DUT_FAULTED_FALSE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_TBCS_DUT_FAULTED_TRUE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_GFX_PREEMPTION_TYPE_ISSUED_BY_FE 29:28 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_GFX_PREEMPTION_TYPE_ISSUED_BY_FE_WFI 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_GFX_PREEMPTION_TYPE_ISSUED_BY_FE_GFXP 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_COMPUTE_PREEMPTION_TYPE_ISSUED_BY_FE 31:30 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_COMPUTE_PREEMPTION_TYPE_ISSUED_BY_FE_WFI 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_COMPUTE_PREEMPTION_TYPE_ISSUED_BY_FE_CTA 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_FE_0_COMPUTE_PREEMPTION_TYPE_ISSUED_BY_FE_CILP 0x00000002 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_GPC_0 0x00030100 /* R--4R */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_GPC_0_HWW 0:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_GPC_0_CTXSW_HALT 1:1 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_GPC_0_STOP_SM 2:2 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1 0x00010000 /* R--4R */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_CONSTANT_0 0:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_LOCAL_PRIV_ERROR 1:1 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_RC_LANES 2:2 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_RC_LANES_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_RC_LANES_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_CONTEXT_RESET 3:3 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_CONTEXT_RESET_ACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_CONTEXT_RESET_DISABLED 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL 4:4 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_BUSY 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_IDLE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_SEQUENCER 5:5 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_SEQUENCER_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_SEQUENCER_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_READ 6:6 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_READ_DONE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_READ_NOT_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_WRACK 7:7 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_WRACK_DONE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_WRACK_NOT_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_COMP0 8:8 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_COMP0_DONE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_COMP0_NOT_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_COMP1 9:9 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_COMP1_DONE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_COMP1_NOT_DONE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_DFD_TRIGGER 10:10 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_DFD_TRIGGER_ACTIVE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_DFD_TRIGGER_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_WATCHDOG_TRIGGER 11:11 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_WATCHDOG_TRIGGER_ACTIVE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_WATCHDOG_TRIGGER_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_ARB_BUSY 12:12 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_ARB_NACK 13:13 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_ARB_HALTED 14:14 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_ARB_FLUSH_WHEN_BUSY 15:15 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_CTXSW_CHECKSUM_MISMATCH 16:16 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL 28:28 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_VIOLATION 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_ERROR 29:29 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_DECODE_TRAP 30:30 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_DECODE_TRAP_WRITE_DROPPED 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_DECODE_TRAP_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_UCODE_TRAP 31:31 /* R--VF */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_UCODE_TRAP_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_CTXSW_STATUS_1_PRIV_UCODE_TRAP_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG(i) (0x00010100+(i)*0x4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG__SIZE_1 8 /* */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL0_BIT 4:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL0_BIT_V0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL0_STATUS_REG 5:5 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_0 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_1 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL1_BIT 12:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL1_BIT_V0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL1_STATUS_REG 13:13 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_0 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_1 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_COMBINATION 16:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_COMBINATION_OR 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_COMBINATION_AND 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SENSE 18:17 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SENSE_RISING_EDGE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SENSE_FALLING_EDGE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SENSE_LEVEL_1 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_CFG_SENSE_LEVEL_0 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG(i) (0x00030500+(i)*0x4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG__SIZE_1 19 /* */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL0_BIT 4:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL0_BIT_V0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL0_STATUS_REG 5:5 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_0 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_1 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL1_BIT 12:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL1_BIT_V0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL1_STATUS_REG 13:13 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_0 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_1 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_COMBINATION 16:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_COMBINATION_OR 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_COMBINATION_AND 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SENSE 18:17 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SENSE_RISING_EDGE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SENSE_FALLING_EDGE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SENSE_LEVEL_1 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CFG_SENSE_LEVEL_0 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS 0x00030600 /* R--4R */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_CTXSW_INTR 15:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_CTXSW_INTR_NONE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_CTXSW_INTR0 0:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_CTXSW_INTR0_NOT_ASSERTED 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_CTXSW_INTR0_ASSERTED 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_FAULT_DURING_CTXSW 16:16 /* R--VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_FAULT_DURING_CTXSW_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_FAULT_DURING_CTXSW_ACTIVE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD 17:17 /* R--VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD_ACTIVE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD 18:18 /* R--VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD_ACTIVE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_WATCHDOG 19:19 /* R--VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_WATCHDOG_ACTIVE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_WATCHDOG_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_FLUSH_WHEN_BUSY 20:20 /* R--VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_FLUSH_WHEN_BUSY_ACTIVE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_FLUSH_WHEN_BUSY_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_ECC_CORRECTED 21:21 /* R--VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_ECC_CORRECTED_ACTIVE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_ECC_CORRECTED_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_ECC_UNCORRECTED 22:22 /* R--VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_ECC_UNCORRECTED_ACTIVE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_STATUS_ECC_UNCORRECTED_INACTIVE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET 0x00030700 /* -W-4R */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR0 0:0 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR0_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR1 1:1 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR1_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR2 2:2 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR2_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR2_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR3 3:3 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR3_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR3_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR4 4:4 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR4_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR4_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR5 5:5 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR5_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR5_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR6 6:6 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR6_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR6_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR7 7:7 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR7_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR7_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR8 8:8 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR8_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR8_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR9 9:9 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR9_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR9_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR10 10:10 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR10_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR10_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR11 11:11 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR11_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR11_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR12 12:12 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR12_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR12_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR13 13:13 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR13_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR13_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR14 14:14 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR14_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR14_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR15 15:15 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR15_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_CTXSW_INTR15_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_FAULT_DURING_CTXSW 16:16 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_FAULT_DURING_CTXSW_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_FAULT_DURING_CTXSW_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_UMIMP_FIRMWARE_METHOD 17:17 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_UMIMP_FIRMWARE_METHOD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_UMIMP_FIRMWARE_METHOD_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_UMIMP_ILLEGAL_METHOD 18:18 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_UMIMP_ILLEGAL_METHOD_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_UMIMP_ILLEGAL_METHOD_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_WATCHDOG 19:19 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_WATCHDOG_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_WATCHDOG_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_FLUSH_WHEN_BUSY 20:20 /* -W-VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_FLUSH_WHEN_BUSY_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_SET_FLUSH_WHEN_BUSY_IGNORE 0x00000000 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR 0x00030800 /* -W-4R */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR0 0:0 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR0_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR0_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR1 1:1 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR1_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR1_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR2 2:2 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR2_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR2_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR3 3:3 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR3_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR3_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR4 4:4 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR4_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR4_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR5 5:5 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR5_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR5_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR6 6:6 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR6_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR6_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR7 7:7 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR7_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR7_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR8 8:8 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR8_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR8_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR9 9:9 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR9_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR9_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR10 10:10 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR10_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR10_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR11 11:11 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR11_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR11_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR12 12:12 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR12_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR12_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR13 13:13 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR13_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR13_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR14 14:14 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR14_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR14_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR15 15:15 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR15_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_CTXSW_INTR15_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_FAULT_DURING_CTXSW 16:16 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_FAULT_DURING_CTXSW_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_FAULT_DURING_CTXSW_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_UMIMP_FIRMWARE_METHOD 17:17 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_UMIMP_FIRMWARE_METHOD_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_UMIMP_FIRMWARE_METHOD_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_UMIMP_ILLEGAL_METHOD 18:18 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_UMIMP_ILLEGAL_METHOD_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_UMIMP_ILLEGAL_METHOD_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_WATCHDOG 19:19 /* -WEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_WATCHDOG_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_WATCHDOG_IGNORE 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_FLUSH_WHEN_BUSY 20:20 /* -W-VF */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_FLUSH_WHEN_BUSY_CLEAR 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_CLEAR_FLUSH_WHEN_BUSY_IGNORE 0x00000000 /* -W--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE 0x00030900 /* RW-4R */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR0 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR0_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR0_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR1 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR1_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR1_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR2 2:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR2_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR2_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR3 3:3 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR3_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR3_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR4 4:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR4_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR4_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR5 5:5 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR5_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR5_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR6 6:6 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR6_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR6_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR7 7:7 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR7_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR7_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR8 8:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR8_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR8_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR9 9:9 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR9_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR9_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR10 10:10 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR10_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR10_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR11 11:11 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR11_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR11_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR12 12:12 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR12_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR12_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR13 13:13 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR13_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR13_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR14 14:14 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR14_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR14_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR15 15:15 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR15_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_CTXSW_INTR15_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_FAULT_DURING_CTXSW 16:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_FAULT_DURING_CTXSW_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD 17:17 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD 18:18 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_WATCHDOG 19:19 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_WATCHDOG_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_WATCHDOG_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_FLUSH_WHEN_BUSY 20:20 /* RWEVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_FLUSH_WHEN_BUSY_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_FLUSH_WHEN_BUSY_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_ECC_CORRECTED 21:21 /* R-EVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_ECC_CORRECTED_ENABLE 0x00000001 /* R-E-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_ECC_CORRECTED_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_ECC_UNCORRECTED 22:22 /* R-EVF */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_ECC_UNCORRECTED_ENABLE 0x00000001 /* R-E-V */ #define NV_CTXSW_FIRMWARE_HOST_INT_ENABLE_ECC_UNCORRECTED_DISABLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_WATCHDOG 0x00010c00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_WATCHDOG_COUNT 29:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_WATCHDOG_COUNT_V 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_WATCHDOG_ENABLE 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_WATCHDOG_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_WATCHDOG_ENABLE_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK 0x00010d00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_0 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_0_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_0_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_1 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_1_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_1_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_2 2:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_2_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_2_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_3 3:3 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_3_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_3_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_4 4:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_4_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_4_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_5 5:5 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_5_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_5_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_6 6:6 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_6_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_6_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_7 7:7 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_7_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_INT_ACK_7_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL 0x00018500 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_SYS_HALT 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_SYS_HALT_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_SYS_HALT_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_SYS_ENGINE_RESET 4:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_SYS_ENGINE_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_SYS_CONTEXT_RESET 8:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_GPC_HALT 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_GPC_HALT_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_GPC_HALT_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_HALT_SEQUENCER 2:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_HALT_SEQUENCER_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_HALT_SEQUENCER_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_GPC_ENGINE_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_ZCULL_RT_RESET 11:11 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_ZCULL_RT_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_ZCULL_RT_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ENGINE_RESET_CTL 0x00018400 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ENGINE_RESET_CTL_GPC_ENGINE_RESET 0:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_ENGINE_RESET_CTL_GPC_ENGINE_RESET_ENABLED 0x00000000 /* RWB-V */ #define NV_CTXSW_FIRMWARE_ENGINE_RESET_CTL_GPC_ENGINE_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_CTL_SIGS 0x00022300 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_CTL_SIGS_CTXSW_FREEZE 4:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_CTL_SIGS_CTXSW_FREEZE_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_CTL_SIGS_CTXSW_FREEZE_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTX_STATE_STORE_MAJOR_REV_ID 0x00018300 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTX_STATE_STORE_MAJOR_REV_ID_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTX_STATE_STORE_MAJOR_REV_ID_V_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTX_STATE_STORE_MINOR_REV_ID 0x00018400 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTX_STATE_STORE_MINOR_REV_ID_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTX_STATE_STORE_MINOR_REV_ID_V_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_EMUCRC_DATA 0x00018c00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_EMUCRC_DATA_V 31:0 /* RW-VF */ #define NV_CTXSW_FIRMWARE_EMUCRC_CFG 0x00018d00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_EMUCRC_CFG_V 31:0 /* RW-VF */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX(i) (0x00020000+(i)*0x100) /* RW-4A */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_NONE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_PASS 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_FAIL 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_BIND_POINTER_PASS 0x00000010 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_BIND_POINTER_FAIL 0x00000021 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_MAGIC 0x12345678 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_WAIT_FOR_MODS 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_STOP_WAIT_FOR_MODS 0x0000000e /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SYNC_POINT_1 0x00000005 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SYNC_POINT_2 0x00000006 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SYNC_POINT_3 0x00000007 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_INIT_FAILED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_INVALID_METHOD 0x00000009 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_METHOD_QUEUE_OVERFLOW 0x00000010 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_INVALID_FIRMWARE_METHOD_PARAMETER 0x00000011 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SIDEBAND_METHOD_QUEUE_OVERFLOW 0x00000012 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_FIRMWARE_METHOD_QUEUE_OVERFLOW 0x00000013 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_BECS_RC_NON_ZERO 0x00000014 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_BAD_CTXSW_IMAGE 0x00000015 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS 0x00000016 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SECURE_FAIL_GPCCS 0x00000017 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS_AND_GPCCS 0x00000018 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_GFXP_WITH_VPR_CONTEXT 0x00000019 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_PRI_SEQ_ERROR 0x00000020 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_CTXSW_CHECKSUM_MISMATCH 0x00000021 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_FALCON_CSB_ERROR 0x00000022 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_PATCH_BUFFER_ACCESS_VIOLATION 0x00000023 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_FALCON_STACK_CANARY_CHECK_FAILED 0x00000024 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_1_FAILED 0x00000025 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_2_FAILED 0x00000026 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_INDEX_OOB 0x00000027 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_POINTER_OVERFLOW 0x00000028 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_OFFSET_OVERFLOW 0x00000029 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL 0x00000030 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_INVALID_ARBITER_COMMANDS 0x00000031 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_NUM_GPC_MISMATCH 0x00000032 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_NUM_TPC_MISMATCH 0x00000033 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_GFXP_IN_SMC_MODE 0x00000034 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_RESTORE_SMC_IN_LEGACY 0x00000035 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_RESTORE_LEGACY_IN_SMC 0x00000036 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SMC_LTS_MASK_INDEX_OUT_OF_BOUNDS 0x00000037 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SYS_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000038 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_GPC_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000039 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SYS_PRI_IMAGE_SIZE_MISMATCH 0x00000040 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_GPC_PRI_IMAGE_SIZE_MISMATCH 0x00000041 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_MAX_LTS_PER_LTC 0x00000042 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_NUM_PPC_MISMATCH 0x00000043 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_TRIVIAL_ACK_WITHOUT_NOCHSW 0x00000044 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_SECOND_RESTORE_WITH_NOCHSW 0x00000045 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_INVALID_PRIV_ACCESS_MAP_CONFIG 0x00000046 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_LTC_COUNT_OVERFLOW 0x00000047 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_REV_ID_CHECK_FAILED 0x00000048 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_CHIP_ID_CHECK_FAILED 0x00000049 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_ILLEGAL_FALCON_LEVEL 0x00000050 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_PRIV_SEC_NOT_ENABLED 0x00000051 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_PRIV_ACCESS_VIOLATION 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_VERIF_VIOLATION 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_OOB 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_NOT_IN_WHITELIST 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_ALLOW_NONE 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_KILL 0x00000004 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_OOB 0x00000005 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_NOT_IN_WHITELIST 0x00000006 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_FUNCTION_TRACING_MAILBOX_SET(i) (0x00021200+(i)*0x100) /* -W-4A */ #define NV_CTXSW_FIRMWARE_CTXSW_FUNCTION_TRACING_MAILBOX_SET__SIZE_1 6 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_FUNCTION_TRACING_MAILBOX_SET_VALUE 31:0 /* -W-VF */ #define NV_CTXSW_FIRMWARE_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR(i) (0x00021800+(i)*0x100) /* -W-4A */ #define NV_CTXSW_FIRMWARE_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR__SIZE_1 6 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR_VALUE 31:0 /* -W-VF */ #define NV_CTXSW_FIRMWARE_CTXSW_FUNCTION_TRACING_MAILBOX(i) (0x00023000+(i)*0x100) /* RW-4A */ #define NV_CTXSW_FIRMWARE_CTXSW_FUNCTION_TRACING_MAILBOX__SIZE_1 6 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_FUNCTION_TRACING_MAILBOX_VALUE 31:0 /* -W-VF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK 0x00021e00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_LOCAL_FALCON_ENABLED 0x00080040 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1(i) (0x00023600+(i)*0x100) /* RW-4A */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1__SIZE_1 3 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_VALUE 31:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP1__PRIV_LEVEL_MASK 0x00021e00 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK 0x00021f00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0x0000000c /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2(i) (0x00023900+(i)*0x100) /* RW-4A */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2__SIZE_1 3 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_VALUE 31:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP2__PRIV_LEVEL_MASK 0x00021f00 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK 0x00023f00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3(i) (0x00023c00+(i)*0x100) /* RW-4A */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3__SIZE_1 3 /* */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_VALUE 31:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_CTXSW_FIRMWARE_CTXSW_SECURE_SCRATCH_GROUP3__PRIV_LEVEL_MASK 0x00023f00 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK 0x00010a00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_SOURCE_FALCON_FECS_GPCCS_ENABLED 0x00080174 /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_CTXSW_FIRMWARE_COMP_FS_CONFIG(i) (0x00010300+(i)*0x4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_COMP_FS_CONFIG__SIZE_1 2 /* */ #define NV_CTXSW_FIRMWARE_COMP_FS_CONFIG__PRIV_LEVEL_MASK 0x00010a00 /* */ #define NV_CTXSW_FIRMWARE_COMP_FS_CONFIG_EN 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_FS_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_ACTIVE_CONFIG(i) (0x00010400+(i)*0x4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_COMP_ACTIVE_CONFIG__SIZE_1 2 /* */ #define NV_CTXSW_FIRMWARE_COMP_ACTIVE_CONFIG__PRIV_LEVEL_MASK 0x00010a00 /* */ #define NV_CTXSW_FIRMWARE_COMP_ACTIVE_CONFIG_EN 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_ACTIVE_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_FINISHED(i) (0x00010500+(i)*0x4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_COMP_FINISHED__SIZE_1 2 /* */ #define NV_CTXSW_FIRMWARE_COMP_FINISHED__PRIV_LEVEL_MASK 0x00010a00 /* */ #define NV_CTXSW_FIRMWARE_COMP_FINISHED_BITS 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_COMP_FINISHED_BITS_RESET 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE(i) (0x00010600+(i)*0x100) /* -W-4A */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE__SIZE_1 2 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE__PRIV_LEVEL_MASK 0x00010a00 /* */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT0 0:0 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT0_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT0_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT1 1:1 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT1_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT1_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT2 2:2 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT2_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT2_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT3 3:3 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT3_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT3_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT4 4:4 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT4_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT4_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT5 5:5 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT5_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT5_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT6 6:6 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT6_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT6_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT7 7:7 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT7_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT7_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT8 8:8 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT8_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT8_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT9 9:9 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT9_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT9_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT10 10:10 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT10_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT10_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT11 11:11 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT11_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT11_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT12 12:12 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT12_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT12_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT13 13:13 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT13_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT13_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT14 14:14 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT14_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT14_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT15 15:15 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT15_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT15_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT16 16:16 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT16_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT16_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT17 17:17 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT17_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT17_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT18 18:18 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT18_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT18_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT19 19:19 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT19_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT19_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT20 20:20 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT20_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT20_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT21 21:21 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT21_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT21_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT22 22:22 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT22_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT22_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT23 23:23 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT23_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT23_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT24 24:24 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT24_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT24_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT25 25:25 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT25_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT25_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT26 26:26 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT26_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT26_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT27 27:27 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT27_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT27_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT28 28:28 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT28_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT28_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT29 29:29 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT29_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT29_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT30 30:30 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT30_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT30_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT31 31:31 /* -WEVF */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT31_SET 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_COMP_SET_DONE_BIT31_I 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_POWER_GATE_CTL 0x00022b00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_CTXSW_POWER_GATE_CTL_ENABLE_POWER 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_POWER_GATE_CTL_ENABLE_POWER_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_POWER_GATE_CTL_ENABLE_POWER_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CTXSW_POWER_GATE_CTL_ENABLE_FALCON_CLK 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CTXSW_POWER_GATE_CTL_ENABLE_FALCON_CLK_ON 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CTXSW_POWER_GATE_CTL_ENABLE_FALCON_CLK_OFF 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FS 0x00018100 /* R--4R */ #define NV_CTXSW_FIRMWARE_FS_NUM_AVAILABLE_GPCS 4:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_FS_NUM_AVAILABLE_FBPS 20:16 /* R--VF */ #define NV_CTXSW_FIRMWARE_FS_NUM_AVAILABLE_LTCS 28:24 /* R--VF */ #define NV_CTXSW_FIRMWARE_FS_GPC 0x00018200 /* R--4R */ #define NV_CTXSW_FIRMWARE_FS_GPC_NUM_AVAILABLE_TPCS 4:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 /* R--VF */ #define NV_CTXSW_FIRMWARE_FS_GPC_NUM_AVAILABLE_ROPS 25:21 /* R--VF */ #define NV_CTXSW_FIRMWARE_GPC_INFO 0x00018600 /* R--4R */ #define NV_CTXSW_FIRMWARE_GPC_INFO_GLOBAL_GPC_ID 4:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_GPC_INFO_SMC_LOCAL_GPC_ID 12:8 /* R--VF */ #define NV_CTXSW_FIRMWARE_GPC_INFO_UGPU_ID 13:13 /* R--VF */ #define NV_CTXSW_FIRMWARE_SMC_CONFIGURATION 0x00018700 /* R--4R */ #define NV_CTXSW_FIRMWARE_SMC_CONFIGURATION_MODE 0:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_SMC_CONFIGURATION_MODE_LEGACY_MODE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_SMC_CONFIGURATION_MODE_SMC_MODE 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_SMC_CONFIGURATION_SMC_ENGINE_ID 20:16 /* R--VF */ #define NV_CTXSW_FIRMWARE_CFG_FALCON 0x00018800 /* R--4R */ #define NV_CTXSW_FIRMWARE_CFG_FALCON_IMEM_SZ 7:0 /* R-XVF */ #define NV_CTXSW_FIRMWARE_CFG_FALCON_IMEM_SZ_4K 0x00000010 /* R---V */ #define NV_CTXSW_FIRMWARE_CFG_FALCON_IMEM_SZ_6K 0x00000018 /* R---V */ #define NV_CTXSW_FIRMWARE_CFG_FALCON_IMEM_SZ_8K 0x00000020 /* R---V */ #define NV_CTXSW_FIRMWARE_CFG_FALCON_IMEM_SZ_12K 0x00000030 /* R---V */ #define NV_CTXSW_FIRMWARE_CFG_FALCON_DMEM_SZ 15:8 /* R-XVF */ #define NV_CTXSW_FIRMWARE_CFG_FALCON_DMEM_SZ_2K 0x00000008 /* R---V */ #define NV_CTXSW_FIRMWARE_CFG_FALCON_DMEM_SZ_4K 0x00000010 /* R---V */ #define NV_CTXSW_FIRMWARE_CFG_FALCON_DMEM_SZ_8K 0x00000020 /* R---V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS 0x00033f00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC0 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC0_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC0_BUSY 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC1 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC1_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC1_BUSY 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC2 2:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC2_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC2_BUSY 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC3 3:3 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC3_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC3_BUSY 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC4 4:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC4_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC4_BUSY 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC5 5:5 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC5_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC5_BUSY 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC6 6:6 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC6_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC6_BUSY 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC7 7:7 /* RWEVF */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC7_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_TPCCS_STATUS_TPC7_BUSY 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANES 0x00022000 /* R--4R */ #define NV_CTXSW_FIRMWARE_RC_LANES_NUM_CHAINS 5:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN 0x00022100 /* RW-4R */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE0 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE0_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE0_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE1 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE1_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE1_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE2 2:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE2_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE2_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE3 3:3 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE3_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE3_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE4 4:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE4_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE4_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE5 5:5 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE5_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE5_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE6 6:6 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE6_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE6_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE7 7:7 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE7_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE7_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE8 8:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE8_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE8_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE9 9:9 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE9_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE9_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE10 10:10 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE10_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE10_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE11 11:11 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE11_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE11_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE12 12:12 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE12_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE12_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE13 13:13 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE13_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE13_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE14 14:14 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE14_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE14_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE15 15:15 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE15_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE15_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE16 16:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE16_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE16_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE17 17:17 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE17_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RUN_LANE17_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS 0x00022200 /* R--4R */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE0 0:0 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE0_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE0_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE1 1:1 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE1_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE1_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE2 2:2 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE2_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE2_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE3 3:3 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE3_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE3_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE4 4:4 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE4_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE4_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE5 5:5 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE5_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE5_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE6 6:6 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE6_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE6_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE7 7:7 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE7_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE7_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE8 8:8 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE8_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE8_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE9 9:9 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE9_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE9_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE10 10:10 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE10_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE10_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE11 11:11 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE11_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE11_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE12 12:12 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE12_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE12_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE13 13:13 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE13_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE13_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE14 14:14 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE14_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE14_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE15 15:15 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE15_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE15_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE16 16:16 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE16_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE16_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE17 17:17 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE17_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_STATUS_LANE17_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_SCRUB 0x00019000 /* R--4R */ #define NV_CTXSW_FIRMWARE_RC_LANE_SCRUB_STATUS 31:0 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_SCRUB_STATUS_INIT 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_SCRUB_STATUS_CLEAN 0xffffffff /* R---V */ #define NV_CTXSW_FIRMWARE_SIMULATION_OPTIONS 0x00019100 /* R--4R */ #define NV_CTXSW_FIRMWARE_SIMULATION_OPTIONS_MODEL 1:0 /* R-EVF */ #define NV_CTXSW_FIRMWARE_SIMULATION_OPTIONS_MODEL_GATES 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_SIMULATION_OPTIONS_MODEL_RTL 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_SIMULATION_OPTIONS_MODEL_FMODEL 0x00000002 /* R---V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS 0x00019e00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_PENDING 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM 1:1 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_PENDING 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM 4:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_PENDING 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM 5:5 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_PENDING 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_RESET 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_RESET_TASK 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_STATUS_RESET_INIT 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CORRECTED_ERR_COUNT 0x00019f00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_UNCORRECTED_ERR_COUNT 0x0001a000 /* RW-4R */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_ADDRESS 0x0001a100 /* R--4R */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_ADDRESS_INDEX 22:0 /* R-XVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_ADDRESS_ROW_ADDRESS 19:0 /* R-XVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_ADDRESS_SOURCE_RAM 22:20 /* R-XVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_IMEM 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_DMEM 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK 0x0001a200 /* RW-4R */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL 0x0001a300 /* RW-4R */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL__PRIV_LEVEL_MASK 0x0001a200 /* */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR 0:0 /* -WEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x00000000 /* -W--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR 1:1 /* -WEVF */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x00000000 /* -W--V */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO 0x0001a400 /* R--4R */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_ADDRESS 25:0 /* R-EVF */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_ADDRESS_V 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_TRANSACTION_TYPE 30:29 /* R-EVF */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_TRANSACTION_TYPE_INVALID 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_TRANSACTION_TYPE_READ 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_ACK 0x00000002 /* R---V */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_NO_ACK 0x00000003 /* R---V */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_SOURCE 31:31 /* R-EVF */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_SOURCE_PRI_SEQ 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_INFO_SOURCE_FALCON_CSB 0x00000001 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_CODE 0x0001a500 /* R--4R */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_CODE_VALUE 31:0 /* R-EVF */ #define NV_CTXSW_FIRMWARE_PRI_ERROR_CODE_VALUE_V 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK(i) (0x00025400+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_FUSE0 0x000fffff /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_IFF_GPCCS_FECS_GSP_SEC2_FUSE1 0x0008007c /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL(i) (0x00024100+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL_COMPRESSION 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL_COMPRESSION_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL_COMPRESSION_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL_BLOAT_BUDGET 9:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL_BLOAT_BUDGET_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL_COMPRESSION_SETTINGS 27:10 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CONTROL_COMPRESSION_SETTINGS__0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVE_OFFSET(i) (0x00024200+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVE_OFFSET__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVE_OFFSET__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVE_OFFSET_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_OFFSET(i) (0x00024300+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_OFFSET__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_OFFSET__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_OFFSET_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CURRENT_OFFSET(i) (0x00024b00+(i)*4) /* R--4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CURRENT_OFFSET__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CURRENT_OFFSET_V 31:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CURRENT_OFFSET_V_0 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CURRENT_SUBOFFSET(i) (0x00024c00+(i)*4) /* R--4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CURRENT_SUBOFFSET__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CURRENT_SUBOFFSET_V 5:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CURRENT_SUBOFFSET_V_0 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_SIZE(i) (0x00024400+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_SIZE__SIZE_1 16 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_SIZE__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_SIZE_V 23:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_SIZE_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_PREFETCH_OFFSET(i) (0x00024500+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_PREFETCH_OFFSET__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_PREFETCH_OFFSET__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_PREFETCH_OFFSET_CTL_EN 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_PREFETCH_OFFSET_CTL_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_PREFETCH_OFFSET_CTL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_PREFETCH_OFFSET_V 13:7 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_PREFETCH_OFFSET_V_10 0x0000000a /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVED_WORDS(i) (0x00024d00+(i)*4) /* R--4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVED_WORDS__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVED_WORDS__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVED_WORDS_V 23:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVED_WORDS_V_0 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_WORDS(i) (0x00024e00+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_WORDS__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_WORDS__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_WORDS_V 23:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_RESTORE_WORDS_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_DATA(i) (0x00024600+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_DATA__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_DATA__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_DATA_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_DATA_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_LOC(i) (0x00024700+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_LOC__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_LOC__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_LOC_RAMID 9:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_LOC_RAMID_V 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_LOC_OFFSET 31:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_LOC_OFFSET_V 0x0000000f /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG(i) (0x00024800+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG_DELAY 6:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG_DELAY_V 0x00000041 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG_CREDITS 21:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG_CREDITS_V 0x0000003f /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG_AUTOSEEK 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG_AUTOSEEK_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_CFG_AUTOSEEK_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_RCCLASS(i) (0x00024f00+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_RCCLASS__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_RCCLASS__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_RCCLASS_V 3:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_RCCLASS_V_3 0x00000003 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_RCCLASS_V_WFI 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_RCCLASS_V_GFXP 0x00000004 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS(i) (0x00024900+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD 4:0 /* RW-VF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_IDLE 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_SEEK 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_DISCOVER_LENGTH 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_SAVE 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_RESTORE 0x00000004 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_LOAD 0x00000005 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_READ_POP 0x00000006 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_WRITE_PUSH 0x00000007 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_ENABLE 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_DISABLE 0x00000009 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_ENABLE 0x0000000a /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_DISABLE 0x0000000b /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_ENABLE 0x0000000c /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_DISABLE 0x0000000d /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_OVERRIDE 0x0000000e /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_FLUSH 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_LAST_CMD_SUSPEND 0x00000010 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_CURRENT 9:8 /* R--VF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_CURRENT_IDLE 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_STATUS_CURRENT_BUSY 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC(i) (0x00024a00+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD 4:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_SEEK 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_DISCOVER_LENGTH 0x00000002 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_SAVE 0x00000003 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_RESTORE 0x00000004 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_LOAD 0x00000005 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_READ_POP 0x00000006 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_WRITE_PUSH 0x00000007 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_RAMID_ENABLE 0x00000008 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_RAMID_DISABLE 0x00000009 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_CLASS_ENABLE 0x0000000a /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_CLASS_DISABLE 0x0000000b /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_CHAIN_ENABLE 0x0000000c /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_CHAIN_DISABLE 0x0000000d /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_CLASS_OVERRIDE 0x0000000e /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_FLUSH 0x0000000f /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_SUSPEND 0x00000010 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_CMD_EXEC_CMD_SCRUB 0x00000011 /* -W--T */ #define NV_CTXSW_FIRMWARE_RC_LANE_COMPUTED_CHECKSUM(i) (0x00025100+(i)*4) /* R-E4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_COMPUTED_CHECKSUM__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_COMPUTED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVED_CHECKSUM(i) (0x00025200+(i)*4) /* R-E4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVED_CHECKSUM__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CHECKSUM(i) (0x00025300+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_RC_LANE_CHECKSUM__SIZE_1 18 /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CHECKSUM__PRIV_LEVEL_MASK NV_CTXSW_FIRMWARE_RC_LANE_CMD_PRIV_LEVEL_MASK /* */ #define NV_CTXSW_FIRMWARE_RC_LANE_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CHECKSUM_CTRL_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CHECKSUM_CTRL_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_CTXSW_FIRMWARE_RC_LANE_CHECKSUM_STATUS_MATCH 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_RC_LANE_CHECKSUM_STATUS_MISMATCH 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK 0x0001d800 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000fffff /* RWB-V */ #define NV_CTXSW_FIRMWARE_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_JTAG_IFF_SEC2_ENABLED_FUSE1 0x00080144 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_SAVE_OFFSET 0x0001c000 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_SAVE_OFFSET__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_SAVE_OFFSET_V 31:0 /* RW-VF */ #define NV_CTXSW_FIRMWARE_PVS_SAVE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_RESTORE_OFFSET 0x0001c100 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_RESTORE_OFFSET_V 31:0 /* RW-VF */ #define NV_CTXSW_FIRMWARE_PVS_RESTORE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_SAVE_COUNT 0x0001d200 /* R--4R */ #define NV_CTXSW_FIRMWARE_PVS_SAVE_COUNT_V 15:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_PVS_SAVE_COUNT_V_0 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_PVS_RESTORE_COUNT 0x0001d300 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_RESTORE_COUNT__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_RESTORE_COUNT_V 15:0 /* RW-VF */ #define NV_CTXSW_FIRMWARE_PVS_RESTORE_COUNT_V_0 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_CURRENT_OFFSET 0x0001c200 /* R--4R */ #define NV_CTXSW_FIRMWARE_PVS_CURRENT_OFFSET_V 31:0 /* R-XVF */ #define NV_CTXSW_FIRMWARE_PVS_CURRENT_SUBOFFSET 0x0001c300 /* R--4R */ #define NV_CTXSW_FIRMWARE_PVS_CURRENT_SUBOFFSET_V 5:0 /* R-XVF */ #define NV_CTXSW_FIRMWARE_PVS_REGISTER_BASE_ADDR 0x0001c400 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_REGISTER_BASE_ADDR_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_REGISTER_BASE_ADDR 0x0001c900 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PV_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PV_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_REGISTER_BASE_ADDR_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_ST_CONSTANT 0x0001d100 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_ST_CONSTANT__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_ST_CONSTANT_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_ST_CONSTANT_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_MODE 0x0001c500 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_MODE__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_MODE_FIFO_FREE_ENTRIES 4:0 /* R-EVF */ #define NV_CTXSW_FIRMWARE_PVS_MODE_FIFO_FREE_ENTRIES_IV 0x00000010 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_FIFO_TOTAL_ENTRIES 12:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_MODE_FIFO_TOTAL_ENTRIES_IV 0x00000010 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_DIRECTION 16:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_MODE_DIRECTION_SAVE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_DIRECTION_RESTORE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_START 17:17 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_MODE_START_V 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_START_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_PVS_MODE_FINISH 18:18 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_MODE_FINISH_V 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_FINISH_T 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_PVS_MODE_NO_ADDR_INC 19:19 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_MODE_NO_ADDR_INC_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_NO_ADDR_INC_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_PRIV_LEVEL 29:28 /* R-EVF */ #define NV_CTXSW_FIRMWARE_PVS_MODE_PRIV_LEVEL_NONE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_LOWER_PRIV_LEVEL 30:30 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_MODE_LOWER_PRIV_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_MODE_LOWER_PRIV_LEVEL_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_PREFETCH_CTL 0x0001d000 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_PREFETCH_CTL__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_PREFETCH_CTL_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_PREFETCH_CTL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_PREFETCH_CTL_OFFSET_10 0x0000000a /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_INDEX_INCREMENT 0x0001c600 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_INDEX_INCREMENT__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_INDEX_INCREMENT_V 15:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_INDEX_INCREMENT_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_INDEX_MASK 0x0001c700 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_INDEX_MASK__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_INDEX_MASK_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_INDEX_MASK_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH 0x0001c800 /* -W-4R */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_USE_BASE_ADDR 0:0 /* -WXVF */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_USE_INDEXER 1:1 /* -WXVF */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_ADDR 25:2 /* -WXVF */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_REGISTER_COUNT 30:26 /* -WXVF */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_SPECIAL 31:31 /* -WXVF */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_SPECIAL_DATA 25:0 /* -WXVF */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_SPECIAL_COUNT 11:0 /* -WXVF */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_SPECIAL_CMD 30:26 /* -WXVF */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_SPECIAL_CMD_NOP 0x00000000 /* -W--V */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_SPECIAL_CMD_WAIT 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_SPECIAL_CMD_STORE_CONSTANT 0x00000002 /* -W--V */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_SPECIAL_CMD_SKIP_DATA 0x00000003 /* -W--V */ #define NV_CTXSW_FIRMWARE_PVS_FIFO_PUSH_SPECIAL_CMD_SET_REG_COUNT 0x00000004 /* -W--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ 0x0001ca00 /* RWE4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_USE_BASE_ADDR_NOT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_ADDR 25:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_ADDR_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_LOWER_PRIV_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_LOWER_PRIV_LEVEL_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_TRANS_STATUS 28:27 /* R-EVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_TRANS_STATUS_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_TRANS_STATUS_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_TRANS_STATUS_DONE 0x00000002 /* R---V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_TRANS_TYPE 30:29 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_TRANS_TYPE_READ 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_TRANS_TYPE_UNDEF 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_TRANS_TYPE_WRITE 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_TRANS_TYPE_WRITE_ACK 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_CMD 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_CMD_NONE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_CMD_GO 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A 0x0001cd00 /* RWE4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_USE_BASE_ADDR_NOT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_ADDR 25:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_ADDR_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_TRANS_STATUS 28:27 /* R-EVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_TRANS_STATUS_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_TRANS_STATUS_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_TRANS_STATUS_DONE 0x00000002 /* R---V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_TRANS_TYPE 30:29 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_TRANS_TYPE_READ 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_TRANS_TYPE_UNDEF 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_TRANS_TYPE_WRITE 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_TRANS_TYPE_WRITE_ACK 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_CMD 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_CMD_NONE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_A_CMD_GO 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B 0x0001ce00 /* RWE4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_USE_BASE_ADDR_NOT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_ADDR 25:2 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_ADDR_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_TRANS_STATUS 28:27 /* R-EVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_TRANS_STATUS_IDLE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_TRANS_STATUS_PENDING 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_TRANS_STATUS_DONE 0x00000002 /* R---V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_TRANS_TYPE 30:29 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_TRANS_TYPE_READ 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_TRANS_TYPE_UNDEF 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_TRANS_TYPE_WRITE 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_TRANS_TYPE_WRITE_ACK 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_CMD 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_CMD_NONE 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_B_CMD_GO 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_PV_PRIV_READ_DATA 0x0001cb00 /* R--4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_READ_DATA_V 31:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_READ_DATA_A 0x0001d500 /* R--4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_READ_DATA_A_V 31:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_READ_DATA_B 0x0001d600 /* R--4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_READ_DATA_B_V 31:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA 0x0001cc00 /* RWE4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_A 0x0001cf00 /* RWE4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_A__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_A_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_A_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_B 0x0001d400 /* RWE4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_B__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_B_V 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_WRITE_DATA_B_V_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_STATUS 0x0001d900 /* R--4R */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_STATUS_PRIV_LEVEL 1:0 /* R--VF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_STATUS_PRIV_LEVEL_A 5:4 /* R--VF */ #define NV_CTXSW_FIRMWARE_PV_PRIV_REQ_STATUS_PRIV_LEVEL_B 9:8 /* R--VF */ #define NV_CTXSW_FIRMWARE_PVS_COMPUTED_CHECKSUM 0x0001dd00 /* RWE4R */ #define NV_CTXSW_FIRMWARE_PVS_COMPUTED_CHECKSUM__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_COMPUTED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_SAVED_CHECKSUM 0x0001de00 /* RWE4R */ #define NV_CTXSW_FIRMWARE_PVS_SAVED_CHECKSUM__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_SAVED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_CHECKSUM 0x0001df00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PVS_CHECKSUM__PRIV_LEVEL_MASK 0x0001d800 /* */ #define NV_CTXSW_FIRMWARE_PVS_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PVS_CHECKSUM_CTRL_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PVS_CHECKSUM_CTRL_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_PVS_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_CTXSW_FIRMWARE_PVS_CHECKSUM_STATUS_MATCH 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_PVS_CHECKSUM_STATUS_MISMATCH 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_ARB_LANE_CTL(i) (0x00028000+(i)*4) /* RW-4A */ #define NV_CTXSW_FIRMWARE_ARB_LANE_CTL__SIZE_1 12 /* */ #define NV_CTXSW_FIRMWARE_ARB_LANE_CTL_RETURN_FIFO_ENTRIES 3:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_LANE_CTL_RETURN_FIFO_ENTRIES_V 0x00000008 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_LANE_CTL_WRR_WEIGHT 6:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_LANE_CTL_WRR_WEIGHT_V 0x00000007 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_BASE_ADDR 0x00028100 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_BASE_ADDR_F 31:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_HI_BASE_ADDR 0x00028e00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_HI_BASE_ADDR_F 8:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_HI_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_ENGINE_CTL 0x00028f00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_ENGINE_CTL_ENGINE_ID 7:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_ENGINE_CTL_ENGINE_ID_VEID0 0x00000040 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_ENGINE_CTL_ENGINE_ID_BAR2_FN0 0x000000c0 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_ENGINE_CTL_VEID 21:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_ENGINE_CTL_VEID_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_ENGINE_CTL_GFID 29:24 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_ENGINE_CTL_GFID_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_PREFETCH_CTL 0x00028200 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_PREFETCH_CTL_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_PREFETCH_CTL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_PREFETCH_CTL_OFFSET_V 0x0000000a /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK 0x00028a00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_ADR 0x00028900 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_CTX_ADR__PRIV_LEVEL_MASK 0x00028a00 /* */ #define NV_CTXSW_FIRMWARE_ARB_CTX_ADR_LO 11:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_ADR_LO_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_ADR_L2_CLASS 17:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_ADR_L2_CLASS_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_ADR_RD 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_ADR_RD_WR 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_ADR_RD_RD 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_PTR 0x00028300 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_CTX_PTR__PRIV_LEVEL_MASK 0x00028a00 /* */ #define NV_CTXSW_FIRMWARE_ARB_CTX_PTR_PTR 27:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_PTR_PTR_0 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_PTR_TARGET 29:28 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_PTR_TARGET_VID_MEM 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_PTR_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_PTR_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD 0x00028400 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD__PRIV_LEVEL_MASK 0x00028a00 /* */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD 4:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_FLUSH 0x00000005 /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_SOFT_FLUSH 0x00000006 /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_BIND_INST_BLK_PTR 0x00000007 /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_MMU_TLB_INVALIDATE 0x00000009 /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_PREFETCH 0x0000000a /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_PHYSICAL_L2_CACHE_MGMT 0x0000000b /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_CACHE_MGMT 0x0000000c /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_L2_PEER_INVALIDATE 0x0000000d /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_L2_SYSMEM_INVALIDATE 0x0000000e /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_CLEAN_COMPTAGS 0x0000000f /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_FLUSH_DIRTY 0x00000010 /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_CMD_MEMBAR 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_SUB_OP 8:7 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_SUB_OP_INVALIDATE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_SUB_OP_CLEAN 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_SUB_OP_DEMOTE 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE 9:9 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACK 17:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACK_DEFAULT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACK_FLUSH 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACK_TLB 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACK_MEM 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACK_NONE_REQUIRED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACK_GLOBALLY 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_ACK_INTRANODE 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_HALT 30:30 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_HALT_V 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_HALT_REQUEST 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_UNHALT 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_UNHALT_V 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CTX_CMD_UNHALT_REQUEST 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_L2_EVICTION_CTL 0x00028500 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_L2_EVICTION_CTL_WR 1:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_L2_EVICTION_CTL_WR_FIRST 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_L2_EVICTION_CTL_WR_NORMAL 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_L2_EVICTION_CTL_WR_LAST 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_L2_EVICTION_CTL_RD 9:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_L2_EVICTION_CTL_RD_FIRST 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_L2_EVICTION_CTL_RD_NORMAL 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_L2_EVICTION_CTL_RD_LAST 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_PRIV 0x00028600 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_PRIV_OVERRIDE 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_PRIV_OVERRIDE_PRIV 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_PRIV_OVERRIDE_NONPRIV 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_STATUS 0x00028700 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_CLEAR 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_CLEAR_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_CLEAR_CLEAR 0x00000001 /* -W--T */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_ACK 1:1 /* R-EVF */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_ACK_OK 0x00000001 /* R-E-V */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_ACK_NACK 0x00000000 /* R---V */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_SUBID 15:2 /* R--VF */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_OUTSTANDING_TRANSACTIONS 23:16 /* R--VF */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_BUFFER_NOT_EMPTY 24:24 /* R--VF */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_FLUSH_WHEN_BUSY 28:28 /* R-EVF */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_FLUSH_WHEN_BUSY_DEFAULT 0x00000000 /* R-E-V */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_FLUSH_WHEN_BUSY_ERROR 0x00000001 /* R---V */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_HALTED 30:30 /* R--VF */ #define NV_CTXSW_FIRMWARE_ARB_STATUS_BUSY 31:31 /* R--VF */ #define NV_CTXSW_FIRMWARE_ARB_CMD_OVERRIDE 0x00028800 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_CMD_OVERRIDE_CMD 4:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CMD_OVERRIDE_CMD_VIRTUAL 0x00000001 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CMD_OVERRIDE_CMD_PHYS_VID_MEM 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_COHERENT 0x00000004 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_CMD_OVERRIDE_ENABLE 31:31 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_CMD_OVERRIDE_ENABLE_OFF 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_CMD_OVERRIDE_ENABLE_ON 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_WPR 0x00028b00 /* RWE4R */ #define NV_CTXSW_FIRMWARE_ARB_WPR__PRIV_LEVEL_MASK 0x00028a00 /* */ #define NV_CTXSW_FIRMWARE_ARB_WPR_RC_ID 1:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_RC_ID_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_RC_SECURE_LEVEL 5:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_RC_SECURE_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PVS_ID 9:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PVS_ID_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PVS_SECURE_LEVEL 13:12 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_PVS_SECURE_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_CMD_ID 17:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_CMD_ID_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_CMD_SECURE_LEVEL 21:20 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_CMD_SECURE_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES 24:24 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_BLOCKED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_ALLOWED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK 0x00028c00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG 0x00028d00 /* RWE4R */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG__PRIV_LEVEL_MASK 0x00028c00 /* */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T0 3:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T0_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T1 7:4 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T1_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T2 11:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T2_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T3 15:12 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T3_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T4 19:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T4_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T5 23:20 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T5_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T6 27:24 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T6_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T7 31:28 /* RWEVF */ #define NV_CTXSW_FIRMWARE_ARB_FALCON_REGIONCFG_T7_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PERFMON 0x00022800 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL 6:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_FB_CMD 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_FB_CMD2 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_FB_CMD3 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_FB_DATA 0x00000003 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_MISC_0 0x00000004 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_MISC_1 0x00000005 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_0 0x00000006 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_1 0x00000007 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_2 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_3 0x00000009 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_4 0x0000000a /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_5 0x0000000b /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_6 0x0000000c /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_7 0x0000000d /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_8 0x0000000e /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_9 0x0000000f /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_10 0x00000010 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_11 0x00000011 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_12 0x00000012 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_13 0x00000013 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_14 0x00000014 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_15 0x00000015 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_16 0x00000016 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_17 0x00000017 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_18 0x00000018 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_0 0x00000019 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_1 0x0000001a /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_2 0x0000001b /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_3 0x0000001c /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_4 0x0000001d /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_5 0x0000001e /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_6 0x0000001f /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_7 0x00000020 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_8 0x00000021 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_9 0x00000022 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_RC_10 0x00000023 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_0 0x00000024 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_1 0x00000025 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_2 0x00000026 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_3 0x00000027 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_4 0x00000028 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_5 0x00000029 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_6 0x0000002a /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_7 0x0000002b /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_8 0x0000002c /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_9 0x0000002d /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_10 0x0000002e /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PROBE_0 0x0000002f /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PROBE_1 0x00000030 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_ARB_0 0x00000031 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_ARB_1 0x00000032 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_ERR 0x00000033 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_MISC_2 0x00000034 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_MISC_3 0x00000035 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_MISC_4 0x00000036 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_MISC_5 0x00000037 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_MISC_6 0x00000038 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_19 0x00000039 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_20 0x0000003a /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_21 0x0000003b /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_22 0x0000003c /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_23 0x0000003d /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_24 0x0000003e /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_25 0x0000003f /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_26 0x00000040 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_27 0x00000041 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_28 0x00000042 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_29 0x00000043 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_30 0x00000044 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_31 0x00000045 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_32 0x00000046 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_33 0x00000047 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_34 0x00000048 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_35 0x00000049 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_PRI_36 0x0000004a /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATIC_PATTERN_55_8_GROUP 0x0000004b /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATIC_PATTERN_AA_8_GROUP 0x0000004c /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_11 0x0000004d /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_12 0x0000004e /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_13 0x0000004f /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_14 0x00000050 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_STATUS_15 0x00000051 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_CTXSW_0 0x00000052 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_SEL_ECC_ERR 0x00000053 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_CTRL_ENABLE 8:8 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PERFMON_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_CTRL_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM 0x00022a00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE 7:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE_TOGGLE_BIT0 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE_TOGGLE_BIT1 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE_TOGGLE_BIT2 0x00000004 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE_TOGGLE_BIT3 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE_TOGGLE_BIT4 0x00000010 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE_TOGGLE_BIT5 0x00000020 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE_TOGGLE_BIT6 0x00000040 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_PROBE_TOGGLE_BIT7 0x00000080 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET 23:16 /* -WEVF */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET_INIT 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET_BIT0 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET_BIT1 0x00000002 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET_BIT2 0x00000004 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET_BIT3 0x00000008 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET_BIT4 0x00000010 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET_BIT5 0x00000020 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET_BIT6 0x00000040 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_SET_BIT7 0x00000080 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR 31:24 /* -WEVF */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR_INIT 0x00000000 /* -WE-V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR_BIT0 0x00000001 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR_BIT1 0x00000002 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR_BIT2 0x00000004 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR_BIT3 0x00000008 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR_BIT4 0x00000010 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR_BIT5 0x00000020 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR_BIT6 0x00000040 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_PM_CLEAR_BIT7 0x00000080 /* -W--V */ #define NV_CTXSW_FIRMWARE_PERFMON_MODE 0x00022900 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PERFMON_MODE_PROBE 7:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PERFMON_MODE_PROBE_INIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE 0x0001ac00 /* RW-4R */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE 3:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_IDLE 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_SAVE_OVERHEAD 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_SAVE_WAIT_FOR_FE 0x00000002 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_SAVE_WFI 0x00000004 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_SAVE_GFXP 0x00000005 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_SAVE_CILP 0x00000006 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_SAVE_CTA 0x00000007 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_RESTORE_OVERHEAD 0x00000008 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_RESTORE_WFI 0x00000009 /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_RESTORE_GFXP 0x0000000a /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_RESTORE_CILP 0x0000000b /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_RESTORE_CTA 0x0000000c /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_RESTORE_PATCH_BUFFER 0x0000000d /* RW--V */ #define NV_CTXSW_FIRMWARE_PERFMON_UCODE_STATE_SCRUB 0x0000000e /* RW--V */ #define NV_CTXSW_FIRMWARE_CG 0x00022400 /* RWE4R */ #define NV_CTXSW_FIRMWARE_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CG_IDLE_CG_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CG_IDLE_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CG_STATE_CG_EN 7:7 /* */ #define NV_CTXSW_FIRMWARE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_CTXSW_FIRMWARE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_CTXSW_FIRMWARE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_CNT 23:20 /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_CTXSW_FIRMWARE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_EN 28:28 /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_PAUSE_CG_EN 30:30 /* */ #define NV_CTXSW_FIRMWARE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_HALT_CG_EN 31:31 /* */ #define NV_CTXSW_FIRMWARE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_CTXSW_FIRMWARE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_CTXSW_FIRMWARE_CG1 0x00022500 /* RWE4R */ #define NV_CTXSW_FIRMWARE_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_CTXSW_FIRMWARE_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_CTXSW_FIRMWARE_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_CTXSW_FIRMWARE_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #endif // __ga102_dev_ctxsw_firmware_h__