/* _NVRM_COPYRIGHT_BEGIN_
 *
 * Copyright 2003-2016 by NVIDIA Corporation.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 *
 * _NVRM_COPYRIGHT_END_
 */

#ifndef __ga102_dev_chiplet_pwr_h__
#define __ga102_dev_chiplet_pwr_h__
/* This file is autogenerated.  Do not edit */
#define NV_PCHIPLET_PWR                                             0x0010e1ff:0x0010c000 /* RW--D */
#define NV_PCHIPLET_PWR_GPC                                         0x0010c6ff:0x0010c000 /* RW--L */
#define NV_PCHIPLET_PWR_GPC0                                        0x0010c0ff:0x0010c000 /* RW--L */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010c070 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6                                          0x0010c018 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6__PRIV_LEVEL_MASK                         0x0010c070 /*       */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6_TEX                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6_TEX_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6_CROP                                           15:8 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6_CROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6_ZROP                                          23:16 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6_ZROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6_PE                                            31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_6_PE_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_7                                          0x0010c01c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_7__PRIV_LEVEL_MASK                         0x0010c070 /*       */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_7_SM                                              7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_7_SM_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_7_PES                                           31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC0_WEIGHT_7_PES_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_1                                          0x0010c03c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_1__PRIV_LEVEL_MASK                         0x0010c070 /*       */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_1_BA_IDLE_THRESHOLD                              31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_1_BA_IDLE_THRESHOLD_INIT                     0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2                                          0x0010c044 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2__PRIV_LEVEL_MASK                         0x0010c070 /*       */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_DATA                                          23:16 /* R--VF */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_SM_TEXAM                           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_SM_TEXDF                           0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_SM_SFE                             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_SM_SCTL                            0x3 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_SM_L1C                             0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_SM_TTU                             0x5 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_CROP                               0x6 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_ZROP                               0x7 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_PE                                 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CONFIG_2_BA_PLUGIN_ID_PES                                0x9 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_GPCCS_IDLE_FILTER                                 0x0010c04c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC0_GPCCS_IDLE_FILTER_VALUE                                 31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_GPCCS_IDLE_FILTER_VALUE_INIT                      0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_0                                           0x0010c050 /* RWE4R */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_1                                           0x0010c054 /* R--4R */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R--VF */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_1_CLK_DISABLE                                      5:5 /* R--VF */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_1_PRIV_IDLE                                        6:6 /* R--VF */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_1_CLK_FORCE                                        8:7 /* R--VF */
#define NV_PCHIPLET_PWR_GPC0_DEBUG_1_GATEABLE                                         9:9 /* R--VF */
#define NV_PCHIPLET_PWR_GPC0_CG1                                               0x0010c07c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC0_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_SM_HIGH_POWER_CTRL                                0x0010c08c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC0_SM_HIGH_POWER_CTRL_DELAY                                15:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_SM_HIGH_POWER_CTRL_DELAY_INIT                         0x0000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_SM_HIGH_POWER_CTRL_DELAY_MAX                          0xffff /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_SM_HIGH_POWER_CTRL_EN                                  31:31 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC0_SM_HIGH_POWER_CTRL_EN_DISABLE                            0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC0_SM_HIGH_POWER_CTRL_EN_ENABLE                             0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010c090 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010c038 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_RAM_STAGGER_CONFIG                                0x0010c098 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010c090 /*       */
#define NV_PCHIPLET_PWR_GPC0_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_GROUP_TOP_ORDER                                   0x0010c09c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010c090 /*       */
#define NV_PCHIPLET_PWR_GPC0_GROUP_TOP_ORDER_GR_RAM                                  13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX                 0x0010c0a0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c090 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX                  5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX             0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION                       0x0010c0a4 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c090 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX       0x0010c0a0 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT                0x20 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT                0x21 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_2_ORDER_INIT                0x34 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_3_ORDER_INIT                0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_4_ORDER_INIT                0x10 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_5_ORDER_INIT                0x11 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_6_ORDER_INIT                0x2c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_7_ORDER_INIT                0x22 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_9_ORDER_INIT                0x36 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_10_ORDER_INIT               0x37 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_11_ORDER_INIT               0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_12_ORDER_INIT               0x13 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_13_ORDER_INIT               0x2d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_14_ORDER_INIT               0x24 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_15_ORDER_INIT               0x25 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_16_ORDER_INIT               0x38 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_17_ORDER_INIT               0x39 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_18_ORDER_INIT               0x14 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_19_ORDER_INIT               0x15 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_20_ORDER_INIT               0x2e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_21_ORDER_INIT               0x26 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_22_ORDER_INIT               0x27 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_23_ORDER_INIT               0x3a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_24_ORDER_INIT               0x3b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_25_ORDER_INIT               0x16 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_26_ORDER_INIT               0x17 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_27_ORDER_INIT               0x2f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_28_ORDER_INIT               0x28 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_29_ORDER_INIT               0x29 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_30_ORDER_INIT               0x3c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_31_ORDER_INIT               0x3d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_32_ORDER_INIT               0x18 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_33_ORDER_INIT               0x19 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_34_ORDER_INIT               0x30 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_35_ORDER_INIT               0x2a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_36_ORDER_INIT               0x2b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_37_ORDER_INIT               0x3e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_38_ORDER_INIT               0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_39_ORDER_INIT               0x1a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_40_ORDER_INIT               0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_41_ORDER_INIT               0x31 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_42_ORDER_INIT               0x0a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_43_ORDER_INIT               0x04 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_44_ORDER_INIT               0x0b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_45_ORDER_INIT               0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_46_ORDER_INIT               0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_47_ORDER_INIT               0x32 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_48_ORDER_INIT               0x1e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_49_ORDER_INIT               0x33 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_50_ORDER_INIT               0x1c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_51_ORDER_INIT               0x1d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_52_ORDER_INIT               0x01 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_53_ORDER_INIT               0x02 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_54_ORDER_INIT               0x0c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_55_ORDER_INIT               0x06 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_56_ORDER_INIT               0x0d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_57_ORDER_INIT               0x07 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_58_ORDER_INIT               0x0e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_59_ORDER_INIT               0x08 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_60_ORDER_INIT               0x0f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_61_ORDER_INIT               0x09 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX                0x0010c028 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c038 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX                 5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX            0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1                      0x0010c02c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c038 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX      0x0010c028 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010c0a8 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c090 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN              0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX              0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION                       0x0010c0ac /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c090 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010c0a8 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010c030 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c038 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN             0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1                      0x0010c034 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c038 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010c030 /*       */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE                            0x0010c0b0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010c090 /*       */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC0_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1                                        0x0010c1ff:0x0010c100 /* RW--L */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010c170 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6                                          0x0010c118 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6__PRIV_LEVEL_MASK                         0x0010c170 /*       */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6_TEX                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6_TEX_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6_CROP                                           15:8 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6_CROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6_ZROP                                          23:16 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6_ZROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6_PE                                            31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_6_PE_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_7                                          0x0010c11c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_7__PRIV_LEVEL_MASK                         0x0010c170 /*       */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_7_SM                                              7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_7_SM_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_7_PES                                           31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC1_WEIGHT_7_PES_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_1                                          0x0010c13c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_1__PRIV_LEVEL_MASK                         0x0010c170 /*       */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_1_BA_IDLE_THRESHOLD                              31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_1_BA_IDLE_THRESHOLD_INIT                     0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2                                          0x0010c144 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2__PRIV_LEVEL_MASK                         0x0010c170 /*       */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_DATA                                          23:16 /* R--VF */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_SM_TEXAM                           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_SM_TEXDF                           0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_SM_SFE                             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_SM_SCTL                            0x3 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_SM_L1C                             0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_SM_TTU                             0x5 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_CROP                               0x6 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_ZROP                               0x7 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_PE                                 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CONFIG_2_BA_PLUGIN_ID_PES                                0x9 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_GPCCS_IDLE_FILTER                                 0x0010c14c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC1_GPCCS_IDLE_FILTER_VALUE                                 31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_GPCCS_IDLE_FILTER_VALUE_INIT                      0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_0                                           0x0010c150 /* RWE4R */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_1                                           0x0010c154 /* R--4R */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R--VF */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_1_CLK_DISABLE                                      5:5 /* R--VF */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_1_PRIV_IDLE                                        6:6 /* R--VF */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_1_CLK_FORCE                                        8:7 /* R--VF */
#define NV_PCHIPLET_PWR_GPC1_DEBUG_1_GATEABLE                                         9:9 /* R--VF */
#define NV_PCHIPLET_PWR_GPC1_CG1                                               0x0010c17c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC1_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_SM_HIGH_POWER_CTRL                                0x0010c18c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC1_SM_HIGH_POWER_CTRL_DELAY                                15:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_SM_HIGH_POWER_CTRL_DELAY_INIT                         0x0000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_SM_HIGH_POWER_CTRL_DELAY_MAX                          0xffff /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_SM_HIGH_POWER_CTRL_EN                                  31:31 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC1_SM_HIGH_POWER_CTRL_EN_DISABLE                            0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC1_SM_HIGH_POWER_CTRL_EN_ENABLE                             0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010c190 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010c138 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_RAM_STAGGER_CONFIG                                0x0010c198 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010c190 /*       */
#define NV_PCHIPLET_PWR_GPC1_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_GROUP_TOP_ORDER                                   0x0010c19c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010c190 /*       */
#define NV_PCHIPLET_PWR_GPC1_GROUP_TOP_ORDER_GR_RAM                                  13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX                 0x0010c1a0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c190 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX                  5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX             0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION                       0x0010c1a4 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c190 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX       0x0010c1a0 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT                0x20 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT                0x21 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_2_ORDER_INIT                0x34 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_3_ORDER_INIT                0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_4_ORDER_INIT                0x10 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_5_ORDER_INIT                0x11 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_6_ORDER_INIT                0x2c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_7_ORDER_INIT                0x22 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_9_ORDER_INIT                0x36 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_10_ORDER_INIT               0x37 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_11_ORDER_INIT               0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_12_ORDER_INIT               0x13 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_13_ORDER_INIT               0x2d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_14_ORDER_INIT               0x24 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_15_ORDER_INIT               0x25 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_16_ORDER_INIT               0x38 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_17_ORDER_INIT               0x39 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_18_ORDER_INIT               0x14 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_19_ORDER_INIT               0x15 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_20_ORDER_INIT               0x2e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_21_ORDER_INIT               0x26 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_22_ORDER_INIT               0x27 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_23_ORDER_INIT               0x3a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_24_ORDER_INIT               0x3b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_25_ORDER_INIT               0x16 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_26_ORDER_INIT               0x17 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_27_ORDER_INIT               0x2f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_28_ORDER_INIT               0x28 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_29_ORDER_INIT               0x29 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_30_ORDER_INIT               0x3c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_31_ORDER_INIT               0x3d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_32_ORDER_INIT               0x18 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_33_ORDER_INIT               0x19 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_34_ORDER_INIT               0x30 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_35_ORDER_INIT               0x2a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_36_ORDER_INIT               0x2b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_37_ORDER_INIT               0x3e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_38_ORDER_INIT               0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_39_ORDER_INIT               0x1a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_40_ORDER_INIT               0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_41_ORDER_INIT               0x31 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_42_ORDER_INIT               0x0a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_43_ORDER_INIT               0x04 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_44_ORDER_INIT               0x0b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_45_ORDER_INIT               0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_46_ORDER_INIT               0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_47_ORDER_INIT               0x32 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_48_ORDER_INIT               0x1e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_49_ORDER_INIT               0x33 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_50_ORDER_INIT               0x1c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_51_ORDER_INIT               0x1d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_52_ORDER_INIT               0x01 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_53_ORDER_INIT               0x02 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_54_ORDER_INIT               0x0c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_55_ORDER_INIT               0x06 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_56_ORDER_INIT               0x0d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_57_ORDER_INIT               0x07 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_58_ORDER_INIT               0x0e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_59_ORDER_INIT               0x08 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_60_ORDER_INIT               0x0f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_61_ORDER_INIT               0x09 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX                0x0010c128 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c138 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX                 5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX            0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1                      0x0010c12c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c138 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX      0x0010c128 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010c1a8 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c190 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN              0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX              0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION                       0x0010c1ac /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c190 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010c1a8 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010c130 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c138 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN             0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1                      0x0010c134 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c138 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010c130 /*       */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE                            0x0010c1b0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010c190 /*       */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC1_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2                                        0x0010c2ff:0x0010c200 /* RW--L */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010c270 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6                                          0x0010c218 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6__PRIV_LEVEL_MASK                         0x0010c270 /*       */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6_TEX                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6_TEX_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6_CROP                                           15:8 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6_CROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6_ZROP                                          23:16 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6_ZROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6_PE                                            31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_6_PE_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_7                                          0x0010c21c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_7__PRIV_LEVEL_MASK                         0x0010c270 /*       */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_7_SM                                              7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_7_SM_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_7_PES                                           31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC2_WEIGHT_7_PES_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_1                                          0x0010c23c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_1__PRIV_LEVEL_MASK                         0x0010c270 /*       */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_1_BA_IDLE_THRESHOLD                              31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_1_BA_IDLE_THRESHOLD_INIT                     0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2                                          0x0010c244 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2__PRIV_LEVEL_MASK                         0x0010c270 /*       */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_DATA                                          23:16 /* R--VF */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_SM_TEXAM                           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_SM_TEXDF                           0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_SM_SFE                             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_SM_SCTL                            0x3 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_SM_L1C                             0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_SM_TTU                             0x5 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_CROP                               0x6 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_ZROP                               0x7 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_PE                                 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CONFIG_2_BA_PLUGIN_ID_PES                                0x9 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_GPCCS_IDLE_FILTER                                 0x0010c24c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC2_GPCCS_IDLE_FILTER_VALUE                                 31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_GPCCS_IDLE_FILTER_VALUE_INIT                      0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_0                                           0x0010c250 /* RWE4R */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_1                                           0x0010c254 /* R--4R */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R--VF */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_1_CLK_DISABLE                                      5:5 /* R--VF */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_1_PRIV_IDLE                                        6:6 /* R--VF */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_1_CLK_FORCE                                        8:7 /* R--VF */
#define NV_PCHIPLET_PWR_GPC2_DEBUG_1_GATEABLE                                         9:9 /* R--VF */
#define NV_PCHIPLET_PWR_GPC2_CG1                                               0x0010c27c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC2_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_SM_HIGH_POWER_CTRL                                0x0010c28c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC2_SM_HIGH_POWER_CTRL_DELAY                                15:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_SM_HIGH_POWER_CTRL_DELAY_INIT                         0x0000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_SM_HIGH_POWER_CTRL_DELAY_MAX                          0xffff /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_SM_HIGH_POWER_CTRL_EN                                  31:31 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC2_SM_HIGH_POWER_CTRL_EN_DISABLE                            0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC2_SM_HIGH_POWER_CTRL_EN_ENABLE                             0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010c290 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010c238 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_RAM_STAGGER_CONFIG                                0x0010c298 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010c290 /*       */
#define NV_PCHIPLET_PWR_GPC2_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_GROUP_TOP_ORDER                                   0x0010c29c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010c290 /*       */
#define NV_PCHIPLET_PWR_GPC2_GROUP_TOP_ORDER_GR_RAM                                  13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX                 0x0010c2a0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c290 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX                  5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX             0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION                       0x0010c2a4 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c290 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX       0x0010c2a0 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT                0x20 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT                0x21 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_2_ORDER_INIT                0x34 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_3_ORDER_INIT                0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_4_ORDER_INIT                0x10 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_5_ORDER_INIT                0x11 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_6_ORDER_INIT                0x2c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_7_ORDER_INIT                0x22 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_9_ORDER_INIT                0x36 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_10_ORDER_INIT               0x37 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_11_ORDER_INIT               0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_12_ORDER_INIT               0x13 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_13_ORDER_INIT               0x2d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_14_ORDER_INIT               0x24 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_15_ORDER_INIT               0x25 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_16_ORDER_INIT               0x38 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_17_ORDER_INIT               0x39 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_18_ORDER_INIT               0x14 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_19_ORDER_INIT               0x15 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_20_ORDER_INIT               0x2e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_21_ORDER_INIT               0x26 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_22_ORDER_INIT               0x27 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_23_ORDER_INIT               0x3a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_24_ORDER_INIT               0x3b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_25_ORDER_INIT               0x16 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_26_ORDER_INIT               0x17 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_27_ORDER_INIT               0x2f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_28_ORDER_INIT               0x28 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_29_ORDER_INIT               0x29 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_30_ORDER_INIT               0x3c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_31_ORDER_INIT               0x3d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_32_ORDER_INIT               0x18 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_33_ORDER_INIT               0x19 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_34_ORDER_INIT               0x30 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_35_ORDER_INIT               0x2a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_36_ORDER_INIT               0x2b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_37_ORDER_INIT               0x3e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_38_ORDER_INIT               0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_39_ORDER_INIT               0x1a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_40_ORDER_INIT               0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_41_ORDER_INIT               0x31 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_42_ORDER_INIT               0x0a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_43_ORDER_INIT               0x04 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_44_ORDER_INIT               0x0b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_45_ORDER_INIT               0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_46_ORDER_INIT               0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_47_ORDER_INIT               0x32 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_48_ORDER_INIT               0x1e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_49_ORDER_INIT               0x33 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_50_ORDER_INIT               0x1c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_51_ORDER_INIT               0x1d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_52_ORDER_INIT               0x01 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_53_ORDER_INIT               0x02 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_54_ORDER_INIT               0x0c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_55_ORDER_INIT               0x06 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_56_ORDER_INIT               0x0d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_57_ORDER_INIT               0x07 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_58_ORDER_INIT               0x0e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_59_ORDER_INIT               0x08 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_60_ORDER_INIT               0x0f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_61_ORDER_INIT               0x09 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX                0x0010c228 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c238 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX                 5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX            0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1                      0x0010c22c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c238 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX      0x0010c228 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010c2a8 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c290 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN              0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX              0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION                       0x0010c2ac /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c290 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010c2a8 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010c230 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c238 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN             0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1                      0x0010c234 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c238 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010c230 /*       */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE                            0x0010c2b0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010c290 /*       */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC2_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3                                        0x0010c3ff:0x0010c300 /* RW--L */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010c370 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6                                          0x0010c318 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6__PRIV_LEVEL_MASK                         0x0010c370 /*       */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6_TEX                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6_TEX_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6_CROP                                           15:8 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6_CROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6_ZROP                                          23:16 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6_ZROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6_PE                                            31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_6_PE_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_7                                          0x0010c31c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_7__PRIV_LEVEL_MASK                         0x0010c370 /*       */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_7_SM                                              7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_7_SM_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_7_PES                                           31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC3_WEIGHT_7_PES_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_1                                          0x0010c33c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_1__PRIV_LEVEL_MASK                         0x0010c370 /*       */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_1_BA_IDLE_THRESHOLD                              31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_1_BA_IDLE_THRESHOLD_INIT                     0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2                                          0x0010c344 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2__PRIV_LEVEL_MASK                         0x0010c370 /*       */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_DATA                                          23:16 /* R--VF */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_SM_TEXAM                           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_SM_TEXDF                           0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_SM_SFE                             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_SM_SCTL                            0x3 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_SM_L1C                             0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_SM_TTU                             0x5 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_CROP                               0x6 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_ZROP                               0x7 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_PE                                 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CONFIG_2_BA_PLUGIN_ID_PES                                0x9 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_GPCCS_IDLE_FILTER                                 0x0010c34c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC3_GPCCS_IDLE_FILTER_VALUE                                 31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_GPCCS_IDLE_FILTER_VALUE_INIT                      0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_0                                           0x0010c350 /* RWE4R */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_1                                           0x0010c354 /* R--4R */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R--VF */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_1_CLK_DISABLE                                      5:5 /* R--VF */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_1_PRIV_IDLE                                        6:6 /* R--VF */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_1_CLK_FORCE                                        8:7 /* R--VF */
#define NV_PCHIPLET_PWR_GPC3_DEBUG_1_GATEABLE                                         9:9 /* R--VF */
#define NV_PCHIPLET_PWR_GPC3_CG1                                               0x0010c37c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC3_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_SM_HIGH_POWER_CTRL                                0x0010c38c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC3_SM_HIGH_POWER_CTRL_DELAY                                15:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_SM_HIGH_POWER_CTRL_DELAY_INIT                         0x0000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_SM_HIGH_POWER_CTRL_DELAY_MAX                          0xffff /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_SM_HIGH_POWER_CTRL_EN                                  31:31 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC3_SM_HIGH_POWER_CTRL_EN_DISABLE                            0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC3_SM_HIGH_POWER_CTRL_EN_ENABLE                             0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010c390 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010c338 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_RAM_STAGGER_CONFIG                                0x0010c398 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010c390 /*       */
#define NV_PCHIPLET_PWR_GPC3_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_GROUP_TOP_ORDER                                   0x0010c39c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010c390 /*       */
#define NV_PCHIPLET_PWR_GPC3_GROUP_TOP_ORDER_GR_RAM                                  13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX                 0x0010c3a0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c390 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX                  5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX             0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION                       0x0010c3a4 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c390 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX       0x0010c3a0 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT                0x20 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT                0x21 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_2_ORDER_INIT                0x34 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_3_ORDER_INIT                0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_4_ORDER_INIT                0x10 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_5_ORDER_INIT                0x11 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_6_ORDER_INIT                0x2c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_7_ORDER_INIT                0x22 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_9_ORDER_INIT                0x36 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_10_ORDER_INIT               0x37 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_11_ORDER_INIT               0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_12_ORDER_INIT               0x13 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_13_ORDER_INIT               0x2d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_14_ORDER_INIT               0x24 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_15_ORDER_INIT               0x25 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_16_ORDER_INIT               0x38 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_17_ORDER_INIT               0x39 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_18_ORDER_INIT               0x14 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_19_ORDER_INIT               0x15 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_20_ORDER_INIT               0x2e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_21_ORDER_INIT               0x26 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_22_ORDER_INIT               0x27 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_23_ORDER_INIT               0x3a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_24_ORDER_INIT               0x3b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_25_ORDER_INIT               0x16 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_26_ORDER_INIT               0x17 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_27_ORDER_INIT               0x2f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_28_ORDER_INIT               0x28 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_29_ORDER_INIT               0x29 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_30_ORDER_INIT               0x3c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_31_ORDER_INIT               0x3d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_32_ORDER_INIT               0x18 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_33_ORDER_INIT               0x19 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_34_ORDER_INIT               0x30 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_35_ORDER_INIT               0x2a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_36_ORDER_INIT               0x2b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_37_ORDER_INIT               0x3e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_38_ORDER_INIT               0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_39_ORDER_INIT               0x1a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_40_ORDER_INIT               0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_41_ORDER_INIT               0x31 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_42_ORDER_INIT               0x0a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_43_ORDER_INIT               0x04 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_44_ORDER_INIT               0x0b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_45_ORDER_INIT               0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_46_ORDER_INIT               0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_47_ORDER_INIT               0x32 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_48_ORDER_INIT               0x1e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_49_ORDER_INIT               0x33 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_50_ORDER_INIT               0x1c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_51_ORDER_INIT               0x1d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_52_ORDER_INIT               0x01 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_53_ORDER_INIT               0x02 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_54_ORDER_INIT               0x0c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_55_ORDER_INIT               0x06 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_56_ORDER_INIT               0x0d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_57_ORDER_INIT               0x07 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_58_ORDER_INIT               0x0e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_59_ORDER_INIT               0x08 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_60_ORDER_INIT               0x0f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_61_ORDER_INIT               0x09 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX                0x0010c328 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c338 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX                 5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX            0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1                      0x0010c32c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c338 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX      0x0010c328 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010c3a8 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c390 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN              0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX              0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION                       0x0010c3ac /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c390 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010c3a8 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010c330 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c338 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN             0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1                      0x0010c334 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c338 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010c330 /*       */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE                            0x0010c3b0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010c390 /*       */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC3_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4                                        0x0010c4ff:0x0010c400 /* RW--L */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010c470 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6                                          0x0010c418 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6__PRIV_LEVEL_MASK                         0x0010c470 /*       */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6_TEX                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6_TEX_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6_CROP                                           15:8 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6_CROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6_ZROP                                          23:16 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6_ZROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6_PE                                            31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_6_PE_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_7                                          0x0010c41c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_7__PRIV_LEVEL_MASK                         0x0010c470 /*       */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_7_SM                                              7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_7_SM_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_7_PES                                           31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC4_WEIGHT_7_PES_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_1                                          0x0010c43c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_1__PRIV_LEVEL_MASK                         0x0010c470 /*       */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_1_BA_IDLE_THRESHOLD                              31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_1_BA_IDLE_THRESHOLD_INIT                     0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2                                          0x0010c444 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2__PRIV_LEVEL_MASK                         0x0010c470 /*       */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_DATA                                          23:16 /* R--VF */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_SM_TEXAM                           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_SM_TEXDF                           0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_SM_SFE                             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_SM_SCTL                            0x3 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_SM_L1C                             0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_SM_TTU                             0x5 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_CROP                               0x6 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_ZROP                               0x7 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_PE                                 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CONFIG_2_BA_PLUGIN_ID_PES                                0x9 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_GPCCS_IDLE_FILTER                                 0x0010c44c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC4_GPCCS_IDLE_FILTER_VALUE                                 31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_GPCCS_IDLE_FILTER_VALUE_INIT                      0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_0                                           0x0010c450 /* RWE4R */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_1                                           0x0010c454 /* R--4R */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R--VF */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_1_CLK_DISABLE                                      5:5 /* R--VF */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_1_PRIV_IDLE                                        6:6 /* R--VF */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_1_CLK_FORCE                                        8:7 /* R--VF */
#define NV_PCHIPLET_PWR_GPC4_DEBUG_1_GATEABLE                                         9:9 /* R--VF */
#define NV_PCHIPLET_PWR_GPC4_CG1                                               0x0010c47c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC4_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_SM_HIGH_POWER_CTRL                                0x0010c48c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC4_SM_HIGH_POWER_CTRL_DELAY                                15:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_SM_HIGH_POWER_CTRL_DELAY_INIT                         0x0000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_SM_HIGH_POWER_CTRL_DELAY_MAX                          0xffff /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_SM_HIGH_POWER_CTRL_EN                                  31:31 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC4_SM_HIGH_POWER_CTRL_EN_DISABLE                            0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC4_SM_HIGH_POWER_CTRL_EN_ENABLE                             0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010c490 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010c438 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_RAM_STAGGER_CONFIG                                0x0010c498 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010c490 /*       */
#define NV_PCHIPLET_PWR_GPC4_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_GROUP_TOP_ORDER                                   0x0010c49c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010c490 /*       */
#define NV_PCHIPLET_PWR_GPC4_GROUP_TOP_ORDER_GR_RAM                                  13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX                 0x0010c4a0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c490 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX                  5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX             0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION                       0x0010c4a4 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c490 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX       0x0010c4a0 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT                0x20 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT                0x21 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_2_ORDER_INIT                0x34 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_3_ORDER_INIT                0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_4_ORDER_INIT                0x10 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_5_ORDER_INIT                0x11 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_6_ORDER_INIT                0x2c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_7_ORDER_INIT                0x22 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_9_ORDER_INIT                0x36 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_10_ORDER_INIT               0x37 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_11_ORDER_INIT               0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_12_ORDER_INIT               0x13 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_13_ORDER_INIT               0x2d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_14_ORDER_INIT               0x24 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_15_ORDER_INIT               0x25 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_16_ORDER_INIT               0x38 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_17_ORDER_INIT               0x39 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_18_ORDER_INIT               0x14 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_19_ORDER_INIT               0x15 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_20_ORDER_INIT               0x2e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_21_ORDER_INIT               0x26 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_22_ORDER_INIT               0x27 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_23_ORDER_INIT               0x3a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_24_ORDER_INIT               0x3b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_25_ORDER_INIT               0x16 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_26_ORDER_INIT               0x17 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_27_ORDER_INIT               0x2f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_28_ORDER_INIT               0x28 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_29_ORDER_INIT               0x29 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_30_ORDER_INIT               0x3c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_31_ORDER_INIT               0x3d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_32_ORDER_INIT               0x18 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_33_ORDER_INIT               0x19 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_34_ORDER_INIT               0x30 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_35_ORDER_INIT               0x2a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_36_ORDER_INIT               0x2b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_37_ORDER_INIT               0x3e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_38_ORDER_INIT               0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_39_ORDER_INIT               0x1a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_40_ORDER_INIT               0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_41_ORDER_INIT               0x31 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_42_ORDER_INIT               0x0a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_43_ORDER_INIT               0x04 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_44_ORDER_INIT               0x0b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_45_ORDER_INIT               0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_46_ORDER_INIT               0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_47_ORDER_INIT               0x32 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_48_ORDER_INIT               0x1e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_49_ORDER_INIT               0x33 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_50_ORDER_INIT               0x1c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_51_ORDER_INIT               0x1d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_52_ORDER_INIT               0x01 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_53_ORDER_INIT               0x02 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_54_ORDER_INIT               0x0c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_55_ORDER_INIT               0x06 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_56_ORDER_INIT               0x0d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_57_ORDER_INIT               0x07 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_58_ORDER_INIT               0x0e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_59_ORDER_INIT               0x08 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_60_ORDER_INIT               0x0f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_61_ORDER_INIT               0x09 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX                0x0010c428 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c438 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX                 5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX            0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1                      0x0010c42c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c438 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX      0x0010c428 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010c4a8 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c490 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN              0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX              0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION                       0x0010c4ac /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c490 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010c4a8 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010c430 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c438 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN             0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1                      0x0010c434 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c438 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010c430 /*       */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE                            0x0010c4b0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010c490 /*       */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC4_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5                                        0x0010c5ff:0x0010c500 /* RW--L */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010c570 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6                                          0x0010c518 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6__PRIV_LEVEL_MASK                         0x0010c570 /*       */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6_TEX                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6_TEX_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6_CROP                                           15:8 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6_CROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6_ZROP                                          23:16 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6_ZROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6_PE                                            31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_6_PE_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_7                                          0x0010c51c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_7__PRIV_LEVEL_MASK                         0x0010c570 /*       */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_7_SM                                              7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_7_SM_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_7_PES                                           31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC5_WEIGHT_7_PES_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_1                                          0x0010c53c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_1__PRIV_LEVEL_MASK                         0x0010c570 /*       */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_1_BA_IDLE_THRESHOLD                              31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_1_BA_IDLE_THRESHOLD_INIT                     0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2                                          0x0010c544 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2__PRIV_LEVEL_MASK                         0x0010c570 /*       */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_DATA                                          23:16 /* R--VF */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_SM_TEXAM                           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_SM_TEXDF                           0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_SM_SFE                             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_SM_SCTL                            0x3 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_SM_L1C                             0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_SM_TTU                             0x5 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_CROP                               0x6 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_ZROP                               0x7 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_PE                                 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CONFIG_2_BA_PLUGIN_ID_PES                                0x9 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_GPCCS_IDLE_FILTER                                 0x0010c54c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC5_GPCCS_IDLE_FILTER_VALUE                                 31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_GPCCS_IDLE_FILTER_VALUE_INIT                      0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_0                                           0x0010c550 /* RWE4R */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_1                                           0x0010c554 /* R--4R */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R--VF */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_1_CLK_DISABLE                                      5:5 /* R--VF */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_1_PRIV_IDLE                                        6:6 /* R--VF */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_1_CLK_FORCE                                        8:7 /* R--VF */
#define NV_PCHIPLET_PWR_GPC5_DEBUG_1_GATEABLE                                         9:9 /* R--VF */
#define NV_PCHIPLET_PWR_GPC5_CG1                                               0x0010c57c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC5_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_SM_HIGH_POWER_CTRL                                0x0010c58c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC5_SM_HIGH_POWER_CTRL_DELAY                                15:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_SM_HIGH_POWER_CTRL_DELAY_INIT                         0x0000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_SM_HIGH_POWER_CTRL_DELAY_MAX                          0xffff /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_SM_HIGH_POWER_CTRL_EN                                  31:31 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC5_SM_HIGH_POWER_CTRL_EN_DISABLE                            0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC5_SM_HIGH_POWER_CTRL_EN_ENABLE                             0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010c590 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010c538 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_RAM_STAGGER_CONFIG                                0x0010c598 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010c590 /*       */
#define NV_PCHIPLET_PWR_GPC5_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_GROUP_TOP_ORDER                                   0x0010c59c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010c590 /*       */
#define NV_PCHIPLET_PWR_GPC5_GROUP_TOP_ORDER_GR_RAM                                  13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX                 0x0010c5a0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c590 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX                  5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX             0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION                       0x0010c5a4 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c590 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX       0x0010c5a0 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT                0x20 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT                0x21 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_2_ORDER_INIT                0x34 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_3_ORDER_INIT                0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_4_ORDER_INIT                0x10 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_5_ORDER_INIT                0x11 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_6_ORDER_INIT                0x2c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_7_ORDER_INIT                0x22 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_9_ORDER_INIT                0x36 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_10_ORDER_INIT               0x37 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_11_ORDER_INIT               0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_12_ORDER_INIT               0x13 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_13_ORDER_INIT               0x2d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_14_ORDER_INIT               0x24 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_15_ORDER_INIT               0x25 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_16_ORDER_INIT               0x38 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_17_ORDER_INIT               0x39 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_18_ORDER_INIT               0x14 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_19_ORDER_INIT               0x15 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_20_ORDER_INIT               0x2e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_21_ORDER_INIT               0x26 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_22_ORDER_INIT               0x27 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_23_ORDER_INIT               0x3a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_24_ORDER_INIT               0x3b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_25_ORDER_INIT               0x16 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_26_ORDER_INIT               0x17 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_27_ORDER_INIT               0x2f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_28_ORDER_INIT               0x28 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_29_ORDER_INIT               0x29 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_30_ORDER_INIT               0x3c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_31_ORDER_INIT               0x3d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_32_ORDER_INIT               0x18 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_33_ORDER_INIT               0x19 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_34_ORDER_INIT               0x30 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_35_ORDER_INIT               0x2a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_36_ORDER_INIT               0x2b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_37_ORDER_INIT               0x3e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_38_ORDER_INIT               0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_39_ORDER_INIT               0x1a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_40_ORDER_INIT               0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_41_ORDER_INIT               0x31 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_42_ORDER_INIT               0x0a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_43_ORDER_INIT               0x04 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_44_ORDER_INIT               0x0b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_45_ORDER_INIT               0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_46_ORDER_INIT               0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_47_ORDER_INIT               0x32 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_48_ORDER_INIT               0x1e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_49_ORDER_INIT               0x33 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_50_ORDER_INIT               0x1c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_51_ORDER_INIT               0x1d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_52_ORDER_INIT               0x01 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_53_ORDER_INIT               0x02 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_54_ORDER_INIT               0x0c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_55_ORDER_INIT               0x06 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_56_ORDER_INIT               0x0d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_57_ORDER_INIT               0x07 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_58_ORDER_INIT               0x0e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_59_ORDER_INIT               0x08 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_60_ORDER_INIT               0x0f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_61_ORDER_INIT               0x09 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX                0x0010c528 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c538 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX                 5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX            0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1                      0x0010c52c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c538 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX      0x0010c528 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010c5a8 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c590 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN              0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX              0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION                       0x0010c5ac /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c590 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010c5a8 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010c530 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c538 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN             0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1                      0x0010c534 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c538 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010c530 /*       */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE                            0x0010c5b0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010c590 /*       */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC5_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6                                        0x0010c6ff:0x0010c600 /* RW--L */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010c670 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6                                          0x0010c618 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6__PRIV_LEVEL_MASK                         0x0010c670 /*       */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6_TEX                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6_TEX_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6_CROP                                           15:8 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6_CROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6_ZROP                                          23:16 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6_ZROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6_PE                                            31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_6_PE_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_7                                          0x0010c61c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_7__PRIV_LEVEL_MASK                         0x0010c670 /*       */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_7_SM                                              7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_7_SM_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_7_PES                                           31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC6_WEIGHT_7_PES_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_1                                          0x0010c63c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_1__PRIV_LEVEL_MASK                         0x0010c670 /*       */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_1_BA_IDLE_THRESHOLD                              31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_1_BA_IDLE_THRESHOLD_INIT                     0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2                                          0x0010c644 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2__PRIV_LEVEL_MASK                         0x0010c670 /*       */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_DATA                                          23:16 /* R--VF */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_SM_TEXAM                           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_SM_TEXDF                           0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_SM_SFE                             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_SM_SCTL                            0x3 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_SM_L1C                             0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_SM_TTU                             0x5 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_CROP                               0x6 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_ZROP                               0x7 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_PE                                 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CONFIG_2_BA_PLUGIN_ID_PES                                0x9 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_GPCCS_IDLE_FILTER                                 0x0010c64c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC6_GPCCS_IDLE_FILTER_VALUE                                 31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_GPCCS_IDLE_FILTER_VALUE_INIT                      0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_0                                           0x0010c650 /* RWE4R */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_1                                           0x0010c654 /* R--4R */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R--VF */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_1_CLK_DISABLE                                      5:5 /* R--VF */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_1_PRIV_IDLE                                        6:6 /* R--VF */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_1_CLK_FORCE                                        8:7 /* R--VF */
#define NV_PCHIPLET_PWR_GPC6_DEBUG_1_GATEABLE                                         9:9 /* R--VF */
#define NV_PCHIPLET_PWR_GPC6_CG1                                               0x0010c67c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC6_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_SM_HIGH_POWER_CTRL                                0x0010c68c /* RWE4R */
#define NV_PCHIPLET_PWR_GPC6_SM_HIGH_POWER_CTRL_DELAY                                15:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_SM_HIGH_POWER_CTRL_DELAY_INIT                         0x0000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_SM_HIGH_POWER_CTRL_DELAY_MAX                          0xffff /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_SM_HIGH_POWER_CTRL_EN                                  31:31 /* RWIVF */
#define NV_PCHIPLET_PWR_GPC6_SM_HIGH_POWER_CTRL_EN_DISABLE                            0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPC6_SM_HIGH_POWER_CTRL_EN_ENABLE                             0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010c690 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010c638 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_RAM_STAGGER_CONFIG                                0x0010c698 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010c690 /*       */
#define NV_PCHIPLET_PWR_GPC6_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_GROUP_TOP_ORDER                                   0x0010c69c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010c690 /*       */
#define NV_PCHIPLET_PWR_GPC6_GROUP_TOP_ORDER_GR_RAM                                  13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX                 0x0010c6a0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c690 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX                  5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX             0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION                       0x0010c6a4 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c690 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX       0x0010c6a0 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT                0x20 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT                0x21 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_2_ORDER_INIT                0x34 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_3_ORDER_INIT                0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_4_ORDER_INIT                0x10 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_5_ORDER_INIT                0x11 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_6_ORDER_INIT                0x2c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_7_ORDER_INIT                0x22 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_9_ORDER_INIT                0x36 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_10_ORDER_INIT               0x37 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_11_ORDER_INIT               0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_12_ORDER_INIT               0x13 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_13_ORDER_INIT               0x2d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_14_ORDER_INIT               0x24 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_15_ORDER_INIT               0x25 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_16_ORDER_INIT               0x38 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_17_ORDER_INIT               0x39 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_18_ORDER_INIT               0x14 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_19_ORDER_INIT               0x15 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_20_ORDER_INIT               0x2e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_21_ORDER_INIT               0x26 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_22_ORDER_INIT               0x27 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_23_ORDER_INIT               0x3a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_24_ORDER_INIT               0x3b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_25_ORDER_INIT               0x16 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_26_ORDER_INIT               0x17 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_27_ORDER_INIT               0x2f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_28_ORDER_INIT               0x28 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_29_ORDER_INIT               0x29 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_30_ORDER_INIT               0x3c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_31_ORDER_INIT               0x3d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_32_ORDER_INIT               0x18 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_33_ORDER_INIT               0x19 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_34_ORDER_INIT               0x30 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_35_ORDER_INIT               0x2a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_36_ORDER_INIT               0x2b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_37_ORDER_INIT               0x3e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_38_ORDER_INIT               0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_39_ORDER_INIT               0x1a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_40_ORDER_INIT               0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_41_ORDER_INIT               0x31 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_42_ORDER_INIT               0x0a /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_43_ORDER_INIT               0x04 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_44_ORDER_INIT               0x0b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_45_ORDER_INIT               0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_46_ORDER_INIT               0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_47_ORDER_INIT               0x32 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_48_ORDER_INIT               0x1e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_49_ORDER_INIT               0x33 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_50_ORDER_INIT               0x1c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_51_ORDER_INIT               0x1d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_52_ORDER_INIT               0x01 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_53_ORDER_INIT               0x02 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_54_ORDER_INIT               0x0c /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_55_ORDER_INIT               0x06 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_56_ORDER_INIT               0x0d /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_57_ORDER_INIT               0x07 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_58_ORDER_INIT               0x0e /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_59_ORDER_INIT               0x08 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_60_ORDER_INIT               0x0f /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_61_ORDER_INIT               0x09 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX                0x0010c628 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c638 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX                 5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX            0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1                      0x0010c62c /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c638 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX      0x0010c628 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010c6a8 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010c690 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN              0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX              0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION                       0x0010c6ac /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010c690 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010c6a8 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010c630 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010c638 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN             0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1                      0x0010c634 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010c638 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010c630 /*       */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE                            0x0010c6b0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010c690 /*       */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWE-V */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWEVF */
#define NV_PCHIPLET_PWR_GPC6_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS                                        0x0010e0ff:0x0010e000 /* RW--L */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010e070 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6                                          0x0010e018 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6__PRIV_LEVEL_MASK                         0x0010e070 /*       */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6_TEX                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6_TEX_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6_CROP                                           15:8 /* RWIUF */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6_CROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6_ZROP                                          23:16 /* RWIUF */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6_ZROP_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6_PE                                            31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_6_PE_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_7                                          0x0010e01c /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_7__PRIV_LEVEL_MASK                         0x0010e070 /*       */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_7_SM                                              7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_7_SM_ZERO                                        0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_7_PES                                           31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPCS_WEIGHT_7_PES_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_1                                          0x0010e03c /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_1__PRIV_LEVEL_MASK                         0x0010e070 /*       */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_1_BA_IDLE_THRESHOLD                              31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_1_BA_IDLE_THRESHOLD_INIT                     0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2                                          0x0010e044 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2__PRIV_LEVEL_MASK                         0x0010e070 /*       */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_DATA                                          23:16 /* R--VF */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_SM_TEXAM                           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_SM_TEXDF                           0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_SM_SFE                             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_SM_SCTL                            0x3 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_SM_L1C                             0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_SM_TTU                             0x5 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_CROP                               0x6 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_ZROP                               0x7 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_PE                                 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CONFIG_2_BA_PLUGIN_ID_PES                                0x9 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_GPCCS_IDLE_FILTER                                 0x0010e04c /* RWE4R */
#define NV_PCHIPLET_PWR_GPCS_GPCCS_IDLE_FILTER_VALUE                                 31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_GPCCS_IDLE_FILTER_VALUE_INIT                      0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_0                                           0x0010e050 /* RWE4R */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_1                                           0x0010e054 /* R--4R */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R--VF */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_1_CLK_DISABLE                                      5:5 /* R--VF */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_1_PRIV_IDLE                                        6:6 /* R--VF */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_1_CLK_FORCE                                        8:7 /* R--VF */
#define NV_PCHIPLET_PWR_GPCS_DEBUG_1_GATEABLE                                         9:9 /* R--VF */
#define NV_PCHIPLET_PWR_GPCS_CG1                                               0x0010e07c /* RWE4R */
#define NV_PCHIPLET_PWR_GPCS_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_SM_HIGH_POWER_CTRL                                0x0010e08c /* RWE4R */
#define NV_PCHIPLET_PWR_GPCS_SM_HIGH_POWER_CTRL_DELAY                                15:0 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_SM_HIGH_POWER_CTRL_DELAY_INIT                         0x0000 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_SM_HIGH_POWER_CTRL_DELAY_MAX                          0xffff /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_SM_HIGH_POWER_CTRL_EN                                  31:31 /* RWIVF */
#define NV_PCHIPLET_PWR_GPCS_SM_HIGH_POWER_CTRL_EN_DISABLE                            0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_GPCS_SM_HIGH_POWER_CTRL_EN_ENABLE                             0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010e090 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010e038 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_RAM_STAGGER_CONFIG                                0x0010e098 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010e090 /*       */
#define NV_PCHIPLET_PWR_GPCS_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_GROUP_TOP_ORDER                                   0x0010e09c /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010e090 /*       */
#define NV_PCHIPLET_PWR_GPCS_GROUP_TOP_ORDER_GR_RAM                                  13:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX                 0x0010e0a0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010e090 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX                  5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX             0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION                       0x0010e0a4 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010e090 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX       0x0010e0a0 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT                0x20 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT                0x21 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_2_ORDER_INIT                0x34 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_3_ORDER_INIT                0x35 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_4_ORDER_INIT                0x10 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_5_ORDER_INIT                0x11 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_6_ORDER_INIT                0x2c /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_7_ORDER_INIT                0x22 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_9_ORDER_INIT                0x36 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_10_ORDER_INIT               0x37 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_11_ORDER_INIT               0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_12_ORDER_INIT               0x13 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_13_ORDER_INIT               0x2d /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_14_ORDER_INIT               0x24 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_15_ORDER_INIT               0x25 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_16_ORDER_INIT               0x38 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_17_ORDER_INIT               0x39 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_18_ORDER_INIT               0x14 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_19_ORDER_INIT               0x15 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_20_ORDER_INIT               0x2e /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_21_ORDER_INIT               0x26 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_22_ORDER_INIT               0x27 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_23_ORDER_INIT               0x3a /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_24_ORDER_INIT               0x3b /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_25_ORDER_INIT               0x16 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_26_ORDER_INIT               0x17 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_27_ORDER_INIT               0x2f /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_28_ORDER_INIT               0x28 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_29_ORDER_INIT               0x29 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_30_ORDER_INIT               0x3c /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_31_ORDER_INIT               0x3d /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_32_ORDER_INIT               0x18 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_33_ORDER_INIT               0x19 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_34_ORDER_INIT               0x30 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_35_ORDER_INIT               0x2a /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_36_ORDER_INIT               0x2b /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_37_ORDER_INIT               0x3e /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_38_ORDER_INIT               0x3f /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_39_ORDER_INIT               0x1a /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_40_ORDER_INIT               0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_41_ORDER_INIT               0x31 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_42_ORDER_INIT               0x0a /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_43_ORDER_INIT               0x04 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_44_ORDER_INIT               0x0b /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_45_ORDER_INIT               0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_46_ORDER_INIT               0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_47_ORDER_INIT               0x32 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_48_ORDER_INIT               0x1e /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_49_ORDER_INIT               0x33 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_50_ORDER_INIT               0x1c /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_51_ORDER_INIT               0x1d /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_52_ORDER_INIT               0x01 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_53_ORDER_INIT               0x02 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_54_ORDER_INIT               0x0c /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_55_ORDER_INIT               0x06 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_56_ORDER_INIT               0x0d /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_57_ORDER_INIT               0x07 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_58_ORDER_INIT               0x0e /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_59_ORDER_INIT               0x08 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_60_ORDER_INIT               0x0f /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_61_ORDER_INIT               0x09 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX                0x0010e028 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010e038 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX                 5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX            0x3d /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1                      0x0010e02c /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010e038 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX      0x0010e028 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010e0a8 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010e090 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN              0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX              0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION                       0x0010e0ac /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010e090 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010e0a8 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x12 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x1b /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x05 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010e030 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010e038 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN             0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX             0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1                      0x0010e034 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010e038 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010e030 /*       */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE                            0x0010e0b0 /* RW-4R */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010e090 /*       */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWE-V */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWEVF */
#define NV_PCHIPLET_PWR_GPCS_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWE-V */
#define NV_PCHIPLET_PWR_FBP                                         0x0010c5ff:0x0010c000 /* RW--L */
#define NV_PCHIPLET_PWR_FBP0                                        0x0010d0ff:0x0010d000 /* RW--L */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010d070 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_WEIGHT_0                                          0x0010d000 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_WEIGHT_0__PRIV_LEVEL_MASK                         0x0010d070 /*       */
#define NV_PCHIPLET_PWR_FBP0_WEIGHT_0_FBPA                                          31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP0_WEIGHT_0_FBPA_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_WEIGHT_1                                          0x0010d004 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_WEIGHT_1__PRIV_LEVEL_MASK                         0x0010d070 /*       */
#define NV_PCHIPLET_PWR_FBP0_WEIGHT_1_LTC                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP0_WEIGHT_1_LTC_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_1                                          0x0010d03c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_1__PRIV_LEVEL_MASK                         0x0010d070 /*       */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD                        31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD_INIT               0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2                                          0x0010d044 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2__PRIV_LEVEL_MASK                         0x0010d070 /*       */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_DATA                                          23:16 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_BA_PLUGIN_ID_LTC                                0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_CONFIG_2_BA_PLUGIN_ID_FBPA                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_BECS_IDLE_FILTER                                  0x0010d04c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_BECS_IDLE_FILTER_VALUE                                  31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_BECS_IDLE_FILTER_VALUE_INIT                       0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_0                                           0x0010d050 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_1                                           0x0010d054 /* R--4R */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_1_CLK_FORCE                                        8:7 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_2                                           0x0010d058 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_2_SPARE                                           31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_DEBUG_2_SPARE_INIT                                0x00000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_CG1                                               0x0010d07c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010d080 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010d0a4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_RAM_STAGGER_CONFIG                                0x0010d088 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010d080 /*       */
#define NV_PCHIPLET_PWR_FBP0_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER                                   0x0010d08c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010d080 /*       */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER_GR_LOGIC                                 5:0 /*       */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER_GR_LOGIC_INIT                           0x00 /*       */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER_GR_RAM                                  14:8 /*       */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /*       */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER_DI_RAM                                 28:24 /*       */
#define NV_PCHIPLET_PWR_FBP0_GROUP_TOP_ORDER_DI_RAM_INIT                             0x00 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010d098 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010d080 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX             0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION                       0x0010d09c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010d080 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010d098 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x29 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x31 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x25 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_3_ORDER_INIT                0x2d /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_4_ORDER_INIT                0x28 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_5_ORDER_INIT                0x30 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_6_ORDER_INIT                0x24 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_7_ORDER_INIT                0x2c /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_9_ORDER_INIT                0x2b /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_10_ORDER_INIT               0x27 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_11_ORDER_INIT               0x2f /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_12_ORDER_INIT               0x22 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_13_ORDER_INIT               0x2a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_14_ORDER_INIT               0x26 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_15_ORDER_INIT               0x2e /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_16_ORDER_INIT               0x0a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_17_ORDER_INIT               0x11 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010d0b0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010d0a4 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX            0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1                      0x0010d0b4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010d0a4 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010d0b0 /*       */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE                            0x0010d0a0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010d080 /*       */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP0_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1                                        0x0010d1ff:0x0010d100 /* RW--L */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010d170 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_WEIGHT_0                                          0x0010d100 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_WEIGHT_0__PRIV_LEVEL_MASK                         0x0010d170 /*       */
#define NV_PCHIPLET_PWR_FBP1_WEIGHT_0_FBPA                                          31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP1_WEIGHT_0_FBPA_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_WEIGHT_1                                          0x0010d104 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_WEIGHT_1__PRIV_LEVEL_MASK                         0x0010d170 /*       */
#define NV_PCHIPLET_PWR_FBP1_WEIGHT_1_LTC                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP1_WEIGHT_1_LTC_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_1                                          0x0010d13c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_1__PRIV_LEVEL_MASK                         0x0010d170 /*       */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD                        31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD_INIT               0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2                                          0x0010d144 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2__PRIV_LEVEL_MASK                         0x0010d170 /*       */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_DATA                                          23:16 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_BA_PLUGIN_ID_LTC                                0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_CONFIG_2_BA_PLUGIN_ID_FBPA                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_BECS_IDLE_FILTER                                  0x0010d14c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_BECS_IDLE_FILTER_VALUE                                  31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_BECS_IDLE_FILTER_VALUE_INIT                       0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_0                                           0x0010d150 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_1                                           0x0010d154 /* R--4R */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_1_CLK_FORCE                                        8:7 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_2                                           0x0010d158 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_2_SPARE                                           31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_DEBUG_2_SPARE_INIT                                0x00000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_CG1                                               0x0010d17c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010d180 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010d1a4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_RAM_STAGGER_CONFIG                                0x0010d188 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010d180 /*       */
#define NV_PCHIPLET_PWR_FBP1_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER                                   0x0010d18c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010d180 /*       */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER_GR_LOGIC                                 5:0 /*       */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER_GR_LOGIC_INIT                           0x00 /*       */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER_GR_RAM                                  14:8 /*       */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /*       */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER_DI_RAM                                 28:24 /*       */
#define NV_PCHIPLET_PWR_FBP1_GROUP_TOP_ORDER_DI_RAM_INIT                             0x00 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010d198 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010d180 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX             0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION                       0x0010d19c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010d180 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010d198 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x29 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x31 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x25 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_3_ORDER_INIT                0x2d /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_4_ORDER_INIT                0x28 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_5_ORDER_INIT                0x30 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_6_ORDER_INIT                0x24 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_7_ORDER_INIT                0x2c /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_9_ORDER_INIT                0x2b /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_10_ORDER_INIT               0x27 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_11_ORDER_INIT               0x2f /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_12_ORDER_INIT               0x22 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_13_ORDER_INIT               0x2a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_14_ORDER_INIT               0x26 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_15_ORDER_INIT               0x2e /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_16_ORDER_INIT               0x0a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_17_ORDER_INIT               0x11 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010d1b0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010d1a4 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX            0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1                      0x0010d1b4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010d1a4 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010d1b0 /*       */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE                            0x0010d1a0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010d180 /*       */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP1_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2                                        0x0010d2ff:0x0010d200 /* RW--L */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010d270 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_WEIGHT_0                                          0x0010d200 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_WEIGHT_0__PRIV_LEVEL_MASK                         0x0010d270 /*       */
#define NV_PCHIPLET_PWR_FBP2_WEIGHT_0_FBPA                                          31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP2_WEIGHT_0_FBPA_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_WEIGHT_1                                          0x0010d204 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_WEIGHT_1__PRIV_LEVEL_MASK                         0x0010d270 /*       */
#define NV_PCHIPLET_PWR_FBP2_WEIGHT_1_LTC                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP2_WEIGHT_1_LTC_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_1                                          0x0010d23c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_1__PRIV_LEVEL_MASK                         0x0010d270 /*       */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD                        31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD_INIT               0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2                                          0x0010d244 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2__PRIV_LEVEL_MASK                         0x0010d270 /*       */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_DATA                                          23:16 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_BA_PLUGIN_ID_LTC                                0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_CONFIG_2_BA_PLUGIN_ID_FBPA                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_BECS_IDLE_FILTER                                  0x0010d24c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_BECS_IDLE_FILTER_VALUE                                  31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_BECS_IDLE_FILTER_VALUE_INIT                       0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_0                                           0x0010d250 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_1                                           0x0010d254 /* R--4R */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_1_CLK_FORCE                                        8:7 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_2                                           0x0010d258 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_2_SPARE                                           31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_DEBUG_2_SPARE_INIT                                0x00000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_CG1                                               0x0010d27c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010d280 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010d2a4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_RAM_STAGGER_CONFIG                                0x0010d288 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010d280 /*       */
#define NV_PCHIPLET_PWR_FBP2_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER                                   0x0010d28c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010d280 /*       */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER_GR_LOGIC                                 5:0 /*       */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER_GR_LOGIC_INIT                           0x00 /*       */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER_GR_RAM                                  14:8 /*       */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /*       */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER_DI_RAM                                 28:24 /*       */
#define NV_PCHIPLET_PWR_FBP2_GROUP_TOP_ORDER_DI_RAM_INIT                             0x00 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010d298 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010d280 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX             0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION                       0x0010d29c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010d280 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010d298 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x29 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x31 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x25 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_3_ORDER_INIT                0x2d /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_4_ORDER_INIT                0x28 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_5_ORDER_INIT                0x30 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_6_ORDER_INIT                0x24 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_7_ORDER_INIT                0x2c /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_9_ORDER_INIT                0x2b /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_10_ORDER_INIT               0x27 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_11_ORDER_INIT               0x2f /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_12_ORDER_INIT               0x22 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_13_ORDER_INIT               0x2a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_14_ORDER_INIT               0x26 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_15_ORDER_INIT               0x2e /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_16_ORDER_INIT               0x0a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_17_ORDER_INIT               0x11 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010d2b0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010d2a4 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX            0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1                      0x0010d2b4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010d2a4 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010d2b0 /*       */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE                            0x0010d2a0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010d280 /*       */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP2_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3                                        0x0010d3ff:0x0010d300 /* RW--L */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010d370 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_WEIGHT_0                                          0x0010d300 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_WEIGHT_0__PRIV_LEVEL_MASK                         0x0010d370 /*       */
#define NV_PCHIPLET_PWR_FBP3_WEIGHT_0_FBPA                                          31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP3_WEIGHT_0_FBPA_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_WEIGHT_1                                          0x0010d304 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_WEIGHT_1__PRIV_LEVEL_MASK                         0x0010d370 /*       */
#define NV_PCHIPLET_PWR_FBP3_WEIGHT_1_LTC                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP3_WEIGHT_1_LTC_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_1                                          0x0010d33c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_1__PRIV_LEVEL_MASK                         0x0010d370 /*       */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD                        31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD_INIT               0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2                                          0x0010d344 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2__PRIV_LEVEL_MASK                         0x0010d370 /*       */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_DATA                                          23:16 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_BA_PLUGIN_ID_LTC                                0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_CONFIG_2_BA_PLUGIN_ID_FBPA                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_BECS_IDLE_FILTER                                  0x0010d34c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_BECS_IDLE_FILTER_VALUE                                  31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_BECS_IDLE_FILTER_VALUE_INIT                       0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_0                                           0x0010d350 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_1                                           0x0010d354 /* R--4R */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_1_CLK_FORCE                                        8:7 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_2                                           0x0010d358 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_2_SPARE                                           31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_DEBUG_2_SPARE_INIT                                0x00000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_CG1                                               0x0010d37c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010d380 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010d3a4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_RAM_STAGGER_CONFIG                                0x0010d388 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010d380 /*       */
#define NV_PCHIPLET_PWR_FBP3_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER                                   0x0010d38c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010d380 /*       */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER_GR_LOGIC                                 5:0 /*       */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER_GR_LOGIC_INIT                           0x00 /*       */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER_GR_RAM                                  14:8 /*       */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /*       */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER_DI_RAM                                 28:24 /*       */
#define NV_PCHIPLET_PWR_FBP3_GROUP_TOP_ORDER_DI_RAM_INIT                             0x00 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010d398 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010d380 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX             0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION                       0x0010d39c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010d380 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010d398 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x29 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x31 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x25 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_3_ORDER_INIT                0x2d /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_4_ORDER_INIT                0x28 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_5_ORDER_INIT                0x30 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_6_ORDER_INIT                0x24 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_7_ORDER_INIT                0x2c /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_9_ORDER_INIT                0x2b /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_10_ORDER_INIT               0x27 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_11_ORDER_INIT               0x2f /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_12_ORDER_INIT               0x22 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_13_ORDER_INIT               0x2a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_14_ORDER_INIT               0x26 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_15_ORDER_INIT               0x2e /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_16_ORDER_INIT               0x0a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_17_ORDER_INIT               0x11 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010d3b0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010d3a4 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX            0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1                      0x0010d3b4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010d3a4 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010d3b0 /*       */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE                            0x0010d3a0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010d380 /*       */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP3_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4                                        0x0010d4ff:0x0010d400 /* RW--L */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010d470 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_WEIGHT_0                                          0x0010d400 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_WEIGHT_0__PRIV_LEVEL_MASK                         0x0010d470 /*       */
#define NV_PCHIPLET_PWR_FBP4_WEIGHT_0_FBPA                                          31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP4_WEIGHT_0_FBPA_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_WEIGHT_1                                          0x0010d404 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_WEIGHT_1__PRIV_LEVEL_MASK                         0x0010d470 /*       */
#define NV_PCHIPLET_PWR_FBP4_WEIGHT_1_LTC                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP4_WEIGHT_1_LTC_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_1                                          0x0010d43c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_1__PRIV_LEVEL_MASK                         0x0010d470 /*       */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD                        31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD_INIT               0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2                                          0x0010d444 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2__PRIV_LEVEL_MASK                         0x0010d470 /*       */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_DATA                                          23:16 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_BA_PLUGIN_ID_LTC                                0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_CONFIG_2_BA_PLUGIN_ID_FBPA                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_BECS_IDLE_FILTER                                  0x0010d44c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_BECS_IDLE_FILTER_VALUE                                  31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_BECS_IDLE_FILTER_VALUE_INIT                       0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_0                                           0x0010d450 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_1                                           0x0010d454 /* R--4R */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_1_CLK_FORCE                                        8:7 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_2                                           0x0010d458 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_2_SPARE                                           31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_DEBUG_2_SPARE_INIT                                0x00000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_CG1                                               0x0010d47c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010d480 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010d4a4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_RAM_STAGGER_CONFIG                                0x0010d488 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010d480 /*       */
#define NV_PCHIPLET_PWR_FBP4_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER                                   0x0010d48c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010d480 /*       */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER_GR_LOGIC                                 5:0 /*       */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER_GR_LOGIC_INIT                           0x00 /*       */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER_GR_RAM                                  14:8 /*       */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /*       */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER_DI_RAM                                 28:24 /*       */
#define NV_PCHIPLET_PWR_FBP4_GROUP_TOP_ORDER_DI_RAM_INIT                             0x00 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010d498 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010d480 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX             0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION                       0x0010d49c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010d480 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010d498 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x29 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x31 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x25 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_3_ORDER_INIT                0x2d /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_4_ORDER_INIT                0x28 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_5_ORDER_INIT                0x30 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_6_ORDER_INIT                0x24 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_7_ORDER_INIT                0x2c /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_9_ORDER_INIT                0x2b /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_10_ORDER_INIT               0x27 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_11_ORDER_INIT               0x2f /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_12_ORDER_INIT               0x22 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_13_ORDER_INIT               0x2a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_14_ORDER_INIT               0x26 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_15_ORDER_INIT               0x2e /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_16_ORDER_INIT               0x0a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_17_ORDER_INIT               0x11 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010d4b0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010d4a4 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX            0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1                      0x0010d4b4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010d4a4 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010d4b0 /*       */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE                            0x0010d4a0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010d480 /*       */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP4_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5                                        0x0010d5ff:0x0010d500 /* RW--L */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010d570 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_WEIGHT_0                                          0x0010d500 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_WEIGHT_0__PRIV_LEVEL_MASK                         0x0010d570 /*       */
#define NV_PCHIPLET_PWR_FBP5_WEIGHT_0_FBPA                                          31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP5_WEIGHT_0_FBPA_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_WEIGHT_1                                          0x0010d504 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_WEIGHT_1__PRIV_LEVEL_MASK                         0x0010d570 /*       */
#define NV_PCHIPLET_PWR_FBP5_WEIGHT_1_LTC                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP5_WEIGHT_1_LTC_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_1                                          0x0010d53c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_1__PRIV_LEVEL_MASK                         0x0010d570 /*       */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD                        31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD_INIT               0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2                                          0x0010d544 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2__PRIV_LEVEL_MASK                         0x0010d570 /*       */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_DATA                                          23:16 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_BA_PLUGIN_ID_LTC                                0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_CONFIG_2_BA_PLUGIN_ID_FBPA                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_BECS_IDLE_FILTER                                  0x0010d54c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_BECS_IDLE_FILTER_VALUE                                  31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_BECS_IDLE_FILTER_VALUE_INIT                       0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_0                                           0x0010d550 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_1                                           0x0010d554 /* R--4R */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_1_CLK_FORCE                                        8:7 /* R-XVF */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_2                                           0x0010d558 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_2_SPARE                                           31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_DEBUG_2_SPARE_INIT                                0x00000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_CG1                                               0x0010d57c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010d580 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010d5a4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_RAM_STAGGER_CONFIG                                0x0010d588 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010d580 /*       */
#define NV_PCHIPLET_PWR_FBP5_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER                                   0x0010d58c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010d580 /*       */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER_GR_LOGIC                                 5:0 /*       */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER_GR_LOGIC_INIT                           0x00 /*       */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER_GR_RAM                                  14:8 /*       */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /*       */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER_DI_RAM                                 28:24 /*       */
#define NV_PCHIPLET_PWR_FBP5_GROUP_TOP_ORDER_DI_RAM_INIT                             0x00 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010d598 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010d580 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX             0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION                       0x0010d59c /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010d580 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010d598 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x29 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x31 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x25 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_3_ORDER_INIT                0x2d /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_4_ORDER_INIT                0x28 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_5_ORDER_INIT                0x30 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_6_ORDER_INIT                0x24 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_7_ORDER_INIT                0x2c /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_9_ORDER_INIT                0x2b /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_10_ORDER_INIT               0x27 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_11_ORDER_INIT               0x2f /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_12_ORDER_INIT               0x22 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_13_ORDER_INIT               0x2a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_14_ORDER_INIT               0x26 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_15_ORDER_INIT               0x2e /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_16_ORDER_INIT               0x0a /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_17_ORDER_INIT               0x11 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010d5b0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010d5a4 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX            0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1                      0x0010d5b4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010d5a4 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010d5b0 /*       */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE                            0x0010d5a0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010d580 /*       */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWI-V */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBP5_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS                                        0x0010e1ff:0x0010e100 /* RW--L */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK                      0x0010e170 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION             3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0      0:0 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1      1:1 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2      2:2 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3      3:3 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION            7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0     4:4 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1     5:5 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2     6:6 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3     7:7 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON   0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL       10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL      11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE             31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_WEIGHT_0                                          0x0010e100 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_WEIGHT_0__PRIV_LEVEL_MASK                         0x0010e170 /*       */
#define NV_PCHIPLET_PWR_FBPS_WEIGHT_0_FBPA                                          31:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBPS_WEIGHT_0_FBPA_ZERO                                      0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_WEIGHT_1                                          0x0010e104 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_WEIGHT_1__PRIV_LEVEL_MASK                         0x0010e170 /*       */
#define NV_PCHIPLET_PWR_FBPS_WEIGHT_1_LTC                                             7:0 /* RWIUF */
#define NV_PCHIPLET_PWR_FBPS_WEIGHT_1_LTC_ZERO                                       0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_1                                          0x0010e13c /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_1__PRIV_LEVEL_MASK                         0x0010e170 /*       */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_1_BA_ENABLE                                       0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_1_BA_ENABLE_NO                                    0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_1_BA_ENABLE_YES                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD                        31:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_1_BA_IDLE_THRESHOLD_NVVDD_INIT               0x000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2                                          0x0010e144 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2__PRIV_LEVEL_MASK                         0x0010e170 /*       */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_MODE                                            1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_MODE_ERR                                        0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_MODE_ELCG_CTR                                   0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_DATA                                          23:16 /* R-XVF */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_CTR_CLEAR                                     24:24 /* RWIUF */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_CTR_CLEAR_INIT                                  0x0 /* R-I-V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_CTR_CLEAR_DONE                                  0x0 /* R---V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_CTR_CLEAR_NOT_DONE                              0x1 /* R---V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_CTR_CLEAR_TRIGGER                               0x1 /* -W--T */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_BA_PLUGIN_ID                                  31:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_BA_PLUGIN_ID_LTC                                0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_CONFIG_2_BA_PLUGIN_ID_FBPA                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_BECS_IDLE_FILTER                                  0x0010e14c /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_BECS_IDLE_FILTER_VALUE                                  31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_BECS_IDLE_FILTER_VALUE_INIT                       0x00000010 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_0                                           0x0010e150 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_0_ENG_SM                                           0:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_0_ENG_SM_DEFAULT                                   0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_0_ENG_SM_RUN_ALWAYS                                0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_0_FAST_TIMER_MODE                                  4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_0_FAST_TIMER_MODE_OFF                              0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_0_FAST_TIMER_MODE_ON                               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_1                                           0x0010e154 /* R--4R */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_1_GTCTL_SERVER_STATE                               4:2 /* R-XVF */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_1_CLK_FORCE                                        8:7 /* R-XVF */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_2                                           0x0010e158 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_2_SPARE                                           31:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_DEBUG_2_SPARE_INIT                                0x00000000 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_CG1                                               0x0010e17c /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_CG1_SLCG                                                 2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_CG1_SLCG_ENABLED                                         0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_CG1_SLCG_DISABLED                                        0x7 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_CG1_SLCG__PROD                                           0x4 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK                     0x0010e180 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0     0:0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1     1:1 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2     2:2 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3     3:3 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION           7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0    4:4 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1    5:5 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2    6:6 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3    7:7 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION             8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON  0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION            9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL      10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL     11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE            31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK                 0x0010e1a4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION        3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION       7:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION         8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION        9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL  10:10 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE        31:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_RAM_STAGGER_CONFIG                                0x0010e188 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK               0x0010e180 /*       */
#define NV_PCHIPLET_PWR_FBPS_RAM_STAGGER_CONFIG_ZONE_DELAY                            3:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT                       0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_RAM_STAGGER_CONFIG_FAST_MODE                             4:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_RAM_STAGGER_CONFIG_FAST_MODE_EN                          0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_RAM_STAGGER_CONFIG_FAST_MODE_DIS                         0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_RAM_STAGGER_CONFIG_RET_EN_DELAY                         13:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT                    0x03 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER                                   0x0010e18c /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER__PRIV_LEVEL_MASK                  0x0010e180 /*       */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER_GR_LOGIC                                 5:0 /*       */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER_GR_LOGIC_INIT                           0x00 /*       */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER_GR_RAM                                  14:8 /*       */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER_GR_RAM_INIT                             0x3f /*       */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER_MS_RAM                                 21:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER_MS_RAM_INIT                             0x35 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER_DI_RAM                                 28:24 /*       */
#define NV_PCHIPLET_PWR_FBPS_GROUP_TOP_ORDER_DI_RAM_INIT                             0x00 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX                 0x0010e198 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010e180 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX                  4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN             0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX             0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR               8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED      0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED       0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR              9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION                       0x0010e19c /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK      0x0010e180 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX       0x0010e198 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_ORDER                        5:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT                0x29 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT                0x31 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT                0x25 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_3_ORDER_INIT                0x2d /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_4_ORDER_INIT                0x28 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_5_ORDER_INIT                0x30 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_6_ORDER_INIT                0x24 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_7_ORDER_INIT                0x2c /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_8_ORDER_INIT                0x23 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_9_ORDER_INIT                0x2b /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_10_ORDER_INIT               0x27 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_11_ORDER_INIT               0x2f /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_12_ORDER_INIT               0x22 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_13_ORDER_INIT               0x2a /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_14_ORDER_INIT               0x26 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_15_ORDER_INIT               0x2e /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_16_ORDER_INIT               0x0a /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_17_ORDER_INIT               0x11 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL               9:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING     0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING    0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE   0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX                0x0010e1b0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010e1a4 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX                 4:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN            0x00 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX            0x11 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR              8:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED     0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED      0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR             9:9 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED    0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED     0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1                      0x0010e1b4 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK     0x0010e1a4 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX      0x0010e1b0 /*       */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0                    1:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1                    3:2 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON           0x0 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG               0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2                    5:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3                    7:6 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON           0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG               0x1 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG                0x2 /* RW--V */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE                            0x0010e1a0 /* RW-4R */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK           0x0010e180 /*       */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX                       2:0 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT                  0x0 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX                       6:4 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT                  0x1 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX                      10:8 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT                  0x2 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX                     14:12 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT                  0x3 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX                     18:16 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT                  0x4 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX                     22:20 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT                  0x5 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX                     26:24 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT                  0x6 /* RWI-V */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX                     30:28 /* RWIVF */
#define NV_PCHIPLET_PWR_FBPS_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT                  0x7 /* RWI-V */
#endif // __ga102_dev_chiplet_pwr_h__