/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_bus_h__ #define __ga102_dev_bus_h__ /* This file is autogenerated. Do not edit */ #define NV_MEMORY 0xFFFFFFFF:0x00000000 /* RW--D */ #define NV_IO 0xFFFFFFFF:0x00000000 /* RW--D */ #define NV_EXPROM 0x0007FFFF:0x00000000 /* R---D */ #define NV_SPACE 0x01FFFFFF:0x00000000 /* RW--D */ #define NV_RSPACE 0x00FFFFFF:0x00000000 /* RW--D */ #define NV_MSPACE 0x1FFFFFFF:0x00000000 /* RW--D */ #define NV_ISPACE 0x01FFFFFF:0x00000000 /* RW--D */ #define NV_IOBAR 0x0000007F:0x00000000 /* RW--D */ #define NV_IFB 0x00060FFF:0x00060000 /* RW--D */ #define NV_PRMIO 0x00007FFF:0x00007000 /* RW--D */ #define NV_PBUS 0x00001fff:0x00001000 /* RW--D */ #define NV_IOBAR_CNTRL0 0x00000000 /* RW-4R */ #define NV_IOBAR_CNTRL0_ENABLE 0:0 /* RWIVF */ #define NV_IOBAR_CNTRL0_ENABLE_OFF 0x00000000 /* RW--V */ #define NV_IOBAR_CNTRL0_ENABLE_ON 0x00000001 /* RWI-V */ #define NV_IOBAR_CNTRL0_ACCESS_ID 31:1 /* R-IVF */ #define NV_IOBAR_CNTRL0_ACCESS_ID_VAL 0x1234fedc /* R-I-V */ #define NV_IOBAR_CNTRL1 0x00000004 /* RW-4R */ #define NV_IOBAR_CNTRL1_TRIG_MODE 0:0 /* RWIVF */ #define NV_IOBAR_CNTRL1_TRIG_MODE_OFF 0x00000000 /* RWI-V */ #define NV_IOBAR_CNTRL1_TRIG_MODE_ON 0x00000001 /* RW--V */ #define NV_IOBAR_CNTRL1_RSVD0 31:1 /* RWIVF */ #define NV_IOBAR_CNTRL1_RSVD0_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_PRIV_INDEX 0x00000008 /* RW-4R */ #define NV_IOBAR_PRIV_INDEX_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_PRIV_INDEX_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_PRIV_DATA 0x0000000c /* RW-4R */ #define NV_IOBAR_PRIV_DATA_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_PRIV_DATA_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_FBI_INDEX 0x00000010 /* RW-4R */ #define NV_IOBAR_FBI_INDEX_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_FBI_INDEX_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_FBI_DATA 0x00000014 /* RW-4R */ #define NV_IOBAR_FBI_DATA_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_FBI_DATA_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_INST_INDEX 0x00000018 /* RW-4R */ #define NV_IOBAR_INST_INDEX_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_INST_INDEX_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_INST_DATA 0x0000001c /* RW-4R */ #define NV_IOBAR_INST_DATA_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_INST_DATA_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_CNTRL_RSVD 0x00000020 /* RW-4R */ #define NV_IOBAR_CNTRL_RSVD_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_CNTRL_RSVD_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_RSVD0 0x00000024 /* RW-4R */ #define NV_IOBAR_RSVD0_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_RSVD0_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_RSVD1 0x00000028 /* RW-4R */ #define NV_IOBAR_RSVD1_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_RSVD1_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_RSVD2 0x0000002c /* RW-4R */ #define NV_IOBAR_RSVD2_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_RSVD2_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_RSVD3 0x00000030 /* RW-4R */ #define NV_IOBAR_RSVD3_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_RSVD3_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_RSVD4 0x00000034 /* RW-4R */ #define NV_IOBAR_RSVD4_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_RSVD4_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_RSVD5 0x00000038 /* RW-4R */ #define NV_IOBAR_RSVD5_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_RSVD5_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_RSVD6 0x0000003c /* RW-4R */ #define NV_IOBAR_RSVD6_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_RSVD6_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH0 0x00000040 /* RW-4R */ #define NV_IOBAR_SCRATCH0_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH0_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH1 0x00000044 /* RW-4R */ #define NV_IOBAR_SCRATCH1_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH1_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH2 0x00000048 /* RW-4R */ #define NV_IOBAR_SCRATCH2_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH2_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH3 0x0000004c /* RW-4R */ #define NV_IOBAR_SCRATCH3_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH3_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH4 0x00000050 /* RW-4R */ #define NV_IOBAR_SCRATCH4_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH4_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH5 0x00000054 /* RW-4R */ #define NV_IOBAR_SCRATCH5_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH5_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH6 0x00000058 /* RW-4R */ #define NV_IOBAR_SCRATCH6_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH6_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH7 0x0000005c /* RW-4R */ #define NV_IOBAR_SCRATCH7_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH7_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH8 0x00000060 /* RW-4R */ #define NV_IOBAR_SCRATCH8_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH8_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCH9 0x00000064 /* RW-4R */ #define NV_IOBAR_SCRATCH9_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCH9_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCHA 0x00000068 /* RW-4R */ #define NV_IOBAR_SCRATCHA_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCHA_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCHB 0x0000006c /* RW-4R */ #define NV_IOBAR_SCRATCHB_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCHB_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCHC 0x00000070 /* RW-4R */ #define NV_IOBAR_SCRATCHC_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCHC_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCHD 0x00000074 /* RW-4R */ #define NV_IOBAR_SCRATCHD_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCHD_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCHE 0x00000078 /* RW-4R */ #define NV_IOBAR_SCRATCHE_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCHE_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_IOBAR_SCRATCHF 0x0000007c /* RW-4R */ #define NV_IOBAR_SCRATCHF_VALUE 31:0 /* RWIVF */ #define NV_IOBAR_SCRATCHF_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK 0x00001630 /* RW-4R */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RWI-V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PBUS_DEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PBUS_DEBUG_0 0x00001080 /* RW-4R */ #define NV_PBUS_DEBUG_0_SPARE 31:0 /* RWIVF */ #define NV_PBUS_DEBUG_0_SPARE_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_DEBUG_2 0x00001088 /* RW-4R */ #define NV_PBUS_DEBUG_2__PRIV_LEVEL_MASK 0x00001630 /* */ #define NV_PBUS_DEBUG_2_PRI_TO_INTR 23:23 /* RWIVF */ #define NV_PBUS_DEBUG_2_PRI_TO_INTR_ENABLED 0x00000000 /* RWI-V */ #define NV_PBUS_DEBUG_2_PRI_TO_INTR_DISABLED 0x00000001 /* RW--V */ #define NV_PBUS_DEBUG_3 0x0000108C /* RW-4R */ #define NV_PBUS_DEBUG_3__PRIV_LEVEL_MASK 0x00001630 /* */ #define NV_PBUS_DEBUG_3_IFF_IFR_RESTART 11:11 /* RWIVF */ #define NV_PBUS_DEBUG_3_IFF_IFR_RESTART_INACTIVE 0x00000000 /* R-I-V */ #define NV_PBUS_DEBUG_3_IFF_IFR_RESTART_ACTIVE 0x00000001 /* R---V */ #define NV_PBUS_DEBUG_3_IFF_IFR_RESTART_TRIGGER 0x00000001 /* -W--T */ #define NV_PBUS_DEBUG_4 0x00001098 /* RW-4R */ #define NV_PBUS_DEBUG_4_STOP_IFR_ON_PARITY_FAILURE 22:22 /* RWIVF */ #define NV_PBUS_DEBUG_4_STOP_IFR_ON_PARITY_FAILURE_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_DEBUG_4_STOP_IFR_ON_PARITY_FAILURE_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_DEBUG_10 0x00001544 /* RW-4R */ #define NV_PBUS_DEBUG_10_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_DEBUG_10_SCRATCH_DATA 0x00000000 /* RWI-V */ #define NV_PBUS_DEBUG_11 0x00001548 /* RW-4R */ #define NV_PBUS_DEBUG_11_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_DEBUG_11_SCRATCH_DATA 0x00000000 /* RWI-V */ #define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */ #define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */ #define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */ #define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */ #define NV_PBUS_VBIOS_SCRATCH(i) (0x00001400+(i)*4) /* */ #define NV_PBUS_VBIOS_SCRATCH__SIZE_1 16 /* */ #define NV_PBUS_VBIOS_SCRATCH_FIELD 31:0 /* */ #define NV_PBUS_VBIOS_SCRATCH_FIELD_INIT 0x00000000 /* */ #define NV_PBUS_EMULATION_REV0 0x00001070 /* R--4R */ #define NV_PBUS_EMULATION_REV0_VALUE 31:0 /* R-IVF */ #define NV_PBUS_EMULATION_REV0_VALUE_HARDWARE 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_REV1 0x00001074 /* R--4R */ #define NV_PBUS_EMULATION_REV1_VALUE 31:0 /* R-IVF */ #define NV_PBUS_EMULATION_REV1_VALUE_HARDWARE 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0 0x00001078 /* R--4R */ #define NV_PBUS_EMULATION_STUB0_CHUNK0 0:0 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK0_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK0_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK1 1:1 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK1_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK1_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK2 2:2 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK2_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK2_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK3 3:3 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK3_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK3_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK4 4:4 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK4_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK4_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK5 5:5 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK5_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK5_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK6 6:6 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK6_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK6_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK7 7:7 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK7_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK7_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK8 8:8 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK8_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK8_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK9 9:9 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK9_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK9_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK10 10:10 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK10_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK10_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK11 11:11 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK11_REMOVED 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK11_PRESENT 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK12 12:12 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK12_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK12_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK13 13:13 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK13_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK13_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK14 14:14 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK14_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK14_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK15 15:15 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK15_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK15_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK16 16:16 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK16_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK16_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK17 17:17 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK17_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK17_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK18 18:18 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK18_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK18_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK19 19:19 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK19_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK19_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK20 20:20 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK20_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK20_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK21 21:21 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK21_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK21_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK22 22:22 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK22_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK22_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK23 23:23 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK23_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK23_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK24 24:24 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK24_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK24_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK25 25:25 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK25_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK25_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK26 26:26 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK26_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK26_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK27 27:27 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK27_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK27_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK28 28:28 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK28_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK28_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK29 29:29 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK29_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK29_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK30 30:30 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK30_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK30_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_CHUNK31 31:31 /* R-IVF */ #define NV_PBUS_EMULATION_STUB0_CHUNK31_PRESENT 0x00000000 /* R-I-V */ #define NV_PBUS_EMULATION_STUB0_CHUNK31_REMOVED 0x00000001 /* R---V */ #define NV_PBUS_EMULATION_STUB0_GR 0:0 /* */ #define NV_PBUS_EMULATION_STUB0_GR_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_GR_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_DISP 1:1 /* */ #define NV_PBUS_EMULATION_STUB0_DISP_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_DISP_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_PMU 2:2 /* */ #define NV_PBUS_EMULATION_STUB0_PMU_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_PMU_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_FIFO 3:3 /* */ #define NV_PBUS_EMULATION_STUB0_FIFO_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_FIFO_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_INTR 4:4 /* */ #define NV_PBUS_EMULATION_STUB0_INTR_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_INTR_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_CLK 5:5 /* */ #define NV_PBUS_EMULATION_STUB0_CLK_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_CLK_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_PWR 6:6 /* */ #define NV_PBUS_EMULATION_STUB0_PWR_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_PWR_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_DPAUX 7:7 /* */ #define NV_PBUS_EMULATION_STUB0_DPAUX_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_DPAUX_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_FB 8:8 /* */ #define NV_PBUS_EMULATION_STUB0_FB_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_FB_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_TMR 9:9 /* */ #define NV_PBUS_EMULATION_STUB0_TMR_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_TMR_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_MSENC 10:10 /* */ #define NV_PBUS_EMULATION_STUB0_MSENC_PRESENT 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_MSENC_REMOVED 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_ELPG 11:11 /* */ #define NV_PBUS_EMULATION_STUB0_ELPG_REMOVED 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_ELPG_PRESENT 0x00000001 /* */ #define NV_PBUS_EMULATION_STUB0_GSP 12:12 /* */ #define NV_PBUS_EMULATION_STUB0_GSP_REMOVED 0x00000000 /* */ #define NV_PBUS_EMULATION_STUB0_GSP_PRESENT 0x00000001 /* */ #define NV_PBUS_NULL 0x0000109C /* C--4R */ #define NV_PBUS_NULL_FIELD 31:0 /* C--VF */ #define NV_PBUS_NULL_FIELD_ZERO 0x0 /* C---V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK 0x00001634 /* RW-4R */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "host_pbus_access" /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE_FUSE0 12 /* RWI-V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE_FUSE1 8 /* RW--V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PBUS_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PBUS_ACCESS 0x00001620 /* RW-4R */ #define NV_PBUS_ACCESS__PRIV_LEVEL_MASK 0x00001634 /* */ #define NV_PBUS_ACCESS_DEVICE(i) (i):(i) /* */ #define NV_PBUS_ACCESS_DEVICE__SIZE_1 32 /* */ #define NV_PBUS_ACCESS_DEVICE_ENABLED 0x00000001 /* */ #define NV_PBUS_ACCESS_DEVICE_DISABLED 0x00000000 /* */ #define NV_PBUS_ACCESS_XVE_P 0:0 /* RWIVF */ #define NV_PBUS_ACCESS_XVE_P_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_XVE_P_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_XVE_N 1:1 /* RWIVF */ #define NV_PBUS_ACCESS_XVE_N_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_XVE_N_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_PMU 20:20 /* RWIVF */ #define NV_PBUS_ACCESS_PMU_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_PMU_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_JTAG 5:5 /* RWIVF */ #define NV_PBUS_ACCESS_JTAG_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_JTAG_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_I2C 7:7 /* RWIVF */ #define NV_PBUS_ACCESS_I2C_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_I2C_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_ROM 21:21 /* RWIVF */ #define NV_PBUS_ACCESS_ROM_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_ROM_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_SEC_DEVICE_INFO 2:2 /* RWIVF */ #define NV_PBUS_ACCESS_SEC_DEVICE_INFO_RESET 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_NVDEC0_DEVICE_INFO 3:3 /* RWIVF */ #define NV_PBUS_ACCESS_NVDEC0_DEVICE_INFO_RESET 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_NVDEC1_DEVICE_INFO 4:4 /* RWIVF */ #define NV_PBUS_ACCESS_NVDEC1_DEVICE_INFO_RESET 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_GSP 14:14 /* RWIVF */ #define NV_PBUS_ACCESS_GSP_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_GSP_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_L2 0x0000162c /* RW-4R */ #define NV_PBUS_L2_EVICT 1:0 /* RWIVF */ #define NV_PBUS_L2_EVICT_FIRST 0x00000000 /* RW--V */ #define NV_PBUS_L2_EVICT_NORMAL 0x00000001 /* RWI-V */ #define NV_PBUS_L2_EVICT_LAST 0x00000002 /* RW--V */ #define NV_PBUS_ACCESS_TIMEOUT 0x00001628 /* RW-4R */ #define NV_PBUS_ACCESS_TIMEOUT__PRIV_LEVEL_MASK 0x00001634 /* */ #define NV_PBUS_ACCESS_TIMEOUT_DEVICE(i) (i):(i) /* */ #define NV_PBUS_ACCESS_TIMEOUT_DEVICE__SIZE_1 32 /* */ #define NV_PBUS_ACCESS_TIMEOUT_DEVICE_ENABLED 0x00000001 /* */ #define NV_PBUS_ACCESS_TIMEOUT_DEVICE_DISABLED 0x00000000 /* */ #define NV_PBUS_ACCESS_TIMEOUT_XVE_P 0:0 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_XVE_P_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_XVE_P_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_TIMEOUT_XVE_N 1:1 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_XVE_N_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_XVE_N_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_ACCESS_TIMEOUT_PMU 20:20 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_PMU_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_ACCESS_TIMEOUT_PMU_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_JTAG 5:5 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_JTAG_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_ACCESS_TIMEOUT_JTAG_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_I2C 7:7 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_I2C_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_ACCESS_TIMEOUT_I2C_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_ROM 21:21 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_ROM_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_ACCESS_TIMEOUT_ROM_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_SEC_DEVICE_INFO 2:2 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_SEC_DEVICE_INFO_RESET 0x00000000 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_NVDEC0_DEVICE_INFO 3:3 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_NVDEC0_DEVICE_INFO_RESET 0x00000000 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_NVDEC1_DEVICE_INFO 4:4 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_NVDEC1_DEVICE_INFO_RESET 0x00000000 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_GSP 14:14 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_GSP_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_ACCESS_TIMEOUT_GSP_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_EXP 29:25 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_EXP_MAX 0x0000001F /* RWI-V */ #define NV_PBUS_ACCESS_TIMEOUT_MAN 31:30 /* RWIVF */ #define NV_PBUS_ACCESS_TIMEOUT_MAN_MAX 0x00000003 /* RWI-V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK 0x0000163C /* RW-4R */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "host_dbg_bus" /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLE_FUSE0 15 /* RWI-V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE_FUSE1 8 /* RW--V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PBUS_DEBUG_BUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PBUS_DEBUG_CTL 0x00001090 /* RW-4R */ #define NV_PBUS_DEBUG_CTL__PRIV_LEVEL_MASK 0x0000163C /* */ #define NV_PBUS_DEBUG_CTL_MODE_PORT0 0:0 /* RWIVF */ #define NV_PBUS_DEBUG_CTL_MODE_PORT0_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_DEBUG_CTL_MODE_PORT0_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_DEBUG_CTL_MODE_PORT1 1:1 /* RWIVF */ #define NV_PBUS_DEBUG_CTL_MODE_PORT1_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_DEBUG_CTL_MODE_PORT1_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_DEBUG_CTL_PULLUP_EN 5:5 /* RWIVF */ #define NV_PBUS_DEBUG_CTL_PULLUP_EN_0 0x00000000 /* RWI-V */ #define NV_PBUS_DEBUG_CTL_PULLUP_EN_1 0x00000001 /* RW--V */ #define NV_PBUS_DEBUG_READ 0x00001094 /* R--4R */ #define NV_PBUS_DEBUG_READ__PRIV_LEVEL_MASK 0x0000163C /* */ #define NV_PBUS_DEBUG_READ_DATA 15:0 /* R-XUF */ #define NV_PBUS_DEBUG_SEL_0 0x000010A0 /* RW-4R */ #define NV_PBUS_DEBUG_SEL_0__PRIV_LEVEL_MASK 0x0000163C /* */ #define NV_PBUS_DEBUG_SEL_0_X 3:0 /* RWXUF */ #define NV_PBUS_DEBUG_SEL_1 0x000010A4 /* RW-4R */ #define NV_PBUS_DEBUG_SEL_1__PRIV_LEVEL_MASK 0x0000163C /* */ #define NV_PBUS_DEBUG_SEL_1_X 3:0 /* RWXUF */ #define NV_PBUS_DEBUG_SEL_2 0x000010A8 /* RW-4R */ #define NV_PBUS_DEBUG_SEL_2__PRIV_LEVEL_MASK 0x0000163C /* */ #define NV_PBUS_DEBUG_SEL_2_X 23:0 /* RWXUF */ #define NV_PBUS_DEBUG_SEL_3 0x000010AC /* RW-4R */ #define NV_PBUS_DEBUG_SEL_3__PRIV_LEVEL_MASK 0x0000163C /* */ #define NV_PBUS_DEBUG_SEL_3_X 3:0 /* RWXUF */ #define NV_PBUS_DEBUG_SEL_STRAP 0x000010B0 /* RW-4R */ #define NV_PBUS_DEBUG_SEL_STRAP__PRIV_LEVEL_MASK 0x0000163C /* */ #define NV_PBUS_DEBUG_SEL_STRAP_X 1:0 /* RWIVF */ #define NV_PBUS_DEBUG_SEL_STRAP_X_DEFAULT 0x00000000 /* RWI-V */ #define NV_PBUS_PERFMON 0x00001A00 /* RW-4R */ #define NV_PBUS_PERFMON_SYS_SEL0 7:0 /* RWIUF */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP0 0x00000000 /* RWI-V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP1 0x00000001 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP2 0x00000002 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP3 0x00000003 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP4 0x00000004 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP5 0x00000005 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP6 0x00000006 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP7 0x00000007 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP8 0x00000008 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP9 0x00000009 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP10 0x0000000a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP11 0x0000000b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP12 0x0000000c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP13 0x0000000d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP14 0x0000000e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP15 0x0000000f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP16 0x00000010 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP17 0x00000011 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP18 0x00000012 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP19 0x00000013 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP20 0x00000014 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP21 0x00000015 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP22 0x00000016 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP23 0x00000017 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP24 0x00000018 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP25 0x00000019 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP26 0x0000001a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP27 0x0000001b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP28 0x0000001c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP29 0x0000001d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP30 0x0000001e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP31 0x0000001f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP32 0x00000020 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP33 0x00000021 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP34 0x00000022 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP35 0x00000023 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP36 0x00000024 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP37 0x00000025 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP38 0x00000026 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP39 0x00000027 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP40 0x00000028 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP41 0x00000029 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP42 0x0000002a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP43 0x0000002b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP44 0x0000002c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP45 0x0000002d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP46 0x0000002e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP47 0x0000002f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP48 0x00000030 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP49 0x00000031 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP50 0x00000032 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP51 0x00000033 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP52 0x00000034 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP53 0x00000035 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP54 0x00000036 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP55 0x00000037 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP56 0x00000038 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP57 0x00000039 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP58 0x0000003a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP59 0x0000003b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP60 0x0000003c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP61 0x0000003d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP62 0x0000003e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP63 0x0000003f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP64 0x00000040 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP65 0x00000041 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP66 0x00000042 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP67 0x00000043 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP68 0x00000044 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP69 0x00000045 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP70 0x00000046 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP71 0x00000047 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP72 0x00000048 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP73 0x00000049 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP74 0x0000004a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP75 0x0000004b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP76 0x0000004c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP77 0x0000004d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP78 0x0000004e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP79 0x0000004f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP80 0x00000050 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP81 0x00000051 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP82 0x00000052 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP83 0x00000053 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP84 0x00000054 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP85 0x00000055 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP86 0x00000056 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP87 0x00000057 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP88 0x00000058 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP89 0x00000059 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP90 0x0000005a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP91 0x0000005b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP92 0x0000005c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP93 0x0000005d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP94 0x0000005e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP95 0x0000005f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP96 0x00000060 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP97 0x00000061 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP98 0x00000062 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP99 0x00000063 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP100 0x00000064 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP101 0x00000065 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP102 0x00000066 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP103 0x00000067 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP104 0x00000068 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP105 0x00000069 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP106 0x0000006a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP107 0x0000006b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP108 0x0000006c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP109 0x0000006d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP110 0x0000006e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP111 0x0000006f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP112 0x00000070 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP113 0x00000071 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP114 0x00000072 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP115 0x00000073 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP116 0x00000074 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP117 0x00000075 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP118 0x00000076 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP119 0x00000077 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP120 0x00000078 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP121 0x00000079 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP122 0x0000007a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP123 0x0000007b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP124 0x0000007c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP125 0x0000007d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP126 0x0000007e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP127 0x0000007f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP128 0x00000080 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP129 0x00000081 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP130 0x00000082 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP131 0x00000083 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP132 0x00000084 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP133 0x00000085 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP134 0x00000086 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP135 0x00000087 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP136 0x00000088 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP137 0x00000089 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP138 0x0000008a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP139 0x0000008b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP140 0x0000008c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP141 0x0000008d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP142 0x0000008e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP143 0x0000008f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP144 0x00000090 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP145 0x00000091 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP146 0x00000092 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP147 0x00000093 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP148 0x00000094 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP149 0x00000095 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP150 0x00000096 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP151 0x00000097 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP152 0x00000098 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP153 0x00000099 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP154 0x0000009a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP155 0x0000009b /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP156 0x0000009c /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP157 0x0000009d /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP158 0x0000009e /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP159 0x0000009f /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP160 0x000000a0 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP161 0x000000a1 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP162 0x000000a2 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP163 0x000000a3 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP164 0x000000a4 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP165 0x000000a5 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP166 0x000000a6 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP167 0x000000a7 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP168 0x000000a8 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP169 0x000000a9 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP170 0x000000aa /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP171 0x000000ab /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP172 0x000000ac /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP173 0x000000ad /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP174 0x000000ae /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP175 0x000000af /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP176 0x000000b0 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP177 0x000000b1 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL0_GRP178 0x000000b2 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1 15:8 /* RWIUF */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP0 0x00000000 /* RWI-V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP1 0x00000001 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP2 0x00000002 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP3 0x00000003 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP4 0x00000004 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP5 0x00000005 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP6 0x00000006 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP7 0x00000007 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP8 0x00000008 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP9 0x00000009 /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL1_GRP10 0x0000000a /* RW--V */ #define NV_PBUS_PERFMON_SYS_SEL2 23:16 /* RWIUF */ #define NV_PBUS_PERFMON_SYS_SEL2_GRP0 0x00000000 /* RWI-V */ #define NV_PBUS_PERFMON_HOST_SEL3 30:24 /* RWIUF */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP0 0x00000000 /* RWI-V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP1 0x00000001 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP2 0x00000002 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP3 0x00000003 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP4 0x00000004 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP5 0x00000005 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP6 0x00000006 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP7 0x00000007 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP8 0x00000008 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP9 0x00000009 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP10 0x0000000a /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP11 0x0000000b /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP12 0x0000000c /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP13 0x0000000d /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP14 0x0000000e /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP15 0x0000000f /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP16 0x00000010 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP17 0x00000011 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP18 0x00000012 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP19 0x00000013 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP20 0x00000014 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP21 0x00000015 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP22 0x00000016 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP23 0x00000017 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP24 0x00000018 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP25 0x00000019 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP26 0x0000001a /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP27 0x0000001b /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP28 0x0000001c /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP29 0x0000001d /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP30 0x0000001e /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP31 0x0000001f /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP32 0x00000020 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP33 0x00000021 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP34 0x00000022 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP35 0x00000023 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP36 0x00000024 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP37 0x00000025 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP38 0x00000026 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP39 0x00000027 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP40 0x00000028 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP41 0x00000029 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP42 0x0000002a /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP43 0x0000002b /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP44 0x0000002c /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP45 0x0000002d /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP46 0x0000002e /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP47 0x0000002f /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP48 0x00000030 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP49 0x00000031 /* RW--V */ #define NV_PBUS_PERFMON_HOST_SEL3_GRP50 0x00000032 /* RW--V */ #define NV_PBUS_PERFMON_ENABLE 31:31 /* RWIVF */ #define NV_PBUS_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PBUS_PERFMON_ENABLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PBUS_PERFMON_FILTER_SUBID 0x000010C4 /* RW-4R */ #define NV_PBUS_PERFMON_FILTER_SUBID_VALUE 13:0 /* RWIUF */ #define NV_PBUS_PERFMON_FILTER_SUBID_VALUE_0 0x00000000 /* RWI-V */ #define NV_PBUS_PERFMON_FILTER_SUBID_MASK 29:16 /* RWIUF */ #define NV_PBUS_PERFMON_FILTER_SUBID_MASK_0 0x00000000 /* RWI-V */ #define NV_PBUS_PERFMON_FILTER 0x000010C0 /* RW-4R */ #define NV_PBUS_PERFMON_FILTER_ENABLEGFID 8:8 /* RWIVF */ #define NV_PBUS_PERFMON_FILTER_ENABLEGFID_FALSE 0x0 /* RWI-V */ #define NV_PBUS_PERFMON_FILTER_ENABLEGFID_TRUE 0x1 /* RW--V */ #define NV_PBUS_PERFMON_FILTER_GFID 7:0 /* RWXVF */ #define NV_PBUS_HOST_PRI_FECS_DUMMY_DATA 0xbad0fc00 /* */ #define NV_PBUS_HOST_PRI_TO_DUMMY_DATA 0xbad00100 /* */ #define NV_PBUS_HOST_PRI_HOSTERR_DUMMY_DATA 0xbad00200 /* */ #define NV_PBUS_HOST_FB_TO_DUMMY_DATA 0xbad0fb00 /* */ #define NV_PBUS_HOST_FB_NACK_DUMMY_DATA 0xbad0ac00 /* */ #define NV_PBUS_INTR_0 0x00001100 /* RW-4R */ #define NV_PBUS_INTR_0_PRI_FECSERR 2:2 /* RWIVF */ #define NV_PBUS_INTR_0_PRI_FECSERR_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_PRI_FECSERR_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_PRI_FECSERR_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 /* RWIVF */ #define NV_PBUS_INTR_0_PRI_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_PRI_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_PRI_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_FB_REQ_TIMEOUT 4:4 /* RWIVF */ #define NV_PBUS_INTR_0_FB_REQ_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_FB_REQ_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_FB_REQ_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */ #define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_FB_ACK_EXTRA 6:6 /* RWIVF */ #define NV_PBUS_INTR_0_FB_ACK_EXTRA_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_FB_ACK_EXTRA_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_FB_ACK_EXTRA_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT 7:7 /* RWIVF */ #define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_FB_RDATA_EXTRA 8:8 /* RWIVF */ #define NV_PBUS_INTR_0_FB_RDATA_EXTRA_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_FB_RDATA_EXTRA_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_FB_RDATA_EXTRA_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_SW 26:26 /* RWIVF */ #define NV_PBUS_INTR_0_SW_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_SW_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_SW_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT 27:27 /* RWIVF */ #define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_MPMU 28:28 /* RWIVF */ #define NV_PBUS_INTR_0_MPMU_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_MPMU_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_MPMU_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_0_ACCESS_TIMEOUT 31:31 /* RWIVF */ #define NV_PBUS_INTR_0_ACCESS_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PBUS_INTR_0_ACCESS_TIMEOUT_PENDING 0x00000001 /* R---V */ #define NV_PBUS_INTR_0_ACCESS_TIMEOUT_RESET 0x00000001 /* -W--C */ #define NV_PBUS_INTR_EN_0 0x00001140 /* RW-4R */ #define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 /* RWIVF */ #define NV_PBUS_INTR_EN_0_PRI_FECSERR_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_PRI_FECSERR_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 /* RWIVF */ #define NV_PBUS_INTR_EN_0_PRI_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_PRI_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_FB_REQ_TIMEOUT 4:4 /* RWIVF */ #define NV_PBUS_INTR_EN_0_FB_REQ_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_FB_REQ_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */ #define NV_PBUS_INTR_EN_0_FB_ACK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_FB_ACK_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_FB_ACK_EXTRA 6:6 /* RWIVF */ #define NV_PBUS_INTR_EN_0_FB_ACK_EXTRA_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_FB_ACK_EXTRA_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_FB_RDATA_TIMEOUT 7:7 /* RWIVF */ #define NV_PBUS_INTR_EN_0_FB_RDATA_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_FB_RDATA_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_FB_RDATA_EXTRA 8:8 /* RWIVF */ #define NV_PBUS_INTR_EN_0_FB_RDATA_EXTRA_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_FB_RDATA_EXTRA_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_SW 26:26 /* RWIVF */ #define NV_PBUS_INTR_EN_0_SW_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_SW_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_POSTED_DEADLOCK_TIMEOUT 27:27 /* RWIVF */ #define NV_PBUS_INTR_EN_0_POSTED_DEADLOCK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_POSTED_DEADLOCK_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_MPMU 28:28 /* RWIVF */ #define NV_PBUS_INTR_EN_0_MPMU_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_MPMU_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_0_ACCESS_TIMEOUT 31:31 /* RWIVF */ #define NV_PBUS_INTR_EN_0_ACCESS_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_0_ACCESS_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1 0x00001144 /* RW-4R */ #define NV_PBUS_INTR_EN_1_PRI_FECSERR 2:2 /* RWIVF */ #define NV_PBUS_INTR_EN_1_PRI_FECSERR_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_PRI_FECSERR_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1_PRI_TIMEOUT 3:3 /* RWIVF */ #define NV_PBUS_INTR_EN_1_PRI_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_PRI_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1_FB_REQ_TIMEOUT 4:4 /* RWIVF */ #define NV_PBUS_INTR_EN_1_FB_REQ_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_FB_REQ_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1_FB_ACK_TIMEOUT 5:5 /* RWIVF */ #define NV_PBUS_INTR_EN_1_FB_ACK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_FB_ACK_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1_FB_ACK_EXTRA 6:6 /* RWIVF */ #define NV_PBUS_INTR_EN_1_FB_ACK_EXTRA_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_FB_ACK_EXTRA_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1_FB_RDATA_TIMEOUT 7:7 /* RWIVF */ #define NV_PBUS_INTR_EN_1_FB_RDATA_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_FB_RDATA_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1_FB_RDATA_EXTRA 8:8 /* RWIVF */ #define NV_PBUS_INTR_EN_1_FB_RDATA_EXTRA_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_FB_RDATA_EXTRA_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1_SW 26:26 /* RWIVF */ #define NV_PBUS_INTR_EN_1_SW_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_SW_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1_POSTED_DEADLOCK_TIMEOUT 27:27 /* RWIVF */ #define NV_PBUS_INTR_EN_1_POSTED_DEADLOCK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_POSTED_DEADLOCK_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_INTR_EN_1_ACCESS_TIMEOUT 31:31 /* RWIVF */ #define NV_PBUS_INTR_EN_1_ACCESS_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_INTR_EN_1_ACCESS_TIMEOUT_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_SW_INTR_0 0x00001150 /* -W-4R */ #define NV_PBUS_SW_INTR_0_SET 0:0 /* -W-VF */ #define NV_PBUS_SW_INTR_0_SET_PENDING 0x00000001 /* -W--V */ #define NV_PBUS_SW_INTR_1 0x00001154 /* RW-4R */ #define NV_PBUS_SW_INTR_1_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_SW_INTR_1_SCRATCH_DATA 0x00000000 /* RWI-V */ #define NV_PBUS_SW_INTR_2 0x00001158 /* RW-4R */ #define NV_PBUS_SW_INTR_2_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_SW_INTR_2_SCRATCH_DATA 0x00000000 /* RWI-V */ #define NV_PBUS_SW_INTR_3 0x0000115C /* RW-4R */ #define NV_PBUS_SW_INTR_3_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_SW_INTR_3_SCRATCH_FLAG 0x00000000 /* RWI-V */ #define NV_PBUS_SW_INTR_4 0x00001160 /* RW-4R */ #define NV_PBUS_SW_INTR_4_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_SW_INTR_4_SCRATCH_FLAG 0x00000000 /* RWI-V */ #define NV_PBUS_MPMU_INTR_0 0x00001170 /* -W-4R */ #define NV_PBUS_MPMU_INTR_0_SET 0:0 /* -WIVF */ #define NV_PBUS_MPMU_INTR_0_SET_NOT_PENDING 0x00000000 /* --I-V */ #define NV_PBUS_MPMU_INTR_0_SET_PENDING 0x00000001 /* -W--V */ #define NV_PBUS_MPMU_INTR_1 0x00001174 /* RW-4R */ #define NV_PBUS_MPMU_INTR_1_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_MPMU_INTR_1_SCRATCH_DATA 0x00000000 /* RWI-V */ #define NV_PBUS_MPMU_INTR_2 0x00001178 /* RW-4R */ #define NV_PBUS_MPMU_INTR_2_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_MPMU_INTR_2_SCRATCH_DATA 0x00000000 /* RWI-V */ #define NV_PBUS_MPMU_INTR_3 0x0000117C /* RW-4R */ #define NV_PBUS_MPMU_INTR_3_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_MPMU_INTR_3_SCRATCH_FLAG 0x00000000 /* RWI-V */ #define NV_PBUS_MPMU_INTR_4 0x00001180 /* RW-4R */ #define NV_PBUS_MPMU_INTR_4_SCRATCH 31:0 /* RWIVF */ #define NV_PBUS_MPMU_INTR_4_SCRATCH_FLAG 0x00000000 /* RWI-V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK 0x00001640 /* RW-4R */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "host_fb_timeout" /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLE_FUSE0 15 /* RWI-V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE_FUSE1 8 /* RW--V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PBUS_FB_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PBUS_FB_TIMEOUT 0x00001538 /* RW-4R */ #define NV_PBUS_FB_TIMEOUT__PRIV_LEVEL_MASK 0x00001640 /* */ #define NV_PBUS_FB_TIMEOUT_PERIOD 29:0 /* RWIVF */ #define NV_PBUS_FB_TIMEOUT_PERIOD_INIT 0x000003ff /* RWI-V */ #define NV_PBUS_FB_TIMEOUT_PERIOD_MAX 0x3fffffff /* RW--V */ #define NV_PBUS_FB_TIMEOUT_DETECTION 31:31 /* RWIVF */ #define NV_PBUS_FB_TIMEOUT_DETECTION_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_FB_TIMEOUT_DETECTION_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_FB_RSP_TIMEOUT 0x0000155C /* RW-4R */ #define NV_PBUS_FB_RSP_TIMEOUT__PRIV_LEVEL_MASK 0x00001640 /* */ #define NV_PBUS_FB_RSP_TIMEOUT_PERIOD 29:0 /* RWIVF */ #define NV_PBUS_FB_RSP_TIMEOUT_PERIOD_INIT 0x00003c00 /* RWI-V */ #define NV_PBUS_FB_RSP_TIMEOUT_PERIOD_MAX 0x3fffffff /* RW--V */ #define NV_PBUS_FB_RSP_TIMEOUT_DETECTION 31:31 /* RWIVF */ #define NV_PBUS_FB_RSP_TIMEOUT_DETECTION_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_FB_RSP_TIMEOUT_DETECTION_ENABLED 0x00000001 /* RWI-V */ #define NV_PBUS_FB_CLEANUP 0x00001558 /* RW-4R */ #define NV_PBUS_FB_CLEANUP__PRIV_LEVEL_MASK 0x00001640 /* */ #define NV_PBUS_FB_CLEANUP_REQ_TMO_VAL 23:0 /* RWIVF */ #define NV_PBUS_FB_CLEANUP_REQ_TMO_VAL_INIT 0x00000003 /* RWI-V */ #define NV_PBUS_FB_CLEANUP_REQ_TMO_VAL_MAX 0x00ffffff /* RW--V */ #define NV_PBUS_FB_CLEANUP_REQ_TMO_EN 31:31 /* RWIVF */ #define NV_PBUS_FB_CLEANUP_REQ_TMO_EN_OFF 0x00000000 /* RW--V */ #define NV_PBUS_FB_CLEANUP_REQ_TMO_EN_ON 0x00000001 /* RWI-V */ #define NV_PBUS_FB_RSP_CLEANUP 0x00001560 /* RW-4R */ #define NV_PBUS_FB_RSP_CLEANUP__PRIV_LEVEL_MASK 0x00001640 /* */ #define NV_PBUS_FB_RSP_CLEANUP_TMO_VAL 23:0 /* RWIVF */ #define NV_PBUS_FB_RSP_CLEANUP_TMO_VAL_INIT 0x00000004 /* RWI-V */ #define NV_PBUS_FB_RSP_CLEANUP_TMO_VAL_MAX 0x00ffffff /* RW--V */ #define NV_PBUS_FB_RSP_CLEANUP_TMO_EN 31:31 /* RWIVF */ #define NV_PBUS_FB_RSP_CLEANUP_TMO_EN_OFF 0x00000000 /* RW--V */ #define NV_PBUS_FB_RSP_CLEANUP_TMO_EN_ON 0x00000001 /* RWI-V */ #define NV_PRMIO_CRF0_ALIAS 0x00007080 /* RW-4R */ #define NV_PRMIO_CRF0_ALIAS_INDEX 7:0 /* C--VF */ #define NV_PRMIO_CRF0_ALIAS_INDEX_F0 0x000000F0 /* C---V */ #define NV_PRMIO_CRF0_ALIAS_RMA_ACCESS 8:8 /* RWIVF */ #define NV_PRMIO_CRF0_ALIAS_RMA_ACCESS_DISABLED 0x00000000 /* RWI-V */ #define NV_PRMIO_CRF0_ALIAS_RMA_ACCESS_ENABLED 0x00000001 /* RW--V */ #define NV_PRMIO_CRF0_ALIAS_MODE 10:9 /* RWIVF */ #define NV_PRMIO_CRF0_ALIAS_MODE_ID 0x00000000 /* RWI-V */ #define NV_PRMIO_CRF0_ALIAS_MODE_RMA_PTR 0x00000001 /* RW--V */ #define NV_PRMIO_CRF0_ALIAS_MODE_RMA_DATA 0x00000002 /* RW--V */ #define NV_PRMIO_CRF0_ALIAS_MODE_RMA_DATA32 0x00000003 /* RW--V */ #define NV_PRMIO_CRF1_ALIAS 0x00007084 /* RW-4R */ #define NV_PRMIO_CRF1_ALIAS_INDEX 7:0 /* C--VF */ #define NV_PRMIO_CRF1_ALIAS_INDEX_F1 0x000000F1 /* C---V */ #define NV_PRMIO_CRF1_ALIAS_SCRATCH 15:8 /* RWIVF */ #define NV_PRMIO_CRF1_ALIAS_SCRATCH_0 0x00000000 /* RWI-V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK 0x00001638 /* RW-4R */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 8 /* RWI-V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PBUS_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PBUS_EXT_CYA 0x000012D0 /* RW-4R */ #define NV_PBUS_EXT_CYA__PRIV_LEVEL_MASK 0x00001638 /* */ #define NV_PBUS_EXT_CYA_DATA 31:0 /* RWIUF */ #define NV_PBUS_EXT_CYA_DATA_INIT 0xC0000000 /* RWI-V */ #define NV_PBUS_EXT_CYA_INCREASED_FB_ERROR_ROBUSTNESS 31:31 /* */ #define NV_PBUS_EXT_CYA_SIDE_BAND_REQUESTER_BYPASS 30:30 /* */ #define NV_PBUS_EXT_CYA_WAR_DISABLE_BUG_731978 27:27 /* */ #define NV_PBUS_EXT_CYA_RESERVED 13:0 /* */ #define NV_PBUS_EXT_SPARE1 0x000012D4 /* RW-4R */ #define NV_PBUS_EXT_SPARE1_DATA 31:0 /* RWIUF */ #define NV_PBUS_EXT_SPARE1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PBUS_EXT_SPARE2 0x000012D8 /* RW-4R */ #define NV_PBUS_EXT_SPARE2_DATA 31:0 /* RWIUF */ #define NV_PBUS_EXT_SPARE2_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PBUS_HOLD_LTSSM 0x000012E0 /* RW-4R */ #define NV_PBUS_HOLD_LTSSM_VAL 0:0 /* RWIUF */ #define NV_PBUS_HOLD_LTSSM_VAL_DIS 0x00000000 /* RW--V */ #define NV_PBUS_HOLD_LTSSM_VAL_EN 0x00000001 /* RWI-V */ #define NV_PBUS_HOLD_LTSSM_AUTORELEASE 4:4 /* RWIUF */ #define NV_PBUS_HOLD_LTSSM_AUTORELEASE_DIS 0x00000000 /* RW--V */ #define NV_PBUS_HOLD_LTSSM_AUTORELEASE_EN 0x00000001 /* RWI-V */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD 7:5 /* RWIUF */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_34MS 0x00000000 /* RW--V */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_101MS 0x00000001 /* RWI-V */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_168MS 0x00000002 /* RW--V */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_235MS 0x00000003 /* RW--V */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_302MS 0x00000004 /* RW--V */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_369MS 0x00000005 /* RW--V */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_436MS 0x00000006 /* RW--V */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_503MS 0x00000007 /* RW--V */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_USEC_SHIFT 0x00000010 /* */ #define NV_PBUS_HOLD_LTSSM_FAILSAFE_PERIOD_USEC_BASE 0x00008000 /* */ #define NV_PBUS_PROM_REDIRECT 0x00001A40 /* RW-4R */ #define NV_PBUS_PROM_REDIRECT_EN 0:0 /* RWIUF */ #define NV_PBUS_PROM_REDIRECT_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_PROM_REDIRECT_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PROM_REDIRECT_PTR 23:16 /* RWIUF */ #define NV_PBUS_PROM_REDIRECT_PTR_INIT 0x00000000 /* RWI-V */ #define NV_PBUS_BL_REMAP_1(i) (0x00001900+(i)*4) /* RW-4A */ #define NV_PBUS_BL_REMAP_1__SIZE_1 8 /* */ #define NV_PBUS_BL_REMAP_1_BASE 30:0 /* RWXUF */ #define NV_PBUS_BL_REMAP_1_BASE_0 0x00000000 /* RW--V */ #define NV_PBUS_BL_REMAP_1_BL_ENABLE 31:31 /* RWIUF */ #define NV_PBUS_BL_REMAP_1_BL_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PBUS_BL_REMAP_1_BL_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PBUS_BL_REMAP_2(i) (0x00001920+(i)*4) /* RW-4A */ #define NV_PBUS_BL_REMAP_2__SIZE_1 8 /* */ #define NV_PBUS_BL_REMAP_2_SIZE 22:0 /* RWXUF */ #define NV_PBUS_BL_REMAP_2_BLOCK_HEIGHT 28:26 /* RWXUF */ #define NV_PBUS_BL_REMAP_2_BLOCK_HEIGHT_1 0x00000000 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_HEIGHT_2 0x00000001 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_HEIGHT_4 0x00000002 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_HEIGHT_8 0x00000003 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_HEIGHT_16 0x00000004 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_HEIGHT_32 0x00000005 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_DEPTH 31:29 /* RWXUF */ #define NV_PBUS_BL_REMAP_2_BLOCK_DEPTH_1 0x00000000 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_DEPTH_2 0x00000001 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_DEPTH_4 0x00000002 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_DEPTH_8 0x00000003 /* RW--V */ #define NV_PBUS_BL_REMAP_2_BLOCK_DEPTH_16 0x00000004 /* RW--V */ #define NV_PBUS_BL_REMAP_4(i) (0x00001960+(i)*4) /* RW-4A */ #define NV_PBUS_BL_REMAP_4__SIZE_1 8 /* */ #define NV_PBUS_BL_REMAP_4_BLOCK_BASE 30:0 /* RWXUF */ #define NV_PBUS_BL_REMAP_4_BLOCK_BASE_0 0x00000000 /* RW--V */ #define NV_PBUS_BL_REMAP_6(i) (0x000019A0+(i)*4) /* RW-4A */ #define NV_PBUS_BL_REMAP_6__SIZE_1 8 /* */ #define NV_PBUS_BL_REMAP_6_IMAGE_HEIGHT 15:0 /* RWXUF */ #define NV_PBUS_BL_REMAP_6_IMAGE_HEIGHT_1 0x00000001 /* RW--V */ #define NV_PBUS_BL_REMAP_7(i) (0x000019C0+(i)*4) /* RW-4A */ #define NV_PBUS_BL_REMAP_7__SIZE_1 8 /* */ #define NV_PBUS_BL_REMAP_7_PITCH 19:0 /* RWXUF */ #define NV_PBUS_BL_REMAP_7_PITCH_1 0x00000001 /* RW--V */ #define NV_PBUS_BL_REMAP_7_NUM_BYTES_PIXEL 31:29 /* RWXUF */ #define NV_PBUS_BL_REMAP_7_NUM_BYTES_PIXEL_1 0x00000001 /* RW--V */ #define NV_PBUS_BL_REMAP_7_NUM_BYTES_PIXEL_2 0x00000002 /* RW--V */ #define NV_PBUS_BL_REMAP_7_NUM_BYTES_PIXEL_4 0x00000003 /* RW--V */ #define NV_PBUS_BL_REMAP_7_NUM_BYTES_PIXEL_8 0x00000004 /* RW--V */ #define NV_PBUS_BL_REMAP_7_NUM_BYTES_PIXEL_16 0x00000005 /* RW--V */ #define NV_PBUS_BAR0_WINDOW 0x00001700 /* RW-4R */ #define NV_PBUS_BAR0_WINDOW_BASE 23:0 /* RWIUF */ #define NV_PBUS_BAR0_WINDOW_BASE_0 0x00000000 /* RWI-V */ #define NV_PBUS_BAR0_WINDOW_TARGET 25:24 /* RWIUF */ #define NV_PBUS_BAR0_WINDOW_TARGET_VID_MEM 0x00000000 /* RWI-V */ #define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ #define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_PBUS_BAR0_WINDOW_BASE_SHIFT 16 /* */ #define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */ #define NV_PBUS_BAR1_BLOCK__FMOD_NO_STORAGE 1 /* */ #define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */ #define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */ #define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */ #define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */ #define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ #define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ #define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */ #define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ #define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ #define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */ #define NV_PBUS_BAR1_CONFIG 0x00001708 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE 3:0 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_INIT 2 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_64M 0x00000000 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_128M 0x00000001 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_256M 0x00000002 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_512M 0x00000003 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_1G 0x00000004 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_2G 0x00000005 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_4G 0x00000006 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_8G 0x00000007 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_16G 0x00000008 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_32G 0x00000009 /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_64G 0x0000000A /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_128G 0x0000000B /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_256G_RESERVED 0x0000000C /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_512G_RESERVED 0x0000000D /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_1T_RESERVED 0x0000000E /* */ #define NV_PBUS_BAR1_CONFIG_SIZE_2T_RESERVED 0x0000000F /* */ #define NV_PBUS_BAR1_CONFIG_OVERWRITE 31:31 /* */ #define NV_PBUS_BAR1_CONFIG_OVERWRITE_DISABLED 0x00000000 /* */ #define NV_PBUS_BAR1_CONFIG_OVERWRITE_ENABLED 0x00000001 /* */ #define NV_PBUS_BIND_STATUS 0x00001710 /* R--4R */ #define NV_PBUS_BIND_STATUS__FMOD_NO_STORAGE 1 /* */ #define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */ #define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */ #define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */ #define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */ #define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */ #define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */ #define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */ #define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */ #define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */ #define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */ #define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */ #define NV_PBUS_BAR2_BLOCK__FMOD_NO_STORAGE 1 /* */ #define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* */ #define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */ #define NV_PBUS_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */ #define NV_PBUS_BAR2_BLOCK_TARGET 29:28 /* RWIUF */ #define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ #define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ #define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_PBUS_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */ #define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */ #define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */ #define NV_PBUS_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */ #define NV_PBUS_BAR2_BLOCK_MODE 31:31 /* RWIUF */ #define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ #define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ #define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK 0x00001644 /* RW-4R */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RWI-V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PBUS_FLUSH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PBUS_FLUSH_BIND_CTL 0x0000171C /* RW-4R */ #define NV_PBUS_FLUSH_BIND_CTL__PRIV_LEVEL_MASK 0x00001644 /* */ #define NV_PBUS_FLUSH_BIND_CTL_ENABLE 0:0 /* RWIUF */ #define NV_PBUS_FLUSH_BIND_CTL_ENABLE_TRUE 0x00000001 /* RWI-V */ #define NV_PBUS_FLUSH_BIND_CTL_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PBUS_FLUSH_BIND_THROTTLE 0x00001730 /* RW-4R */ #define NV_PBUS_FLUSH_BIND_THROTTLE__PRIV_LEVEL_MASK 0x00001640 /* */ #define NV_PBUS_FLUSH_BIND_THROTTLE_CNT 7:0 /* RWIUF */ #define NV_PBUS_FLUSH_BIND_THROTTLE_CNT_INIT 0x00000014 /* RWI-V */ #define NV_PBUS_FLUSH_BIND_THROTTLE_CNT_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG 0x00001C00 /* RW-4R */ #define NV_PBUS_EXT_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */ #define NV_PBUS_EXT_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ #define NV_PBUS_EXT_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PBUS_EXT_CG_IDLE_CG_EN 6:6 /* RWIVF */ #define NV_PBUS_EXT_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_EXT_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_EXT_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PBUS_EXT_CG_STATE_CG_EN 7:7 /* */ #define NV_PBUS_EXT_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PBUS_EXT_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PBUS_EXT_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PBUS_EXT_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PBUS_EXT_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG_STALL_CG_EN 14:14 /* RWIVF */ #define NV_PBUS_EXT_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_EXT_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_EXT_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PBUS_EXT_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PBUS_EXT_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PBUS_EXT_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */ #define NV_PBUS_EXT_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ #define NV_PBUS_EXT_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PBUS_EXT_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PBUS_EXT_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PBUS_EXT_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PBUS_EXT_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG_THROT_CLK_EN 28:28 /* */ #define NV_PBUS_EXT_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PBUS_EXT_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PBUS_EXT_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PBUS_EXT_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PBUS_EXT_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PBUS_EXT_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PBUS_EXT_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PBUS_EXT_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PBUS_EXT_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG_HALT_CG_EN 31:31 /* */ #define NV_PBUS_EXT_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PBUS_EXT_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PBUS_EXT_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG1 0x00001C04 /* RW-4R */ #define NV_PBUS_EXT_CG1_MONITOR_CG_EN 0:0 /* RWIVF */ #define NV_PBUS_EXT_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_EXT_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PBUS_EXT_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG 9:1 /* */ #define NV_PBUS_EXT_CG1_SLCG_ENABLED 0x00000000 /* */ #define NV_PBUS_EXT_CG1_SLCG_DISABLED 0x000001ff /* */ #define NV_PBUS_EXT_CG1_SLCG__PROD 0x00000000 /* */ #define NV_PBUS_EXT_CG1_SLCG_BL 1:1 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_BL_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_BL_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_BL__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_C11 2:2 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_C11_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_C11_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_C11__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_MAP 3:3 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_MAP_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_MAP_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_MAP__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_PRI 4:4 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_PRI_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_PRI_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_PRI__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_UNROLL 5:5 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_UNROLL_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_UNROLL_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_UNROLL__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_ASMBL 6:6 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_ASMBL_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_ASMBL_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_ASMBL__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_ROLL 7:7 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_ROLL_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_ROLL_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_ROLL__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_IFR 8:8 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_IFR_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_IFR_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_IFR__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_PM 9:9 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_PM_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_PM_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_PM__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_CPUQ_RSP 10:10 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_CPUQ_RSP_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_CPUQ_RSP_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_CPUQ_RSP__PROD 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_PRIV_RING 11:11 /* RWIVF */ #define NV_PBUS_EXT_CG1_SLCG_PRIV_RING_ENABLED 0x00000000 /* RW--V */ #define NV_PBUS_EXT_CG1_SLCG_PRIV_RING_DISABLED 0x00000001 /* RWI-V */ #define NV_PBUS_EXT_CG1_SLCG_PRIV_RING__PROD 0x00000000 /* RW--V */ #define NV_PBUS_POWER_STATUS 0x1C10 /* R--4R */ #define NV_PBUS_POWER_STATUS_BAR_BIND_STATUS 0:0 /* R-IVF */ #define NV_PBUS_POWER_STATUS_BAR_BIND_STATUS_NOT_IN_PROGRESS 0 /* R-I-V */ #define NV_PBUS_POWER_STATUS_BAR_BIND_STATUS_IN_PROGRESS 1 /* R---V */ #define NV_PBUS_POWER_STATUS_FLUSH_STATUS 4:4 /* R-IVF */ #define NV_PBUS_POWER_STATUS_FLUSH_STATUS_NOT_IN_PROGRESS 0 /* R-I-V */ #define NV_PBUS_POWER_STATUS_FLUSH_STATUS_IN_PROGRESS 1 /* R---V */ #define NV_PBUS_POWER_STATUS_L2_SYSMEM_INVALIDATE_STATUS 5:5 /* R-IVF */ #define NV_PBUS_POWER_STATUS_L2_SYSMEM_INVALIDATE_STATUS_NOT_IN_PROGRESS 0 /* R-I-V */ #define NV_PBUS_POWER_STATUS_L2_SYSMEM_INVALIDATE_STATUS_IN_PROGRESS 1 /* R---V */ #define NV_PBUS_POWER_STATUS_L2_PEERMEM_INVALIDATE_STATUS 6:6 /* R-IVF */ #define NV_PBUS_POWER_STATUS_L2_PEERMEM_INVALIDATE_STATUS_NOT_IN_PROGRESS 0 /* R-I-V */ #define NV_PBUS_POWER_STATUS_L2_PEERMEM_INVALIDATE_STATUS_IN_PROGRESS 1 /* R---V */ #define NV_PBUS_POWER_STATUS_L2_CLEAN_COMPTAGS_STATUS 7:7 /* R-IVF */ #define NV_PBUS_POWER_STATUS_L2_CLEAN_COMPTAGS_STATUS_NOT_IN_PROGRESS 0 /* R-I-V */ #define NV_PBUS_POWER_STATUS_L2_CLEAN_COMPTAGS_STATUS_IN_PROGRESS 1 /* R---V */ #define NV_PBUS_POWER_STATUS_L2_FLUSH_DIRTY_STATUS 8:8 /* R-IVF */ #define NV_PBUS_POWER_STATUS_L2_FLUSH_DIRTY_STATUS_NOT_IN_PROGRESS 0 /* R-I-V */ #define NV_PBUS_POWER_STATUS_L2_FLUSH_DIRTY_STATUS_IN_PROGRESS 1 /* R---V */ #define NV_PBUS_POWER_STATUS_L2_WAIT_FOR_SYS_PENDING_READS_STATUS 9:9 /* R-IVF */ #define NV_PBUS_POWER_STATUS_L2_WAIT_FOR_SYS_PENDING_READS_STATUS_NOT_IN_PROGRESS 0 /* R-I-V */ #define NV_PBUS_POWER_STATUS_L2_WAIT_FOR_SYS_PENDING_READS_STATUS_IN_PROGRESS 1 /* R---V */ #define NV_PBUS_PRI_CTRL 0x00001380 /* RW-4R */ #define NV_PBUS_PRI_CTRL_ADR_SETUP 2:0 /* RWIUF */ #define NV_PBUS_PRI_CTRL_ADR_SETUP_DEFAULT 0x00000000 /* RWI-V */ #define NV_PBUS_PRI_CTRL_RDAT_WAIT 6:4 /* RWIUF */ #define NV_PBUS_PRI_CTRL_RDAT_WAIT_DEFAULT 0x00000000 /* RWI-V */ #define NV_PBUS_PRI_CTRL_ADR_HOLD 10:8 /* RWIUF */ #define NV_PBUS_PRI_CTRL_ADR_HOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PBUS_PRI_CTRL_COUNTER_WIDTH 0x00000008 /* */ #define NV_PBUS_NP_OUTSTANDING 0x00001D00 /* RW-4R */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE 7:0 /* RWIUF */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE_RSTVAL 128 /* RWI-V */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE_128 0x00000080 /* RW--V */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE_64 0x00000040 /* RW--V */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE_32 0x00000020 /* RW--V */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE_16 0x00000010 /* RW--V */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE_8 0x00000008 /* RW--V */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE_4 0x00000004 /* RW--V */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE_2 0x00000002 /* RW--V */ #define NV_PBUS_NP_OUTSTANDING_THROTTLE_1 0x00000001 /* RW--V */ #define NV_PBUS_IFR_STATUS0 0x00001720 /* R--4R */ #define NV_PBUS_IFR_STATUS0_ROMADDR 20:0 /* R-IVF */ #define NV_PBUS_IFR_STATUS0_ROMADDR_INIT 0x001fffff /* R-I-V */ #define NV_PBUS_IFR_STATUS1 0x00001724 /* R--4R */ #define NV_PBUS_IFR_STATUS1_BAR0ADDR 23:0 /* R-IVF */ #define NV_PBUS_IFR_STATUS1_BAR0ADDR_INIT 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_STATUS1_IFF_DONE 27:27 /* R-IVF */ #define NV_PBUS_IFR_STATUS1_IFF_DONE_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_STATUS1_IFF_DONE_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_STATUS1_IDLE 29:29 /* R-IVF */ #define NV_PBUS_IFR_STATUS1_IDLE_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_STATUS1_IDLE_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_STATUS1_LASTEXEC 30:30 /* R-IVF */ #define NV_PBUS_IFR_STATUS1_LASTEXEC_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_STATUS1_LASTEXEC_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_STATUS1_READINRMW 31:31 /* R-IVF */ #define NV_PBUS_IFR_STATUS1_READINRMW_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_STATUS1_READINRMW_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR 0x00001728 /* R--4R */ #define NV_PBUS_IFR_ERROR_BADSIG 0:0 /* R-IVF */ #define NV_PBUS_IFR_ERROR_BADSIG_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_BADSIG_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_FAILSAFE_TIMEOUT 1:1 /* R-IVF */ #define NV_PBUS_IFR_ERROR_FAILSAFE_TIMEOUT_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_FAILSAFE_TIMEOUT_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_BADPARITY 8:8 /* R-IVF */ #define NV_PBUS_IFR_ERROR_BADPARITY_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_BADPARITY_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_BADROMLEN 12:12 /* R-IVF */ #define NV_PBUS_IFR_ERROR_BADROMLEN_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_BADROMLEN_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_BADCHECKSUM 16:16 /* R-IVF */ #define NV_PBUS_IFR_ERROR_BADCHECKSUM_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_BADCHECKSUM_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_BADFORMAT 20:20 /* R-IVF */ #define NV_PBUS_IFR_ERROR_BADFORMAT_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_BADFORMAT_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_PRI_ERROR 21:21 /* R-IVF */ #define NV_PBUS_IFR_ERROR_PRI_ERROR_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_PRI_ERROR_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_IFF_RESENSE_TIMEOUT 23:23 /* R-IVF */ #define NV_PBUS_IFR_ERROR_IFF_RESENSE_TIMEOUT_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_IFF_RESENSE_TIMEOUT_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_IFF_BADFIELDSPEC 24:24 /* R-IVF */ #define NV_PBUS_IFR_ERROR_IFF_BADFIELDSPEC_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_IFF_BADFIELDSPEC_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_IFF_BADSPACEID 25:25 /* R-IVF */ #define NV_PBUS_IFR_ERROR_IFF_BADSPACEID_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_IFF_BADSPACEID_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_IFF_BADFUSELEN 26:26 /* R-IVF */ #define NV_PBUS_IFR_ERROR_IFF_BADFUSELEN_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_IFF_BADFUSELEN_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_IFF_BADCMDOP 27:27 /* R-IVF */ #define NV_PBUS_IFR_ERROR_IFF_BADCMDOP_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_IFF_BADCMDOP_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_ERROR_IFF_PRI_ERROR 29:29 /* R-IVF */ #define NV_PBUS_IFR_ERROR_IFF_PRI_ERROR_TRUE 0x00000001 /* R---V */ #define NV_PBUS_IFR_ERROR_IFF_PRI_ERROR_FALSE 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_INFO0 0x0000172C /* R--4R */ #define NV_PBUS_IFR_INFO0_ROMLEN 19:0 /* R-IVF */ #define NV_PBUS_IFR_INFO0_ROMLEN_INIT 0x00000000 /* R-I-V */ #define NV_PBUS_IFR_FMT_FIXED0 0x00000000 /* RW-4P */ #define NV_PBUS_IFR_FMT_FIXED0_SIGNATURE 31:0 /* */ #define NV_PBUS_IFR_FMT_FIXED0_SIGNATURE_VALUE 0x4947564E /* */ #define NV_PBUS_IFR_FMT_FIXED1 0x00000004 /* RW-4P */ #define NV_PBUS_IFR_FMT_FIXED1_FIXED_DATA_SIZE_VALUE 0x00000024 /* */ #define NV_PBUS_IFR_FMT_FIXED1_CHECKSUM 7:0 /* */ #define NV_PBUS_IFR_FMT_FIXED1_VERSIONSW 15:8 /* */ #define NV_PBUS_IFR_FMT_FIXED1_FIXED_DATA_SIZE 30:16 /* */ #define NV_PBUS_IFR_FMT_FIXED1_PARITY 31:31 /* */ #define NV_PBUS_IFR_FMT_FIXED2 0x00000008 /* RW-4P */ #define NV_PBUS_IFR_FMT_FIXED2_TOTAL_DATA_SIZE 19:0 /* */ #define NV_PBUS_IFR_FMT_FIXED2_TOTAL_DATA_SIZE_MIN 0x00000030 /* */ #define NV_PBUS_IFR_FMT_FIXED2_ZEROS 30:20 /* */ #define NV_PBUS_IFR_FMT_FIXED2_ZEROS_VALUE 0x00000000 /* */ #define NV_PBUS_IFR_FMT_FIXED2_PARITY 31:31 /* */ #define NV_PBUS_IFR_FMT_FIXED3 0x0000000C /* RW-4P */ #define NV_PBUS_IFR_FMT_FIXED3_NV_XVE_SUBSYSTEM 31:0 /* */ #define NV_PBUS_IFR_FMT_CMD 0x00000000 /* RW-4P */ #define NV_PBUS_IFR_FMT_CMD_ADDR_BYTESHIFT 0x00000002 /* */ #define NV_PBUS_IFR_FMT_CMD_OP 1:0 /* */ #define NV_PBUS_IFR_FMT_CMD_OP_WR_INCR 0x00000000 /* */ #define NV_PBUS_IFR_FMT_CMD_OP_WR_STATIC 0x00000001 /* */ #define NV_PBUS_IFR_FMT_CMD_OP_RMW 0x00000002 /* */ #define NV_PBUS_IFR_FMT_CMD_OP_LAST 0x00000003 /* */ #define NV_PBUS_IFR_FMT_CMD_ADDR 23:2 /* */ #define NV_PBUS_IFR_FMT_CMD_RESERVED 24:24 /* */ #define NV_PBUS_IFR_FMT_CMD_RESERVED_VALUE 0x00000000 /* */ #define NV_PBUS_IFR_FMT_CMD_COUNT 30:25 /* */ #define NV_PBUS_IFR_FMT_CMD_COUNT_VALUE_NONWR 0x00000001 /* */ #define NV_PBUS_IFR_FMT_CMD_PARITY 31:31 /* */ #define NV_PBUS_IFR_FMT_RMW_AND 0x00000004 /* RW-4P */ #define NV_PBUS_IFR_FMT_RMW_AND_MASK 31:0 /* */ #define NV_PBUS_IFR_FMT_RMW_OR 0x00000008 /* RW-4P */ #define NV_PBUS_IFR_FMT_RMW_OR_MASK 31:0 /* */ #define NV_PBUS_PRI_LOCAL_ORDERING_XVE 0x00001E00 /* RW-4R */ #define NV_PBUS_PRI_LOCAL_ORDERING_XVE_EN 0:0 /* RWIUF */ #define NV_PBUS_PRI_LOCAL_ORDERING_XVE_EN_DEFAULT 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_LOCAL_ORDERING_XVE_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_XVE_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_SEC 0x00001E04 /* RW-4R */ #define NV_PBUS_PRI_LOCAL_ORDERING_SEC_EN 0:0 /* RWIUF */ #define NV_PBUS_PRI_LOCAL_ORDERING_SEC_EN_DEFAULT 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_LOCAL_ORDERING_SEC_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_SEC_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_PMU 0x00001E08 /* RW-4R */ #define NV_PBUS_PRI_LOCAL_ORDERING_PMU_EN 0:0 /* RWIUF */ #define NV_PBUS_PRI_LOCAL_ORDERING_PMU_EN_DEFAULT 0x00000000 /* RWI-V */ #define NV_PBUS_PRI_LOCAL_ORDERING_PMU_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_PMU_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_I2C 0x00001E0C /* RW-4R */ #define NV_PBUS_PRI_LOCAL_ORDERING_I2C_EN 0:0 /* RWIUF */ #define NV_PBUS_PRI_LOCAL_ORDERING_I2C_EN_DEFAULT 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_LOCAL_ORDERING_I2C_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_I2C_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_JTAG 0x00001E10 /* RW-4R */ #define NV_PBUS_PRI_LOCAL_ORDERING_JTAG_EN 0:0 /* RWIUF */ #define NV_PBUS_PRI_LOCAL_ORDERING_JTAG_EN_DEFAULT 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_LOCAL_ORDERING_JTAG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_JTAG_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_IFR 0x00001E14 /* RW-4R */ #define NV_PBUS_PRI_LOCAL_ORDERING_IFR_EN 0:0 /* RWIUF */ #define NV_PBUS_PRI_LOCAL_ORDERING_IFR_EN_DEFAULT 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_LOCAL_ORDERING_IFR_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_IFR_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC0 0x00001E18 /* RW-4R */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC0_EN 0:0 /* RWIUF */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC0_EN_DEFAULT 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC0_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC0_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC 0x00001E18 /* */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC_EN 0:0 /* */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC_EN_DEFAULT 0x00000001 /* */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC_EN_ENABLED 0x00000001 /* */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC_EN_DISABLED 0x00000000 /* */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC1 0x00001E20 /* RW-4R */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC1_EN 0:0 /* RWIUF */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC1_EN_DEFAULT 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC1_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_NVDEC1_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_GSP 0x00001E1C /* RW-4R */ #define NV_PBUS_PRI_LOCAL_ORDERING_GSP_EN 0:0 /* RWIUF */ #define NV_PBUS_PRI_LOCAL_ORDERING_GSP_EN_DEFAULT 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_LOCAL_ORDERING_GSP_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PBUS_PRI_LOCAL_ORDERING_GSP_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_LVDS_USER 0x00001800 /* RW-4R */ #define NV_PBUS_LVDS_USER_VALUE 3:0 /* RWIVF */ #define NV_PBUS_LVDS_USER_VALUE_INIT 0x0000000F /* RWI-V */ #define NV_PBUS_FUSE_FMT_RECORD 0x00000000 /* */ #define NV_PBUS_FUSE_FMT_RECORD_ALL 31:0 /* */ #define NV_PBUS_FUSE_FMT_RECORD_CHAIN_ID 4:0 /* */ #define NV_PBUS_FUSE_FMT_RECORD_CHAIN_ID_NULL 0x00000000 /* */ #define NV_PBUS_FUSE_FMT_RECORD_CHAIN_ID_INVALID 0x0000001F /* */ #define NV_PBUS_FUSE_FMT_RECORD_IS_IFF 5:5 /* */ #define NV_PBUS_FUSE_FMT_RECORD_IS_IFF_TRUE 0x00000001 /* */ #define NV_PBUS_FUSE_FMT_RECORD_IS_IFF_FALSE 0x00000000 /* */ #define NV_PBUS_FUSE_FMT_RECORD_RECORD_DATA 31:6 /* */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD 0x00000000 /* RW-4P */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_MODIFY_DW_ADDR_BYTESHIFT 0x00000002 /* */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_MODIFY_DW_NUM_DATA 0x00000002 /* */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_WRITE_DW_ADDR_BYTESHIFT 0x00000002 /* */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_WRITE_DW_NUM_DATA 0x00000001 /* */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_ADDR_BYTESHIFT 0x00000002 /* */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_NUM_DATA 0x00000000 /* */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_OP 4:0 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_OP_NULL 0x00000000 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_OP_MODIFY_DW 0x0000001C /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_OP_WRITE_DW 0x0000001D /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_OP_SET_FIELD 0x0000001E /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_OP_INVALID 0x0000001F /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_IS_IFF 5:5 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_IS_IFF_TRUE 0x00000001 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_IS_IFF_FALSE 0x00000000 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_OPERAND 31:6 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_MODIFY_DW_ADDR 27:6 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_WRITE_DW_ADDR 27:6 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_FIELDSPEC 12:6 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_FIELDSPEC_INVALID 0x00000000 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_FIELDSPEC_0BIT 0x00000001 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_FIELDSPEC_1BIT 0x00000002 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_FIELDSPEC_2BIT 0x00000004 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_FIELDSPEC_3BIT 0x00000008 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_FIELDSPEC_4BIT 0x00000010 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_FIELDSPEC_5BIT 0x00000020 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_FIELDSPEC_6BIT 0x00000040 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_BITINDEX 17:13 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_BITINDEX_LSB 0x00000000 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_BITINDEX_MSB 0x0000001F /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE 21:18 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_MIN 0x00000000 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PMC_0 0x00000000 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PBUS_0 0x00000001 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PEXTDEV_0 0x00000002 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PCFG_0 0x00000003 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PCFG1_0 0x00000004 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PPRIV_SYS_0 0x00000005 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_XP3G_0 0x00000006 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_XP3G_1 0x00000007 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_XP3G_2 0x00000008 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_XP3G_3 0x00000009 /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PTRIM_7 0x0000000A /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PVTRIM_0 0x0000000B /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PTRIM_8 0x0000000C /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_NV_PGC6_0 0x0000000D /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_SPACE_MAX 0x0000000D /* RW--V */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_CMD_SET_FIELD_ADDR 31:22 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_WRITE_DW 0x00000004 /* RW-4P */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_WRITE_DW_DATA 31:0 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_MODIFY_DW_AND 0x00000004 /* RW-4P */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_MODIFY_DW_AND_MASK 31:0 /* RWXUF */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_MODIFY_DW_OR 0x00000008 /* RW-4P */ #define NV_PBUS_FUSE_FMT_IFF_RECORD_MODIFY_DW_OR_MASK 31:0 /* RWXUF */ #define NV_BRIDGE 0x0001FFFF:0x00010000 /* RW--D */ #define NV_BRIDGE_REG_ALIAS 0x00010600 /* RW-4R */ #define NV_BRIDGE_REG_ALIAS_ACCESS 0:0 /* RWIVF */ #define NV_BRIDGE_REG_ALIAS_ACCESS_INIT 0x00000001 /* RWI-V */ #define NV_BRIDGE_REG_ALIAS_ACCESS_DISABLED 0x00000000 /* RW--V */ #define NV_BRIDGE_REG_ALIAS_ACCESS_ENABLED 0x00000001 /* RW--V */ #define NV_BRIDGE_REG_ALIAS_BASE_ADDRESS 31:14 /* RWIUF */ #define NV_BRIDGE_REG_ALIAS_BASE_ADDRESS_INIT 0x00037AB7 /* RWI-V */ #define NV_BRIDGE_REG_SCRATCH0 0x00018000 /* RW-4R */ #define NV_BRIDGE_REG_SCRATCH1 0x00018004 /* RW-4R */ #define NV_BRIDGE_REG_LANE_MASK 0x00018008 /* RW-4R */ #define NV_BRIDGE_REG_LANE_MASK_DOWNSTREAM 15:0 /* RWIVF */ #define NV_BRIDGE_REG_LANE_MASK_DOWNSTREAM_INIT 0x0000 /* RWI-V */ #define NV_BRIDGE_REG_LANE_MASK_UPSTREAM 31:16 /* RWIVF */ #define NV_BRIDGE_REG_LANE_MASK_UPSTREAM_INIT 0x0000 /* RWI-V */ #define NV_BRIDGE_REG_LANESKEW0 0x00018030 /* RW-4R */ #define NV_BRIDGE_REG_LANESKEW1 0x00018034 /* RW-4R */ #define NV_BRIDGE_REG_CREDUSP0 0x00018040 /* RW-4R */ #define NV_BRIDGE_REG_CREDUSP1 0x00018044 /* RW-4R */ #define NV_BRIDGE_REG_CREDDSP0 0x00018050 /* RW-4R */ #define NV_BRIDGE_REG_CREDDSP1 0x00018054 /* RW-4R */ #define NV_BRIDGE_REG_PM_CONTROL 0x00018058 /* RW-4R */ #define NV_BRIDGE_REG_PM_CONTROL_DSP_FORCE_L2 0:0 /* RWIVF */ #define NV_BRIDGE_REG_PM_CONTROL_DSP_FORCE_L2_INIT 0 /* RWI-V */ #define NV_BRIDGE_REG_PM_CONTROL_DSP_FORCE_L2_DISABLE 0 /* RW--V */ #define NV_BRIDGE_REG_PM_CONTROL_DSP_FORCE_L2_ENABLE 1 /* RW--V */ #define NV_BRIDGE_REG_PM_CONTROL_FWD_HOTRESET 8:8 /* RWIVF */ #define NV_BRIDGE_REG_PM_CONTROL_FWD_HOTRESET_INIT 0 /* RWI-V */ #define NV_BRIDGE_REG_PM_CONTROL_DSP_CRST_MASK 18:16 /* RWIVF */ #define NV_BRIDGE_REG_PM_CONTROL_DSP_CRST_MASK_INIT 0x0 /* RWI-V */ #define NV_BRIDGE_REG_PM_CONTROL_USP_CRST_MASK 22:20 /* RWIVF */ #define NV_BRIDGE_REG_PM_CONTROL_USP_CRST_MASK_INIT 0x0 /* RWI-V */ #define NV_BRIDGE_REG_CFG_DATA 0x00018060 /* RW-4R */ #define NV_BRIDGE_REG_CFG_CMD 0x00018064 /* RW-4R */ #define NV_BRIDGE_REG_CFG_CMD_ADDRESS 15:0 /* RWIVF */ #define NV_BRIDGE_REG_CFG_CMD_ACTION 19:16 /* RWIVF */ #define NV_BRIDGE_REG_CFG_CMD_ACTION_NOOP 0 /* RWI-V */ #define NV_BRIDGE_REG_CFG_CMD_ACTION_WRITE 1 /* RW--V */ #define NV_BRIDGE_REG_CFG_CMD_MASK 23:20 /* RWIVF */ #define NV_BRIDGE_REG_COUNTER0 0x00018070 /* RW-4R */ #define NV_BRIDGE_REG_COUNTER0_CLKREQ_EVENT 15:0 /* RWIVF */ #define NV_BRIDGE_REG_COUNTER0_CLKREQ_EVENT_INIT 0x00000000 /* RWI-V */ #define NV_BRIDGE_REG_ERR_CONFIG 0x00018080 /* RW-4R */ #define NV_BRIDGE_REG_ERR_CONFIG_BITFLIP_DIST 3:0 /* RWIVF */ #define NV_BRIDGE_REG_ERR_CONFIG_BITFLIP_DIST_INIT 0 /* RWI-V */ #define NV_BRIDGE_REG_ERR_CONFIG_BITSLIP_DIST 7:4 /* RWIVF */ #define NV_BRIDGE_REG_ERR_CONFIG_BITSLIP_DIST_INIT 0 /* RWI-V */ #define NV_BRIDGE_REG_ERR_CONFIG_BITFLIP_ONLY_NONIDLE 11:8 /* RWIVF */ #define NV_BRIDGE_REG_ERR_CONFIG_BITFLIP_ONLY_NONIDLE_INIT 0 /* RWI-V */ #define NV_BRIDGE_REG_ERR_CONFIG_UPSTREAM_DIST 15:12 /* RWIVF */ #define NV_BRIDGE_REG_ERR_CONFIG_UPSTREAM_DIST_INIT 0 /* RWI-V */ #define NV_BRIDGE_REG_ERR_BITFLIP_FREQ 0x00018090 /* RW-4R */ #define NV_BRIDGE_REG_ERR_BITFLIP_FREQ_VAL 31:0 /* RWIVF */ #define NV_BRIDGE_REG_ERR_BITFLIP_FREQ_VAL_INIT 0x00000000 /* RWI-V */ #define NV_BRIDGE_REG_ERR_BITFLIP_STATEMASK 0x00018094 /* RW-4R */ #define NV_BRIDGE_REG_ERR_BITFLIP_STATEMASK_VAL 31:0 /* RWIVF */ #define NV_BRIDGE_REG_ERR_BITFLIP_STATEMASK_VAL_INIT 0xffffffff /* RWI-V */ #define NV_BRIDGE_REG_ERR_BITFLIP_DOUBLE 0x00018098 /* RW-4R */ #define NV_BRIDGE_REG_ERR_BITFLIP_DOUBLE_VAL 31:0 /* RWIVF */ #define NV_BRIDGE_REG_ERR_BITFLIP_DOUBLE_VAL_INIT 0x00000000 /* RWI-V */ #define NV_BRIDGE_REG_ERR_BITSLIP_FREQ 0x000180a0 /* RW-4R */ #define NV_BRIDGE_REG_ERR_BITSLIP_FREQ_VAL 31:0 /* RWIVF */ #define NV_BRIDGE_REG_ERR_BITSLIP_FREQ_VAL_INIT 0x00000000 /* RWI-V */ #define NV_BRIDGE_REG_ERR_BITSLIP_STATEMASK 0x000180a4 /* RW-4R */ #define NV_BRIDGE_REG_ERR_BITSLIP_STATEMASK_VAL 31:0 /* RWIVF */ #define NV_BRIDGE_REG_ERR_BITSLIP_STATEMASK_VAL_INIT 0xffffffff /* RWI-V */ #define NV_BRIDGE_REG_ERR_UPSTREAM 0x000180b0 /* RW-4R */ #define NV_BRIDGE_REG_ERR_UPSTREAM_FREQ 31:0 /* RWIVF */ #define NV_BRIDGE_REG_ERR_UPSTREAM_FREQ_INIT 0x00000000 /* RWI-V */ #define NV_BRIDGE_REG_ERR_EIDLE 0x000180c0 /* RW-4R */ #define NV_BRIDGE_REG_ERR_EIDLE_FALSE_FREQ 7:0 /* RWIVF */ #define NV_BRIDGE_REG_ERR_EIDLE_FALSE_FREQ_INIT 0x00 /* RWI-V */ #define NV_BRIDGE_REG_ERR_EIDLE_SLOP_AMOUNT 11:8 /* RWIVF */ #define NV_BRIDGE_REG_ERR_EIDLE_SLOP_AMOUNT_INIT 0x00 /* RWI-V */ #define NV_BRIDGE_REG_ERR_EIDLE_SLOP_FREQ 19:12 /* RWIVF */ #define NV_BRIDGE_REG_ERR_EIDLE_SLOP_FREQ_INIT 0x00 /* RWI-V */ #define NV_BRIDGE_GPU_BACKDOOR_EC_0 0x00019000 /* RW-4R */ #define NV_BRIDGE_GPU_BACKDOOR_EC_0_GC6_TB_DEBUG 7:0 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_1 0x00019004 /* RW-4R */ #define NV_BRIDGE_GPU_BACKDOOR_EC_1_GC6_KEPLER_PWR 0:0 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_1_GC6_RST_ASSERT 15:1 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_1_GC6_RST_DEASSERT 31:16 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2 0x00019008 /* RW-4R */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPU_EVENT 0:0 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_1_6 6:1 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_7 7:7 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_8 8:8 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_9 9:9 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_10 10:10 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_11 11:11 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_12 12:12 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_13 13:13 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_14 14:14 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_GPIO_15 15:15 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_2_WAKEUP_ASSERT_RESERVED 31:16 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3 0x0001900c /* RW-4R */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_DELAY_RESPONSE 15:0 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_PCH_STUB 31:31 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_PCH_STUB_DISABLE 0x00000000 /* RW--V */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_PCH_STUB_ENABLE 0x00000001 /* RW--V */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_PEXRST 25:25 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_PEXRST_ASSERT 0x00000000 /* RW--V */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_PEXRST_DEASSERT 0x00000001 /* RW--V */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_PEXRST_OVERRIDE 24:24 /* RWXVF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_PEXRST_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_BRIDGE_GPU_BACKDOOR_EC_3_PEXRST_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_BRIDGE_GPU_BACKDOOR_EC_4 0x00019010 /* R--4R */ #define NV_BRIDGE_GPU_BACKDOOR_EC_4_STUB_STATUS 15:0 /* R--VF */ #define NV_BRIDGE_GPU_BACKDOOR_EC_4_RESERVED 31:16 /* R--VF */ #define NV_BRIDGE_GPU_BACKDOOR_RAM_BSI_ADDR 0x00019100 /* RW-4R */ #define NV_BRIDGE_GPU_BACKDOOR_RAM_BSI_DATA 0x00019104 /* R--4R */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0 0x00019200 /* R--4R */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0_DUT0 7:0 /* R--VF */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0_DUT0_L0 0x19 /* R---V */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0_SWITCH_DSP 20:16 /* R--VF */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0_SWITCH_DSP_L0 0x10 /* R---V */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0_SWITCH_DSP_L0s 0x11 /* R---V */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0_SWITCH_DSP_L2 0x14 /* R---V */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0_SWITCH_DSP_DIS 0x16 /* R---V */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0_SWITCH_USP 28:24 /* R--VF */ #define NV_BRIDGE_GPU_BACKDOOR_LTSSM_STATUS0_SWITCH_USP_L0 0x10 /* R---V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK 0x00001760 /* RW-4R */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 8 /* RWI-V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PBUS_PRI_TIMEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_PBUS_PRI_TIMEOUT 0x00001764 /* RW-4R */ #define NV_PBUS_PRI_TIMEOUT__PRIV_LEVEL_MASK 0x00001760 /* */ #define NV_PBUS_PRI_TIMEOUT_PERIOD 23:0 /* RWIVF */ #define NV_PBUS_PRI_TIMEOUT_PERIOD_MIN 0x00000003 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PERIOD_MAX 0x00ffffff /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PERIOD_RTL 0x00000015 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PERIOD_SHORT 0x00000006 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_PERIOD_INIT 0x00000400 /* RWI-V */ #define NV_PBUS_PRI_TIMEOUT_EN 31:31 /* RWIVF */ #define NV_PBUS_PRI_TIMEOUT_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PBUS_PRI_TIMEOUT_EN_ENABLED 0x00000001 /* RWI-V */ #define NV_IO_VGA_VSE1 0x00000102 /* */ #define NV_IO_CRTM_INDEX 0x000003b4 /* */ #define NV_IO_CRTM_DATA 0x000003b5 /* */ #define NV_IO_CRTM_MODE 0x000003b8 /* */ #define NV_IO_CTRM_FCWRITE 0x000003ba /* */ #define NV_IO_VGA_ATTR 0x000003c0 /* */ #define NV_IO_VGA_MODE 0x000003c1 /* */ #define NV_IO_VGA_MISCWRITE 0x000003c2 /* */ #define NV_IO_VGA_VSE2 0x000003c3 /* */ #define NV_IO_VGA_SEQ_INDEX 0x000003c4 /* */ #define NV_IO_VGA_SEQ_DATA 0x000003c5 /* */ #define NV_IO_VGA_DAC_PIXEL_MASK 0x000003c6 /* */ #define NV_IO_VGA_DAC_READ_MODE_ADDRESS 0x000003c7 /* */ #define NV_IO_VGA_DAC_WRITE_MODE_ADDRESS 0x000003c8 /* */ #define NV_IO_VGA_DAC_PALETTE_DATA 0x000003c9 /* */ #define NV_IO_VGA_FCREAD 0x000003ca /* */ #define NV_IO_VGA_MISCREAD 0x000003cc /* */ #define NV_IO_VGA_GR_INDEX 0x000003ce /* */ #define NV_IO_VGA_GR_DATA 0x000003cf /* */ #define NV_IO_RMA_ID 0x000003D0 /* */ #define NV_IO_RMA_PTR 0x000003D1 /* */ #define NV_IO_RMA_DATA 0x000003D2 /* */ #define NV_IO_RMA_DATA32 0x000003D3 /* */ #define NV_IO_CRTC_INDEX 0x000003d4 /* */ #define NV_IO_CRTC_DATA 0x000003d5 /* */ #define NV_IO_CRTC_MODE 0x000003d8 /* */ #define NV_IO_CRTC_FCWRITE 0x000003da /* */ #endif // __ga102_dev_bus_h__