/* _NVRM_COPYRIGHT_BEGIN_
 *
 * Copyright 2003-2016 by NVIDIA Corporation.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 *
 * _NVRM_COPYRIGHT_END_
 */

#ifndef __ga102_ioctrl_discovery_h__
#define __ga102_ioctrl_discovery_h__
/* This file is autogenerated.  Do not edit */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_IOCTRL                 0x00A00000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLIPT                 0x00A02000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_MINION                 0x00A06000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_PLL                    0x00A03800                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLDL_MULTI            0x00A08000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLTLC_MULTI           0x00A0D000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLIPT_LNK_MULTI       0x00A0F000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLDL_0                0x00A10000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLTLC_0               0x00A15000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLIPT_LNK_0           0x00A17000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLDL_1                0x00A18000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLTLC_1               0x00A1D000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLIPT_LNK_1           0x00A1F000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLDL_2                0x00A20000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLTLC_2               0x00A25000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLIPT_LNK_2           0x00A27000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLDL_3                0x00A28000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLTLC_3               0x00A2D000                    /*       */
#define  NV_DISCOVERY_IOCTRL_UNICAST_0_SW_DEVICE_BASE_NVLIPT_LNK_3           0x00A2F000                    /*       */
#endif // __ga102_ioctrl_discovery_h__