/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_vbus_h__ #define __ga102_dev_vbus_h__ /* This file is autogenerated. Do not edit */ #define NV_VBUS 0x00bfffff:0x00bf0000 /* RW--D */ #define NV_VBUS_VF_BAR1_BLOCK(i) (0x00BF0000+(i)*4) /* RW-4A */ #define NV_VBUS_VF_BAR1_BLOCK__SIZE_1 64 /* */ #define NV_VBUS_VF_BAR1_BLOCK_MAP 29:0 /* */ #define NV_VBUS_VF_BAR1_BLOCK_PTR 27:0 /* RWIUF */ #define NV_VBUS_VF_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */ #define NV_VBUS_VF_BAR1_BLOCK_TARGET 29:28 /* RWIUF */ #define NV_VBUS_VF_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ #define NV_VBUS_VF_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ #define NV_VBUS_VF_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_VBUS_VF_BAR1_BLOCK_MODE 31:31 /* RWIUF */ #define NV_VBUS_VF_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ #define NV_VBUS_VF_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ #define NV_VBUS_VBAR1_BLOCK_PTR_SHIFT 12 /* */ #define NV_VBUS_VF_BIND_STATUS(i) (0x00BF0400+(i)*4) /* R--4A */ #define NV_VBUS_VF_BIND_STATUS__SIZE_1 64 /* */ #define NV_VBUS_VF_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */ #define NV_VBUS_VF_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */ #define NV_VBUS_VF_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */ #define NV_VBUS_VF_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */ #define NV_VBUS_VF_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ #define NV_VBUS_VF_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */ #define NV_VBUS_VF_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */ #define NV_VBUS_VF_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */ #define NV_VBUS_VF_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */ #define NV_VBUS_VF_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */ #define NV_VBUS_VF_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ #define NV_VBUS_VF_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */ #define NV_VBUS_VF_BAR2_BLOCK(i) (0x00BF0800+(i)*4) /* RW-4A */ #define NV_VBUS_VF_BAR2_BLOCK__SIZE_1 64 /* */ #define NV_VBUS_VF_BAR2_BLOCK_MAP 29:0 /* */ #define NV_VBUS_VF_BAR2_BLOCK_PTR 27:0 /* RWIUF */ #define NV_VBUS_VF_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */ #define NV_VBUS_VF_BAR2_BLOCK_TARGET 29:28 /* RWIUF */ #define NV_VBUS_VF_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ #define NV_VBUS_VF_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ #define NV_VBUS_VF_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_VBUS_VF_BAR2_BLOCK_DEBUG_CYA 30:30 /* RWIUF */ #define NV_VBUS_VF_BAR2_BLOCK_DEBUG_CYA_OFF 0x00000001 /* RW--V */ #define NV_VBUS_VF_BAR2_BLOCK_DEBUG_CYA_ON 0x00000000 /* RW--V */ #define NV_VBUS_VF_BAR2_BLOCK_DEBUG_CYA_INIT 0x00000001 /* RWI-V */ #define NV_VBUS_VF_BAR2_BLOCK_MODE 31:31 /* RWIUF */ #define NV_VBUS_VF_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ #define NV_VBUS_VF_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ #define NV_VBUS_VBAR2_BLOCK_PTR_SHIFT 12 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK 0x00BF1400 /* RW-4R */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_VBUS_VF_L2_INVALIDATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE(i) (0x00BF0C00+(i)*4) /* RW-4A */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE__SIZE_1 64 /* */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE__PRIV_LEVEL_MASK 0x00BF1400 /* */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE_PENDING 0:0 /* RWIUF */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE_PENDING_ISSUE 0x00000001 /* -W--T */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ #define NV_VBUS_VF_L2_SYSMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE(i) (0x00BF1000+(i)*4) /* RW-4A */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE__SIZE_1 64 /* */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE__PRIV_LEVEL_MASK 0x00BF1400 /* */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE_PENDING 0:0 /* RWIUF */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE_PENDING_ISSUE 0x00000001 /* -W--T */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ #define NV_VBUS_VF_L2_PEERMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */ #endif // __ga102_dev_vbus_h__