/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_top_h__ #define __ga102_dev_top_h__ /* This file is autogenerated. Do not edit */ #define NV_PTOP 0x00022FFF:0x00022400 /* RW--D */ #define NV_PTOP_DEBUG_1 0x00022400 /* R--4R */ #define NV_PTOP_DEBUG_1_OPENGL 16:16 /* R--VF */ #define NV_PTOP_DEBUG_1_OPENGL_OFF 0x00000000 /* R---V */ #define NV_PTOP_DEBUG_1_OPENGL_ON 0x00000001 /* R---V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK 0x00022404 /* RW-4R */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PTOP_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_IFR_XVE 0x00000041 /* RWB-V */ #define NV_PTOP_SCRATCH0 0x00022408 /* RW-4R */ #define NV_PTOP_SCRATCH0__PRIV_LEVEL_MASK 0x00022404 /* */ #define NV_PTOP_SCRATCH0_VALUE 31:0 /* RWIVF */ #define NV_PTOP_SCRATCH0_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTOP_END_OF_SIM 0x00022408 /* */ #define NV_PTOP_END_OF_SIM_REACHED 0:0 /* */ #define NV_PTOP_END_OF_SIM_REACHED_ASSERT 0x00000001 /* */ #define NV_PTOP_END_OF_SIM_REACHED_DEASSERT 0x00000000 /* */ #define NV_PTOP_SCRATCH1 0x0002240c /* RW-4R */ #define NV_PTOP_SCRATCH1_VALUE 31:2 /* RWIVF */ #define NV_PTOP_SCRATCH1_VALUE_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTOP_SCRATCH1_FS_SW_PROTECT 0:0 /* RWIVF */ #define NV_PTOP_SCRATCH1_FS_SW_PROTECT_OFF 0x00000000 /* RWI-V */ #define NV_PTOP_SCRATCH1_FS_SW_PROTECT_ON 0x00000001 /* RW--V */ #define NV_PTOP_SCRATCH1_DEVINIT_COMPLETED 1:1 /* RWIVF */ #define NV_PTOP_SCRATCH1_DEVINIT_COMPLETED_FALSE 0x00000000 /* RWI-V */ #define NV_PTOP_SCRATCH1_DEVINIT_COMPLETED_TRUE 0x00000001 /* RW--V */ #define NV_PTOP_PLATFORM 0x00022410 /* R--4R */ #define NV_PTOP_PLATFORM_TYPE 2:0 /* R-IVF */ #define NV_PTOP_PLATFORM_TYPE_SILICON 0x00000000 /* R-I-V */ #define NV_PTOP_PLATFORM_TYPE_FMODEL 0x00000001 /* R---V */ #define NV_PTOP_PLATFORM_TYPE_RTL 0x00000002 /* R---V */ #define NV_PTOP_PLATFORM_TYPE_EMU 0x00000003 /* R---V */ #define NV_PTOP_PLATFORM_TYPE_FPGA 0x00000004 /* R---V */ #define NV_PTOP_FS4 0x0002241C /* RW-4R */ #define NV_PTOP_FS4_GEN2_PCIE 0:0 /* RWIVF */ #define NV_PTOP_FS4_GEN2_PCIE_DEFAULT 0x00000001 /* RWI-V */ #define NV_PTOP_FS4_GEN2_PCIE_ENABLED 0x00000001 /* RW--V */ #define NV_PTOP_FS4_GEN2_PCIE_DISABLED 0x00000000 /* RW--V */ #define NV_PTOP_FS4_FORCE_MULTIMEDIA_DEV 1:1 /* RWIVF */ #define NV_PTOP_FS4_FORCE_MULTIMEDIA_DEV_DEFAULT 0x00000000 /* RWI-V */ #define NV_PTOP_FS4_FORCE_MULTIMEDIA_DEV_DISABLED 0x00000000 /* RW--V */ #define NV_PTOP_FS4_FORCE_MULTIMEDIA_DEV_ENABLED 0x00000001 /* RW--V */ #define NV_PTOP_FS4_GEN2_PCIE_SPEED 7:7 /* RWIVF */ #define NV_PTOP_FS4_GEN2_PCIE_SPEED_DEFAULT 0x00000001 /* RWI-V */ #define NV_PTOP_FS4_GEN2_PCIE_SPEED_ENABLED 0x00000001 /* RW--V */ #define NV_PTOP_FS4_GEN2_PCIE_SPEED_DISABLED 0x00000000 /* RW--V */ #define NV_PTOP_SCAL_NUM_GPCS 0x00022430 /* R--4R */ #define NV_PTOP_SCAL_NUM_GPCS_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_GPCS_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_TPC_PER_GPC 0x00022434 /* R--4R */ #define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_TPC_PER_GPC_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_FBPS 0x00022438 /* R--4R */ #define NV_PTOP_SCAL_NUM_FBPS_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_FBPS_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_FBPAS 0x0002243C /* R--4R */ #define NV_PTOP_SCAL_NUM_FBPAS_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_FBPAS_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_ZCULL_BANKS 0x00022440 /* R--4R */ #define NV_PTOP_SCAL_NUM_ZCULL_BANKS_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_ZCULL_BANKS_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_CES 0x00022444 /* R--4R */ #define NV_PTOP_SCAL_NUM_CES_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_CES_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_DISP_HEADS 0x00022448 /* R--4R */ #define NV_PTOP_SCAL_NUM_DISP_HEADS_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_DISP_HEADS_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_NVENCS 0x0002244C /* R--4R */ #define NV_PTOP_SCAL_NUM_NVENCS_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_NVENCS_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_LTC_PER_FBP 0x00022450 /* R--4R */ #define NV_PTOP_SCAL_NUM_LTC_PER_FBP_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_LTC_PER_FBP_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_LTCS 0x00022454 /* R--4R */ #define NV_PTOP_SCAL_NUM_LTCS_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_LTCS_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_FBPA_PER_FBP 0x00022458 /* R--4R */ #define NV_PTOP_SCAL_NUM_FBPA_PER_FBP_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_FBPA_PER_FBP_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_SLICES_PER_LTC 0x0002245c /* R--4R */ #define NV_PTOP_SCAL_NUM_SLICES_PER_LTC_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_SLICES_PER_LTC_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_PES_PER_GPC 0x00022460 /* R--4R */ #define NV_PTOP_SCAL_NUM_PES_PER_GPC_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_PES_PER_GPC_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_NVDECS 0x00022464 /* R--4R */ #define NV_PTOP_SCAL_NUM_NVDECS_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_NVDECS_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_NVJPGS 0x00022468 /* R--4R */ #define NV_PTOP_SCAL_NUM_NVJPGS_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_NVJPGS_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_SCAL_NUM_NVLINK 0x0002246c /* R--4R */ #define NV_PTOP_SCAL_NUM_NVLINK_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_NVLINK_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_FLOORSWEEP_STATUS 0x00022470 /* R--4R */ #define NV_PTOP_FLOORSWEEP_STATUS_TPC 0:0 /* R-IVF */ #define NV_PTOP_FLOORSWEEP_STATUS_TPC_INIT 0x00000000 /* R-I-V */ #define NV_PTOP_FLOORSWEEP_STATUS_TPC_NO 0x00000000 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_TPC_YES 0x00000001 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_GPC 1:1 /* R-IVF */ #define NV_PTOP_FLOORSWEEP_STATUS_GPC_INIT 0x00000000 /* R-I-V */ #define NV_PTOP_FLOORSWEEP_STATUS_GPC_NO 0x00000000 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_GPC_YES 0x00000001 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_FBP 2:2 /* R-IVF */ #define NV_PTOP_FLOORSWEEP_STATUS_FBP_INIT 0x00000000 /* R-I-V */ #define NV_PTOP_FLOORSWEEP_STATUS_FBP_NO 0x00000000 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_FBP_YES 0x00000001 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_FBIO 4:4 /* R-IVF */ #define NV_PTOP_FLOORSWEEP_STATUS_FBIO_INIT 0x00000000 /* R-I-V */ #define NV_PTOP_FLOORSWEEP_STATUS_FBIO_NO 0x00000000 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_FBIO_YES 0x00000001 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_PES 5:5 /* R-IVF */ #define NV_PTOP_FLOORSWEEP_STATUS_PES_INIT 0x00000000 /* R-I-V */ #define NV_PTOP_FLOORSWEEP_STATUS_PES_NO 0x00000000 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_PES_YES 0x00000001 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_ROP_GPC 6:6 /* R-IVF */ #define NV_PTOP_FLOORSWEEP_STATUS_ROP_GPC_INIT 0x00000000 /* R-I-V */ #define NV_PTOP_FLOORSWEEP_STATUS_ROP_GPC_NO 0x00000000 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_ROP_GPC_YES 0x00000001 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_LTC 7:7 /* R-IVF */ #define NV_PTOP_FLOORSWEEP_STATUS_LTC_INIT 0x00000000 /* R-I-V */ #define NV_PTOP_FLOORSWEEP_STATUS_LTC_NO 0x00000000 /* R---V */ #define NV_PTOP_FLOORSWEEP_STATUS_LTC_YES 0x00000001 /* R---V */ #define NV_PTOP_SCAL_NUM_ROP_PER_GPC 0x00022480 /* R--4R */ #define NV_PTOP_SCAL_NUM_ROP_PER_GPC_VALUE 4:0 /* R-IVF */ #define NV_PTOP_SCAL_NUM_ROP_PER_GPC_VALUE_DEFAULT 0 /* R-I-V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK 0x00022600 /* RW-4R */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWB-V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PTOP_FEATURE_SECURITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_PTOP_FEATURE_SECURITY_LOCK 0x00022604 /* RW-4R */ #define NV_PTOP_FEATURE_SECURITY_LOCK__PRIV_LEVEL_MASK 0x00022600 /* */ #define NV_PTOP_FEATURE_SECURITY_LOCK_MMU 0:0 /* RWBVF */ #define NV_PTOP_FEATURE_SECURITY_LOCK_MMU_UNLOCKED 0x00000000 /* RWB-V */ #define NV_PTOP_FEATURE_SECURITY_LOCK_MMU_LOCKED 0x00000001 /* RW--V */ #define NV_PTOP_FEATURE_SECURITY_LOCK_HDCP 3:3 /* RWBVF */ #define NV_PTOP_FEATURE_SECURITY_LOCK_HDCP_UNLOCKED 0x00000000 /* RWB-V */ #define NV_PTOP_FEATURE_SECURITY_LOCK_HDCP_LOCKED 0x00000001 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK 0x00022700 /* RW-4R */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWB-V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_PTOP_ROP_THROTTLE_LIMIT(i) (0x00022704+(i)*4) /* RW-4A */ #define NV_PTOP_ROP_THROTTLE_LIMIT__SIZE_1 12 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT__PRIV_LEVEL_MASK 0x00022700 /* */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC 4:0 /* RWBVF */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_MAX_PERF 0x00000000 /* RWB-V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_96875 0x00000001 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_93750 0x00000002 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_90625 0x00000003 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_87500 0x00000004 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_84375 0x00000005 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_81250 0x00000006 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_78125 0x00000007 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_75000 0x00000008 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_71875 0x00000009 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_68750 0x0000000a /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_65625 0x0000000b /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_62500 0x0000000c /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_59375 0x0000000d /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_56250 0x0000000e /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_53125 0x0000000f /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_50000 0x00000010 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_46875 0x00000011 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_43750 0x00000012 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_40625 0x00000013 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_37500 0x00000014 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_34375 0x00000015 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_31250 0x00000016 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_28125 0x00000017 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_25000 0x00000018 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_21875 0x00000019 /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_18750 0x0000001a /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_15625 0x0000001b /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_12500 0x0000001c /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_09375 0x0000001d /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_06250 0x0000001e /* RW--V */ #define NV_PTOP_ROP_THROTTLE_LIMIT_PHYSICAL_GPC_0_03125 0x0000001f /* RW--V */ #define NV_PTOP_DEVICE_INFO_CFG_MAX_DEVICES_STATIC 256 #define NV_PTOP_DEVICE_INFO_CFG_MAX_ROWS_PER_DEVICE_STATIC 15 #define NV_PTOP_DEVICE_INFO_CFG 0x000224FC /* R--4R */ #define NV_PTOP_DEVICE_INFO_CFG_VERSION 3:0 /* C--UF */ #define NV_PTOP_DEVICE_INFO_CFG_VERSION_INIT 2 /* C---V */ #define NV_PTOP_DEVICE_INFO_CFG_MAX_DEVICES 15:4 /* C--UF */ #define NV_PTOP_DEVICE_INFO_CFG_MAX_DEVICES_INIT 14 /* C---V */ #define NV_PTOP_DEVICE_INFO_CFG_MAX_ROWS_PER_DEVICE 19:16 /* C--UF */ #define NV_PTOP_DEVICE_INFO_CFG_MAX_ROWS_PER_DEVICE_INIT 3 /* C---V */ #define NV_PTOP_DEVICE_INFO_CFG_NUM_ROWS 31:20 /* C--UF */ #define NV_PTOP_DEVICE_INFO_CFG_NUM_ROWS_INIT 39 /* C---V */ #define NV_PTOP_DEVICE_INFO2(i) (0x00022800+(i)*4) /* R--4A */ #define NV_PTOP_DEVICE_INFO2__SIZE_1 39 /* */ #define NV_PTOP_DEVICE_INFO2_ROW_VALUE 31:0 /* R--VF */ #define NV_PTOP_DEVICE_INFO2_ROW_VALUE_INVALID 0x0 /* R---V */ #define NV_PTOP_DEVICE_INFO2_ROW_CHAIN 31:31 /* */ #define NV_PTOP_DEVICE_INFO2_ROW_CHAIN_MORE 1 /* */ #define NV_PTOP_DEVICE_INFO2_ROW_CHAIN_LAST 0 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_FAULT_ID 10:0 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_FAULT_ID_INVALID 0 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_INSTANCE_ID 23:16 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM 30:24 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_GRAPHICS 0 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_NVDEC 16 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_NVENC 14 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_NVJPG 21 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_OFA 22 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_SEC 13 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_LCE 19 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_GSP 20 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_IOCTRL 18 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_FLA 23 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_RESET_ID 39:32 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_RESET_ID_INVALID 0 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_DEVICE_PRI_BASE 57:40 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_IS_ENGINE 62:62 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_IS_ENGINE_TRUE 1 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_IS_ENGINE_FALSE 0 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_RLENG_ID 65:64 /* */ #define NV_PTOP_DEVICE_INFO2_DEV_RUNLIST_PRI_BASE 89:74 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_GRAPHICS0 12:12 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_SEC0 1:1 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_NVENC0 18:18 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_NVDEC0 15:15 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_NVDEC1 16:16 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_LCE0 2:2 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_LCE1 3:3 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_LCE2 4:4 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_LCE3 5:5 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_LCE4 6:6 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_OFA0 17:17 /* */ #define NV_PTOP_DEVICE_INFO_RESET_FIELD_FOR_UCODE_AND_VBIOS_ONLY_IOCTRL0 25:25 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_GRAPHICS0 12 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_SEC0 1 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_NVENC0 18 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_NVDEC0 15 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_NVDEC1 16 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_LCE0 2 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_LCE1 3 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_LCE2 4 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_LCE3 5 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_LCE4 6 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_OFA0 17 /* */ #define NV_PTOP_DEVICE_INFO_RESET_BIT_FOR_UCODE_AND_VBIOS_ONLY_IOCTRL0 25 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_LCE 5 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_FLA 0 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_GRAPHICS 1 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_GSP 0 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_IOCTRL 1 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_NVDEC 2 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_NVENC 1 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_NVJPG 0 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_OFA 1 /* */ #define NV_PTOP_DEVICE_INFO_RESET_COUNT_FOR_UCODE_AND_VBIOS_ONLY_SEC 1 /* */ #endif // __ga102_dev_top_h__