/* _NVRM_COPYRIGHT_BEGIN_
 *
 * Copyright 2003-2016 by NVIDIA Corporation.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 *
 * _NVRM_COPYRIGHT_END_
 */

#ifndef __ga102_dev_pri_ringstation_control_gpc_h__
#define __ga102_dev_pri_ringstation_control_gpc_h__
/* This file is autogenerated.  Do not edit */
#define NV_PPRIV_RS_CTRL_GPC                                        0x00127fff:0x00124000 /* RW--D */
#define NV_PPRIV_RS_CTRL_GPC_RING_STATION_SUBSTRATE                            0x00124000 /* R--4R */
#define NV_PPRIV_RS_CTRL_GPC_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION                 4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK                                0x0012405c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION                       3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED    0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED   0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0                0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE         0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE        0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1                1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE         0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE        0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2                2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE         0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE        0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3                3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE         0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE        0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION                      7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED   0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED  0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0               4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE        0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE       0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1               5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE        0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE       0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2               6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE        0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE       0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3               7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE        0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE       0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_VIOLATION                        8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR           0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON             0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION                       9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR          0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON            0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL                 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED           0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED           0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL                11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED          0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED          0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE                       31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST                              0x00124004 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK             0x0012405c /*       */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET                         3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_0                       0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_1                       0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_2                       0x2 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_3                       0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_4                       0x4 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_5                       0x5 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_6                       0x6 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_7                       0x7 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_8                       0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_9                       0x9 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_10                      0xa /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_11                      0xb /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_12                      0xc /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_13                      0xd /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_14                      0xe /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_WIRE_BUCKET_15                      0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_FORCE                               4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_FORCE_ENABLE                        0x1 /* RW--T */
#define NV_PPRIV_RS_CTRL_GPC_FORCE_VW_REBROADCAST_FORCE_DISABLE                       0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_VIRTUAL_WIRE_CONFIG(i)                    (0x00124008+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_GPC_VIRTUAL_WIRE_CONFIG__SIZE_1                               16 /*       */
#define NV_PPRIV_RS_CTRL_GPC_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK              0x0012405c /*       */
#define NV_PPRIV_RS_CTRL_GPC_VIRTUAL_WIRE_CONFIG_TIMER                                7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_VIRTUAL_WIRE_CONFIG_TIMER_RESET                         0x0a /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_VIRTUAL_WIRE_CONFIG_MAX_UPDATES                         15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET                   0x01 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_CG1                                               0x00124048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_CG1_SLCG                                                 1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_CG1_SLCG_ENABLED                                         0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_CG1_SLCG_DISABLED                                        0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_CG1_SLCG__PROD                                           0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_CYA_SETTINGS                                      0x0012404c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_CYA_SETTINGS__PRIV_LEVEL_MASK                     0x0012405c /*       */
#define NV_PPRIV_RS_CTRL_GPC_CYA_SETTINGS_VWIRE_NO_WAKEUP                             0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED                     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED                    0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_CYA_SETTINGS_VWIRE_MAX_UPDATES                           1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED                  0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED                   0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK                    0x00124050 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION           3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0    0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1    1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2    2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3    3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION          7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0   4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1   5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2   6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3   7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION            8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION           9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL     10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL    11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE           31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION                                    0x00124054 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION__PRIV_LEVEL_MASK                   0x00124050 /*       */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_TAG                                       4:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_RS_ENUMERATION_TAG_INIT                                 0x00 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC_RS_MAP_INFO(i)                        (0x001240c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC_RS_MAP_INFO__SIZE_1                                    7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC_RS_MAP_INFO_SMC_ENABLE                             31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE                          0x1 /* R---V */
#define NV_PPRIV_RS_CTRL_GPC_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE                         0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC_RS_MAP_INFO_SMC_ENGINE_ID                            8:8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT                       0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID              2:0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT         0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RING_STATION_SUBSTRATE                       0x00124000 /* R--4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION            4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK                           0x0012405c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION                  3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0           0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1           1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2           2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3           3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION                 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0          4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1          5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2          6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3          7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_VIOLATION                   8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON        0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION                  9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON       0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL            10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL           11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED     0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE                  31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST                         0x00124004 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK        0x0012405c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET                    3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_0                  0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_1                  0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_2                  0x2 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_3                  0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_4                  0x4 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_5                  0x5 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_6                  0x6 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_7                  0x7 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_8                  0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_9                  0x9 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_10                 0xa /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_11                 0xb /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_12                 0xc /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_13                 0xd /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_14                 0xe /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_WIRE_BUCKET_15                 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_FORCE                          4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_FORCE_ENABLE                   0x1 /* RW--T */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_FORCE_VW_REBROADCAST_FORCE_DISABLE                  0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_VIRTUAL_WIRE_CONFIG(i)               (0x00124008+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_VIRTUAL_WIRE_CONFIG__SIZE_1                          16 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK         0x0012405c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_VIRTUAL_WIRE_CONFIG_TIMER                           7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_VIRTUAL_WIRE_CONFIG_TIMER_RESET                    0x0a /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_VIRTUAL_WIRE_CONFIG_MAX_UPDATES                    15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET              0x01 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CG1                                          0x00124048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CG1_SLCG                                            1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CG1_SLCG_ENABLED                                    0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CG1_SLCG_DISABLED                                   0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CG1_SLCG__PROD                                      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CYA_SETTINGS                                 0x0012404c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CYA_SETTINGS__PRIV_LEVEL_MASK                0x0012405c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CYA_SETTINGS_VWIRE_NO_WAKEUP                        0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED                0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED               0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CYA_SETTINGS_VWIRE_MAX_UPDATES                      1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED             0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED              0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK               0x00124050 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION      3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION     7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION       8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION      9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE      31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION                               0x00124054 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION__PRIV_LEVEL_MASK              0x00124050 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_TAG                                  4:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_RS_ENUMERATION_TAG_INIT                            0x00 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_GPC_RS_MAP_INFO(i)                   (0x001240c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_GPC_RS_MAP_INFO__SIZE_1                               7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_GPC_RS_MAP_INFO_SMC_ENABLE                        31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE                     0x1 /* R---V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE                    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_GPC_RS_MAP_INFO_SMC_ENGINE_ID                       8:8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT                  0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID         2:0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC0_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RING_STATION_SUBSTRATE                       0x00124800 /* R--4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION            4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK                           0x0012485c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION                  3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0           0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1           1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2           2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3           3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION                 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0          4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1          5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2          6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3          7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_VIOLATION                   8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON        0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION                  9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON       0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL            10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL           11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED     0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE                  31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST                         0x00124804 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK        0x0012485c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET                    3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_0                  0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_1                  0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_2                  0x2 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_3                  0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_4                  0x4 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_5                  0x5 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_6                  0x6 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_7                  0x7 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_8                  0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_9                  0x9 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_10                 0xa /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_11                 0xb /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_12                 0xc /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_13                 0xd /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_14                 0xe /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_WIRE_BUCKET_15                 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_FORCE                          4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_FORCE_ENABLE                   0x1 /* RW--T */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_FORCE_VW_REBROADCAST_FORCE_DISABLE                  0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_VIRTUAL_WIRE_CONFIG(i)               (0x00124808+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_VIRTUAL_WIRE_CONFIG__SIZE_1                          16 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK         0x0012485c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_VIRTUAL_WIRE_CONFIG_TIMER                           7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_VIRTUAL_WIRE_CONFIG_TIMER_RESET                    0x0a /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_VIRTUAL_WIRE_CONFIG_MAX_UPDATES                    15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET              0x01 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CG1                                          0x00124848 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CG1_SLCG                                            1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CG1_SLCG_ENABLED                                    0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CG1_SLCG_DISABLED                                   0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CG1_SLCG__PROD                                      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CYA_SETTINGS                                 0x0012484c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CYA_SETTINGS__PRIV_LEVEL_MASK                0x0012485c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CYA_SETTINGS_VWIRE_NO_WAKEUP                        0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED                0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED               0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CYA_SETTINGS_VWIRE_MAX_UPDATES                      1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED             0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED              0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK               0x00124850 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION      3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION     7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION       8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION      9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE      31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION                               0x00124854 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION__PRIV_LEVEL_MASK              0x00124850 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_TAG                                  4:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_RS_ENUMERATION_TAG_INIT                            0x00 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_GPC_RS_MAP_INFO(i)                   (0x001248c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_GPC_RS_MAP_INFO__SIZE_1                               7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_GPC_RS_MAP_INFO_SMC_ENABLE                        31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE                     0x1 /* R---V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE                    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_GPC_RS_MAP_INFO_SMC_ENGINE_ID                       8:8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT                  0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID         2:0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC1_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RING_STATION_SUBSTRATE                       0x00125000 /* R--4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION            4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK                           0x0012505c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION                  3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0           0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1           1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2           2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3           3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION                 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0          4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1          5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2          6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3          7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_VIOLATION                   8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON        0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION                  9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON       0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL            10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL           11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED     0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE                  31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST                         0x00125004 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK        0x0012505c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET                    3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_0                  0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_1                  0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_2                  0x2 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_3                  0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_4                  0x4 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_5                  0x5 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_6                  0x6 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_7                  0x7 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_8                  0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_9                  0x9 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_10                 0xa /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_11                 0xb /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_12                 0xc /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_13                 0xd /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_14                 0xe /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_WIRE_BUCKET_15                 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_FORCE                          4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_FORCE_ENABLE                   0x1 /* RW--T */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_FORCE_VW_REBROADCAST_FORCE_DISABLE                  0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_VIRTUAL_WIRE_CONFIG(i)               (0x00125008+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_VIRTUAL_WIRE_CONFIG__SIZE_1                          16 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK         0x0012505c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_VIRTUAL_WIRE_CONFIG_TIMER                           7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_VIRTUAL_WIRE_CONFIG_TIMER_RESET                    0x0a /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_VIRTUAL_WIRE_CONFIG_MAX_UPDATES                    15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET              0x01 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CG1                                          0x00125048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CG1_SLCG                                            1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CG1_SLCG_ENABLED                                    0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CG1_SLCG_DISABLED                                   0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CG1_SLCG__PROD                                      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CYA_SETTINGS                                 0x0012504c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CYA_SETTINGS__PRIV_LEVEL_MASK                0x0012505c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CYA_SETTINGS_VWIRE_NO_WAKEUP                        0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED                0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED               0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CYA_SETTINGS_VWIRE_MAX_UPDATES                      1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED             0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED              0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK               0x00125050 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION      3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION     7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION       8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION      9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE      31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION                               0x00125054 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION__PRIV_LEVEL_MASK              0x00125050 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_TAG                                  4:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_RS_ENUMERATION_TAG_INIT                            0x00 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_GPC_RS_MAP_INFO(i)                   (0x001250c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_GPC_RS_MAP_INFO__SIZE_1                               7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_GPC_RS_MAP_INFO_SMC_ENABLE                        31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE                     0x1 /* R---V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE                    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_GPC_RS_MAP_INFO_SMC_ENGINE_ID                       8:8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT                  0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID         2:0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC2_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RING_STATION_SUBSTRATE                       0x00125800 /* R--4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION            4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK                           0x0012585c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION                  3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0           0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1           1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2           2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3           3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION                 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0          4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1          5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2          6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3          7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_VIOLATION                   8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON        0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION                  9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON       0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL            10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL           11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED     0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE                  31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST                         0x00125804 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK        0x0012585c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET                    3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_0                  0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_1                  0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_2                  0x2 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_3                  0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_4                  0x4 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_5                  0x5 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_6                  0x6 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_7                  0x7 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_8                  0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_9                  0x9 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_10                 0xa /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_11                 0xb /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_12                 0xc /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_13                 0xd /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_14                 0xe /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_WIRE_BUCKET_15                 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_FORCE                          4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_FORCE_ENABLE                   0x1 /* RW--T */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_FORCE_VW_REBROADCAST_FORCE_DISABLE                  0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_VIRTUAL_WIRE_CONFIG(i)               (0x00125808+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_VIRTUAL_WIRE_CONFIG__SIZE_1                          16 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK         0x0012585c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_VIRTUAL_WIRE_CONFIG_TIMER                           7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_VIRTUAL_WIRE_CONFIG_TIMER_RESET                    0x0a /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_VIRTUAL_WIRE_CONFIG_MAX_UPDATES                    15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET              0x01 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CG1                                          0x00125848 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CG1_SLCG                                            1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CG1_SLCG_ENABLED                                    0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CG1_SLCG_DISABLED                                   0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CG1_SLCG__PROD                                      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CYA_SETTINGS                                 0x0012584c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CYA_SETTINGS__PRIV_LEVEL_MASK                0x0012585c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CYA_SETTINGS_VWIRE_NO_WAKEUP                        0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED                0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED               0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CYA_SETTINGS_VWIRE_MAX_UPDATES                      1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED             0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED              0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK               0x00125850 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION      3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION     7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION       8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION      9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE      31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION                               0x00125854 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION__PRIV_LEVEL_MASK              0x00125850 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_TAG                                  4:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_RS_ENUMERATION_TAG_INIT                            0x00 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_GPC_RS_MAP_INFO(i)                   (0x001258c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_GPC_RS_MAP_INFO__SIZE_1                               7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_GPC_RS_MAP_INFO_SMC_ENABLE                        31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE                     0x1 /* R---V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE                    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_GPC_RS_MAP_INFO_SMC_ENGINE_ID                       8:8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT                  0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID         2:0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC3_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RING_STATION_SUBSTRATE                       0x00126000 /* R--4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION            4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK                           0x0012605c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION                  3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0           0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1           1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2           2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3           3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION                 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0          4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1          5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2          6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3          7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_VIOLATION                   8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON        0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION                  9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON       0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL            10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL           11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED     0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE                  31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST                         0x00126004 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK        0x0012605c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET                    3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_0                  0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_1                  0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_2                  0x2 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_3                  0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_4                  0x4 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_5                  0x5 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_6                  0x6 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_7                  0x7 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_8                  0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_9                  0x9 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_10                 0xa /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_11                 0xb /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_12                 0xc /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_13                 0xd /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_14                 0xe /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_WIRE_BUCKET_15                 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_FORCE                          4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_FORCE_ENABLE                   0x1 /* RW--T */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_FORCE_VW_REBROADCAST_FORCE_DISABLE                  0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_VIRTUAL_WIRE_CONFIG(i)               (0x00126008+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_VIRTUAL_WIRE_CONFIG__SIZE_1                          16 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK         0x0012605c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_VIRTUAL_WIRE_CONFIG_TIMER                           7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_VIRTUAL_WIRE_CONFIG_TIMER_RESET                    0x0a /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_VIRTUAL_WIRE_CONFIG_MAX_UPDATES                    15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET              0x01 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CG1                                          0x00126048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CG1_SLCG                                            1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CG1_SLCG_ENABLED                                    0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CG1_SLCG_DISABLED                                   0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CG1_SLCG__PROD                                      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CYA_SETTINGS                                 0x0012604c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CYA_SETTINGS__PRIV_LEVEL_MASK                0x0012605c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CYA_SETTINGS_VWIRE_NO_WAKEUP                        0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED                0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED               0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CYA_SETTINGS_VWIRE_MAX_UPDATES                      1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED             0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED              0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK               0x00126050 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION      3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION     7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION       8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION      9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE      31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION                               0x00126054 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION__PRIV_LEVEL_MASK              0x00126050 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_TAG                                  4:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_RS_ENUMERATION_TAG_INIT                            0x00 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_GPC_RS_MAP_INFO(i)                   (0x001260c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_GPC_RS_MAP_INFO__SIZE_1                               7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_GPC_RS_MAP_INFO_SMC_ENABLE                        31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE                     0x1 /* R---V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE                    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_GPC_RS_MAP_INFO_SMC_ENGINE_ID                       8:8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT                  0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID         2:0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC4_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RING_STATION_SUBSTRATE                       0x00126800 /* R--4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION            4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK                           0x0012685c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION                  3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0           0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1           1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2           2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3           3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION                 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0          4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1          5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2          6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3          7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_VIOLATION                   8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON        0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION                  9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON       0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL            10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL           11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED     0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE                  31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST                         0x00126804 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK        0x0012685c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET                    3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_0                  0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_1                  0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_2                  0x2 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_3                  0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_4                  0x4 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_5                  0x5 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_6                  0x6 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_7                  0x7 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_8                  0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_9                  0x9 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_10                 0xa /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_11                 0xb /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_12                 0xc /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_13                 0xd /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_14                 0xe /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_WIRE_BUCKET_15                 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_FORCE                          4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_FORCE_ENABLE                   0x1 /* RW--T */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_FORCE_VW_REBROADCAST_FORCE_DISABLE                  0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_VIRTUAL_WIRE_CONFIG(i)               (0x00126808+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_VIRTUAL_WIRE_CONFIG__SIZE_1                          16 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK         0x0012685c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_VIRTUAL_WIRE_CONFIG_TIMER                           7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_VIRTUAL_WIRE_CONFIG_TIMER_RESET                    0x0a /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_VIRTUAL_WIRE_CONFIG_MAX_UPDATES                    15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET              0x01 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CG1                                          0x00126848 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CG1_SLCG                                            1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CG1_SLCG_ENABLED                                    0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CG1_SLCG_DISABLED                                   0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CG1_SLCG__PROD                                      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CYA_SETTINGS                                 0x0012684c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CYA_SETTINGS__PRIV_LEVEL_MASK                0x0012685c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CYA_SETTINGS_VWIRE_NO_WAKEUP                        0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED                0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED               0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CYA_SETTINGS_VWIRE_MAX_UPDATES                      1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED             0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED              0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK               0x00126850 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION      3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION     7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION       8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION      9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE      31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION                               0x00126854 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION__PRIV_LEVEL_MASK              0x00126850 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_TAG                                  4:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_RS_ENUMERATION_TAG_INIT                            0x00 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_GPC_RS_MAP_INFO(i)                   (0x001268c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_GPC_RS_MAP_INFO__SIZE_1                               7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_GPC_RS_MAP_INFO_SMC_ENABLE                        31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE                     0x1 /* R---V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE                    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_GPC_RS_MAP_INFO_SMC_ENGINE_ID                       8:8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT                  0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID         2:0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC5_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RING_STATION_SUBSTRATE                       0x00127000 /* R--4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION            4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK                           0x0012705c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION                  3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0           0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1           1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2           2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3           3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE    0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE   0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION                 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0          4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1          5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2          6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3          7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE   0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE  0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_VIOLATION                   8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON        0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION                  9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON       0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL            10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED      0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL           11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED     0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED     0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE                  31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST                         0x00127004 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK        0x0012705c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET                    3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_0                  0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_1                  0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_2                  0x2 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_3                  0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_4                  0x4 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_5                  0x5 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_6                  0x6 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_7                  0x7 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_8                  0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_9                  0x9 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_10                 0xa /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_11                 0xb /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_12                 0xc /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_13                 0xd /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_14                 0xe /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_WIRE_BUCKET_15                 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_FORCE                          4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_FORCE_ENABLE                   0x1 /* RW--T */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_FORCE_VW_REBROADCAST_FORCE_DISABLE                  0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_VIRTUAL_WIRE_CONFIG(i)               (0x00127008+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_VIRTUAL_WIRE_CONFIG__SIZE_1                          16 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK         0x0012705c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_VIRTUAL_WIRE_CONFIG_TIMER                           7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_VIRTUAL_WIRE_CONFIG_TIMER_RESET                    0x0a /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_VIRTUAL_WIRE_CONFIG_MAX_UPDATES                    15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET              0x01 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CG1                                          0x00127048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CG1_SLCG                                            1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CG1_SLCG_ENABLED                                    0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CG1_SLCG_DISABLED                                   0x3 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CG1_SLCG__PROD                                      0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CYA_SETTINGS                                 0x0012704c /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CYA_SETTINGS__PRIV_LEVEL_MASK                0x0012705c /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CYA_SETTINGS_VWIRE_NO_WAKEUP                        0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED                0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED               0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CYA_SETTINGS_VWIRE_MAX_UPDATES                      1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED             0x0 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED              0x1 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK               0x00127050 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION      3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION     7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION       8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION      9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE      31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION                               0x00127054 /* RW-4R */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION__PRIV_LEVEL_MASK              0x00127050 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_TAG                                  4:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_RS_ENUMERATION_TAG_INIT                            0x00 /* RWB-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_GPC_RS_MAP_INFO(i)                   (0x001270c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_GPC_RS_MAP_INFO__SIZE_1                               7 /*       */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_GPC_RS_MAP_INFO_SMC_ENABLE                        31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE                     0x1 /* R---V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE                    0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_GPC_RS_MAP_INFO_SMC_ENGINE_ID                       8:8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT                  0x0 /* R-B-V */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID         2:0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_GPC_GPC6_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT    0x0 /* R-B-V */
#endif // __ga102_dev_pri_ringstation_control_gpc_h__