Add experimental RTX 5090 (GDDR7) memory temperature support
Reads the per-module GDDR7 DRAM sensors (FBPA DQR) directly and reports the hotspot by default; --per-module lists each of the 8 modules. Adds a per-device decode so the existing GDDR6/6X path is unchanged.
This commit is contained in:
8
.gitignore
vendored
8
.gitignore
vendored
@@ -2,3 +2,11 @@ gddr6
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build/
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build/
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*.o
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*.o
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*.a
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*.a
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# local reverse-engineering probes / scratch tools
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probe_*
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probe5090*
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scan_therm*
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measure_gentle*
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memload*
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!*.md
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14
README.md
14
README.md
@@ -3,6 +3,19 @@
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Reads GDDR6/GDDR6X VRAM memory temperatures from multiple supported NVIDIA GPUs found in a host Linux system.
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Reads GDDR6/GDDR6X VRAM memory temperatures from multiple supported NVIDIA GPUs found in a host Linux system.
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These findings are based on reverse engineering of the NVIDIA GPU Linux driver.
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These findings are based on reverse engineering of the NVIDIA GPU Linux driver.
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### Experimental: RTX 5090 (GDDR7)
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Experimental support for the RTX 5090 (Blackwell / GB202, GDDR7) is included. It reads the per-module
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DRAM sensors directly and reports the hotspot (hottest module) by default:
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```
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sudo gddr6 # VRAM hotspot temperature
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sudo gddr6 --per-module # each of the 8 GDDR7 modules separately
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```
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This is reverse-engineered and unofficial (NVIDIA does not expose memory temperature via nvidia-smi/NVML
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on this card) — treat the readings as approximate.
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## Prerequisites
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## Prerequisites
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@@ -46,6 +59,7 @@ sudo gddr6
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```
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```
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## Supported GPUs
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## Supported GPUs
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- RTX 5090 (GB202) — GDDR7, experimental (see above)
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- RTX 4090 (AD102)
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- RTX 4090 (AD102)
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- RTX 4080 Super (AD103)
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- RTX 4080 Super (AD103)
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- RTX 4080 (AD103)
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- RTX 4080 (AD103)
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@@ -2,6 +2,7 @@
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#include "gddr6.h"
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#include "gddr6.h"
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#include <stdio.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <string.h>
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#include <signal.h>
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#include <signal.h>
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void register_signal_handlers(void)
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void register_signal_handlers(void)
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@@ -18,6 +19,21 @@ void register_signal_handlers(void)
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int main(int argc, char **argv)
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int main(int argc, char **argv)
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{
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{
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int per_module = 0;
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for (int i = 1; i < argc; i++)
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{
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if (strcmp(argv[i], "--per-module") == 0)
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per_module = 1;
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else if (strcmp(argv[i], "--help") == 0 || strcmp(argv[i], "-h") == 0)
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{
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printf("Usage: %s [--per-module]\n"
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" (default) show VRAM temperature (Blackwell: hottest module)\n"
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" --per-module show each GDDR7 module separately (Blackwell only)\n",
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argv[0]);
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return 0;
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}
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}
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register_signal_handlers();
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register_signal_handlers();
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gddr6_init();
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gddr6_init();
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int num_devs = gddr6_detect_compatible_gpus();
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int num_devs = gddr6_detect_compatible_gpus();
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@@ -29,7 +45,7 @@ int main(int argc, char **argv)
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}
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}
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gddr6_memory_map();
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gddr6_memory_map();
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gddr6_monitor_temperatures();
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gddr6_monitor_temperatures(per_module);
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return 0;
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return 0;
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}
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}
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@@ -4,11 +4,19 @@
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#include <stdint.h>
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#include <stdint.h>
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// How to convert a raw register read into degrees Celsius.
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enum temp_decode {
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DECODE_ADA = 0, // Ada/Ampere: (raw & 0xfff) / 32
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DECODE_GDDR_MRCODE, // Blackwell FBPA DQR: byte in bits 23:16 is a GDDR temp
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// MR-code; C = (code-20)*2 for code>19, else -(40-code*2)
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};
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struct device
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struct device
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{
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{
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uint32_t bar0;
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uint32_t bar0;
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uint8_t bus, dev, func;
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uint8_t bus, dev, func;
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uint32_t offset;
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uint32_t offset;
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enum temp_decode decode; // how to turn the raw reg into Celsius
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uint16_t dev_id;
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uint16_t dev_id;
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const char *vram;
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const char *vram;
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const char *arch;
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const char *arch;
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@@ -27,7 +35,7 @@ struct gddr6_ctx {
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void gddr6_init(void);
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void gddr6_init(void);
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void gddr6_memory_map(void);
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void gddr6_memory_map(void);
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void gddr6_cleanup(int signal);
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void gddr6_cleanup(int signal);
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void gddr6_monitor_temperatures(void);
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void gddr6_monitor_temperatures(int per_module);
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int gddr6_detect_compatible_gpus(void);
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int gddr6_detect_compatible_gpus(void);
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#endif // GDDR6_H
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#endif // GDDR6_H
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107
lib/src/gddr6.c
107
lib/src/gddr6.c
@@ -11,7 +11,6 @@
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#include <fcntl.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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#include <sys/mman.h>
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#include <pci/pci.h>
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#include <pci/pci.h>
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#include <signal.h>
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#define PG_SZ sysconf(_SC_PAGE_SIZE)
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#define PG_SZ sysconf(_SC_PAGE_SIZE)
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#define PRINT_ERROR() \
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#define PRINT_ERROR() \
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@@ -23,6 +22,7 @@
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#define MAX_DEVICES 32
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#define MAX_DEVICES 32
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struct gddr6_ctx ctx = {0};
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struct gddr6_ctx ctx = {0};
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// Ada/Ampere GPUs: temperature field is bits [11:0], Celsius = field / 32.
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struct device dev_table[] =
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struct device dev_table[] =
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{
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{
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{ .offset = 0x0000E2A8, .dev_id = 0x2684, .vram = "GDDR6X", .arch = "AD102", .name = "RTX 4090" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2684, .vram = "GDDR6X", .arch = "AD102", .name = "RTX 4090" },
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@@ -49,6 +49,14 @@ struct device dev_table[] =
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{ .offset = 0x0000E2A8, .dev_id = 0x27b8, .vram = "GDDR6", .arch = "AD104", .name = "L4" },
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{ .offset = 0x0000E2A8, .dev_id = 0x27b8, .vram = "GDDR6", .arch = "AD104", .name = "L4" },
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{ .offset = 0x0000E2A8, .dev_id = 0x26b9, .vram = "GDDR6", .arch = "AD102", .name = "L40S" },
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{ .offset = 0x0000E2A8, .dev_id = 0x26b9, .vram = "GDDR6", .arch = "AD102", .name = "L40S" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2236, .vram = "GDDR6", .arch = "GA102", .name = "A10" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2236, .vram = "GDDR6", .arch = "GA102", .name = "A10" },
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// Blackwell GDDR7 memory temperature: the raw FBPA DRAM sensor at
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// NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP0 (0x9A24C0) - the register the FBFALCON
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// firmware reads. NOT PLM-locked; reads valid data from userspace (validity
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// bit 24 of 0x9A24D0). The value is a per-device GDDR temp MR-code in bits
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// 23:16; DECODE_GDDR_MRCODE converts it to Celsius. (The documented mem-temp
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// reg 0x9A44B0 is PLM-locked and its 0xE2A8 scratch mirror is unpopulated on
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// this card, so we read the raw sensor directly.)
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{ .offset = 0x009A24C0, .decode = DECODE_GDDR_MRCODE, .dev_id = 0x2b85, .vram = "GDDR7", .arch = "GB202", .name = "RTX 5090" },
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};
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};
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void gddr6_init(void)
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void gddr6_init(void)
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@@ -125,8 +133,77 @@ void gddr6_memory_map(void)
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}
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}
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}
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}
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void gddr6_monitor_temperatures(void)
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// Convert a raw register value to degrees Celsius per the device's decode.
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static int decode_temp(enum temp_decode decode, uint32_t raw)
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{
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{
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switch (decode)
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{
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case DECODE_GDDR_MRCODE:
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{
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// GDDR temp MR-code in bits 23:16 (see NV_PFB_FBPA_DQR_STATUS_DQ).
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// code 20 = 0 C, +2 C per unit above 20; below 20 is negative.
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int code = (raw >> 16) & 0xFF;
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if (code > 80) code = 80;
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return (code > 19) ? (code - 20) * 2 : -(40 - code * 2);
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}
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case DECODE_ADA:
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default:
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return (raw & 0x00000fff) / 0x20;
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}
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}
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// Blackwell GDDR7 per-memory-partition (module) DQR sensors. Module p lives at
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// BAR0 + DQR_MODULE0 + p*DQR_STRIDE; validity nibble (all 4 IC/subp valid = 0xF)
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// is at +DQR_VLD_OFF. Unlike the single pre-mapped register, these span several
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// pages, so they are read on demand with a fresh page-aligned mmap.
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#define DQR_MODULE0 0x009024C0u
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#define DQR_VLD_OFF (0x009024D0u - 0x009024C0u) // +0x10
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#define DQR_STRIDE 0x00004000u
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#define DQR_MAX_MODULES 16
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// Read one 32-bit MMIO register at BAR0+off via a fresh read-only page mmap.
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// Returns 0 on success. Used only for the on-demand per-module GDDR7 reads.
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static int read_bar0_reg(uint32_t bar0, uint32_t off, uint32_t *out)
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{
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long pg = PG_SZ;
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uint64_t phys = (uint64_t)bar0 + off;
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uint64_t base = phys & ~((uint64_t)pg - 1);
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volatile void *map = mmap(0, pg, PROT_READ, MAP_SHARED, ctx.fd, base);
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if (map == MAP_FAILED) return -1;
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*out = *(volatile uint32_t *)((const uint8_t *)map + (phys - base));
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munmap((void *)map, pg);
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return 0;
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}
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// Read the GDDR7 modules for a Blackwell device. Fills temps[]/present[] for up
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// to DQR_MAX_MODULES, returns the module count found and the hottest temp in
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// *hottest. A module counts as present only if all 4 DQR valid bits are set and
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// the data word is not the 0xBADF.... poison sentinel.
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static int gddr7_read_modules(uint32_t bar0, int temps[], int *hottest)
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{
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int count = 0, hot = -128;
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for (int p = 0; p < DQR_MAX_MODULES; p++)
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{
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uint32_t off = DQR_MODULE0 + (uint32_t)p * DQR_STRIDE;
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uint32_t vld = 0, dq = 0;
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if (read_bar0_reg(bar0, off + DQR_VLD_OFF, &vld) != 0) continue;
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if (read_bar0_reg(bar0, off, &dq) != 0) continue;
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int all_valid = (((vld >> 24) & 0xF) == 0xF);
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int poison = ((dq & 0xFFFF0000u) == 0xBADF0000u);
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if (!all_valid || poison) continue;
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int c = decode_temp(DECODE_GDDR_MRCODE, dq);
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temps[count++] = c;
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if (c > hot) hot = c;
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}
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*hottest = hot;
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return count;
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}
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void gddr6_monitor_temperatures(int per_module)
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{
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int temps[DQR_MAX_MODULES];
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while (1) {
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while (1) {
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printf("\rVRAM Temps: |");
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printf("\rVRAM Temps: |");
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for (uint32_t i = 0; i < ctx.num_devices; i++)
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for (uint32_t i = 0; i < ctx.num_devices; i++)
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@@ -136,11 +213,31 @@ void gddr6_monitor_temperatures(void)
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continue;
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continue;
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}
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}
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// Blackwell GDDR7: per-module DQR sensors. Default shows the hotspot
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// (max across modules); --per-module lists each module.
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if (ctx.devices[i].decode == DECODE_GDDR_MRCODE)
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{
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int hottest = 0;
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int n = gddr7_read_modules(ctx.devices[i].bar0, temps, &hottest);
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if (n == 0) { printf(" n/a |"); continue; }
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if (per_module)
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{
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for (int m = 0; m < n; m++)
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printf(" m%d=%3d°C |", m, temps[m]);
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}
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else
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{
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printf(" %3d°C (hotspot) |", hottest);
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}
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continue;
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}
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// Ada/Ampere: single pre-mapped VRAM register.
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void *virt_addr = (uint8_t *) ctx.devices[i].mapped_addr + (ctx.devices[i].phys_addr - ctx.devices[i].base_offset);
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void *virt_addr = (uint8_t *) ctx.devices[i].mapped_addr + (ctx.devices[i].phys_addr - ctx.devices[i].base_offset);
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uint32_t read_result = *((uint32_t *)virt_addr);
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uint32_t read_result = *((uint32_t *)virt_addr);
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uint32_t temp = ((read_result & 0x00000fff) / 0x20);
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int temp = decode_temp(ctx.devices[i].decode, read_result);
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printf(" %3d°C |", temp);
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printf(" %3u°C |", temp);
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}
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}
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fflush(stdout);
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fflush(stdout);
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sleep(1);
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sleep(1);
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Reference in New Issue
Block a user