first commit
This commit is contained in:
Ole Algoritme
330
include/ampere/ga102/user_access_map_gpc_regranges.h
Normal file
330
include/ampere/ga102/user_access_map_gpc_regranges.h
Normal file
@@ -0,0 +1,330 @@
|
||||
|
||||
|
||||
|
||||
#ifndef ACCESS_MAP_REGISTER_RANGE
|
||||
#define ACCESS_MAP_REGISTER_RANGE(start, end)
|
||||
#endif
|
||||
#ifdef GPC_UNICAST_FULL
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500384, 0x500384) // (NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5004a0, 0x5004a0) // (NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500604, 0x500604) // (NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500680, 0x500680) // (NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500714, 0x500714) // (NV_PGRAPH_PRI_GPC0_TC_PM_CTRL, NV_PGRAPH_PRI_GPC0_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50081c, 0x50081c) // (NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500884, 0x500884) // (NV_PGRAPH_PRI_GPC0_MMU_PM, NV_PGRAPH_PRI_GPC0_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5008c8, 0x5008cc) // (NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500b04, 0x500b04) // (NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500c04, 0x500c04) // (NV_PGRAPH_PRI_GPC0_GPM_PD_PM, NV_PGRAPH_PRI_GPC0_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500c88, 0x500c88) // (NV_PGRAPH_PRI_GPC0_GPM_SD_PM, NV_PGRAPH_PRI_GPC0_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500d00, 0x500d00) // (NV_PGRAPH_PRI_GPC0_GPM_RPT_PM, NV_PGRAPH_PRI_GPC0_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500e08, 0x500e08) // (NV_PGRAPH_PRI_GPC0_SWDX_PM, NV_PGRAPH_PRI_GPC0_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500f08, 0x500f08) // (NV_PGRAPH_PRI_GPC0_WDXPS_PM, NV_PGRAPH_PRI_GPC0_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50100c, 0x50100c) // (NV_PGRAPH_PRI_GPC0_GCC_PERFMON, NV_PGRAPH_PRI_GPC0_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5020a8, 0x5020a8) // (NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5028a0, 0x5028a8) // (NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508384, 0x508384) // (NV_PGRAPH_PRI_GPC1_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC1_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5084a0, 0x5084a0) // (NV_PGRAPH_PRI_GPC1_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC1_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508604, 0x508604) // (NV_PGRAPH_PRI_GPC1_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC1_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508680, 0x508680) // (NV_PGRAPH_PRI_GPC1_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC1_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508714, 0x508714) // (NV_PGRAPH_PRI_GPC1_TC_PM_CTRL, NV_PGRAPH_PRI_GPC1_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50881c, 0x50881c) // (NV_PGRAPH_PRI_GPC1_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC1_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508884, 0x508884) // (NV_PGRAPH_PRI_GPC1_MMU_PM, NV_PGRAPH_PRI_GPC1_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5088c8, 0x5088cc) // (NV_PGRAPH_PRI_GPC1_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC1_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508b04, 0x508b04) // (NV_PGRAPH_PRI_GPC1_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC1_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508c04, 0x508c04) // (NV_PGRAPH_PRI_GPC1_GPM_PD_PM, NV_PGRAPH_PRI_GPC1_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508c88, 0x508c88) // (NV_PGRAPH_PRI_GPC1_GPM_SD_PM, NV_PGRAPH_PRI_GPC1_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508d00, 0x508d00) // (NV_PGRAPH_PRI_GPC1_GPM_RPT_PM, NV_PGRAPH_PRI_GPC1_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508e08, 0x508e08) // (NV_PGRAPH_PRI_GPC1_SWDX_PM, NV_PGRAPH_PRI_GPC1_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508f08, 0x508f08) // (NV_PGRAPH_PRI_GPC1_WDXPS_PM, NV_PGRAPH_PRI_GPC1_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50900c, 0x50900c) // (NV_PGRAPH_PRI_GPC1_GCC_PERFMON, NV_PGRAPH_PRI_GPC1_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50a0a8, 0x50a0a8) // (NV_PGRAPH_PRI_GPC1_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC1_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50a8a0, 0x50a8a8) // (NV_PGRAPH_PRI_GPC1_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC1_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510384, 0x510384) // (NV_PGRAPH_PRI_GPC2_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC2_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5104a0, 0x5104a0) // (NV_PGRAPH_PRI_GPC2_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC2_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510604, 0x510604) // (NV_PGRAPH_PRI_GPC2_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC2_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510680, 0x510680) // (NV_PGRAPH_PRI_GPC2_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC2_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510714, 0x510714) // (NV_PGRAPH_PRI_GPC2_TC_PM_CTRL, NV_PGRAPH_PRI_GPC2_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51081c, 0x51081c) // (NV_PGRAPH_PRI_GPC2_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC2_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510884, 0x510884) // (NV_PGRAPH_PRI_GPC2_MMU_PM, NV_PGRAPH_PRI_GPC2_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5108c8, 0x5108cc) // (NV_PGRAPH_PRI_GPC2_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC2_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510b04, 0x510b04) // (NV_PGRAPH_PRI_GPC2_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC2_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510c04, 0x510c04) // (NV_PGRAPH_PRI_GPC2_GPM_PD_PM, NV_PGRAPH_PRI_GPC2_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510c88, 0x510c88) // (NV_PGRAPH_PRI_GPC2_GPM_SD_PM, NV_PGRAPH_PRI_GPC2_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510d00, 0x510d00) // (NV_PGRAPH_PRI_GPC2_GPM_RPT_PM, NV_PGRAPH_PRI_GPC2_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510e08, 0x510e08) // (NV_PGRAPH_PRI_GPC2_SWDX_PM, NV_PGRAPH_PRI_GPC2_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510f08, 0x510f08) // (NV_PGRAPH_PRI_GPC2_WDXPS_PM, NV_PGRAPH_PRI_GPC2_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51100c, 0x51100c) // (NV_PGRAPH_PRI_GPC2_GCC_PERFMON, NV_PGRAPH_PRI_GPC2_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5120a8, 0x5120a8) // (NV_PGRAPH_PRI_GPC2_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC2_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5128a0, 0x5128a8) // (NV_PGRAPH_PRI_GPC2_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC2_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518384, 0x518384) // (NV_PGRAPH_PRI_GPC3_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC3_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5184a0, 0x5184a0) // (NV_PGRAPH_PRI_GPC3_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC3_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518604, 0x518604) // (NV_PGRAPH_PRI_GPC3_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC3_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518680, 0x518680) // (NV_PGRAPH_PRI_GPC3_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC3_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518714, 0x518714) // (NV_PGRAPH_PRI_GPC3_TC_PM_CTRL, NV_PGRAPH_PRI_GPC3_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51881c, 0x51881c) // (NV_PGRAPH_PRI_GPC3_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC3_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518884, 0x518884) // (NV_PGRAPH_PRI_GPC3_MMU_PM, NV_PGRAPH_PRI_GPC3_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5188c8, 0x5188cc) // (NV_PGRAPH_PRI_GPC3_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC3_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518b04, 0x518b04) // (NV_PGRAPH_PRI_GPC3_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC3_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518c04, 0x518c04) // (NV_PGRAPH_PRI_GPC3_GPM_PD_PM, NV_PGRAPH_PRI_GPC3_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518c88, 0x518c88) // (NV_PGRAPH_PRI_GPC3_GPM_SD_PM, NV_PGRAPH_PRI_GPC3_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518d00, 0x518d00) // (NV_PGRAPH_PRI_GPC3_GPM_RPT_PM, NV_PGRAPH_PRI_GPC3_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518e08, 0x518e08) // (NV_PGRAPH_PRI_GPC3_SWDX_PM, NV_PGRAPH_PRI_GPC3_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518f08, 0x518f08) // (NV_PGRAPH_PRI_GPC3_WDXPS_PM, NV_PGRAPH_PRI_GPC3_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51900c, 0x51900c) // (NV_PGRAPH_PRI_GPC3_GCC_PERFMON, NV_PGRAPH_PRI_GPC3_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51a0a8, 0x51a0a8) // (NV_PGRAPH_PRI_GPC3_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC3_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51a8a0, 0x51a8a8) // (NV_PGRAPH_PRI_GPC3_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC3_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520384, 0x520384) // (NV_PGRAPH_PRI_GPC4_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC4_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5204a0, 0x5204a0) // (NV_PGRAPH_PRI_GPC4_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC4_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520604, 0x520604) // (NV_PGRAPH_PRI_GPC4_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC4_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520680, 0x520680) // (NV_PGRAPH_PRI_GPC4_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC4_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520714, 0x520714) // (NV_PGRAPH_PRI_GPC4_TC_PM_CTRL, NV_PGRAPH_PRI_GPC4_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x52081c, 0x52081c) // (NV_PGRAPH_PRI_GPC4_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC4_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520884, 0x520884) // (NV_PGRAPH_PRI_GPC4_MMU_PM, NV_PGRAPH_PRI_GPC4_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5208c8, 0x5208cc) // (NV_PGRAPH_PRI_GPC4_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC4_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520b04, 0x520b04) // (NV_PGRAPH_PRI_GPC4_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC4_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520c04, 0x520c04) // (NV_PGRAPH_PRI_GPC4_GPM_PD_PM, NV_PGRAPH_PRI_GPC4_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520c88, 0x520c88) // (NV_PGRAPH_PRI_GPC4_GPM_SD_PM, NV_PGRAPH_PRI_GPC4_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520d00, 0x520d00) // (NV_PGRAPH_PRI_GPC4_GPM_RPT_PM, NV_PGRAPH_PRI_GPC4_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520e08, 0x520e08) // (NV_PGRAPH_PRI_GPC4_SWDX_PM, NV_PGRAPH_PRI_GPC4_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x520f08, 0x520f08) // (NV_PGRAPH_PRI_GPC4_WDXPS_PM, NV_PGRAPH_PRI_GPC4_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x52100c, 0x52100c) // (NV_PGRAPH_PRI_GPC4_GCC_PERFMON, NV_PGRAPH_PRI_GPC4_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5220a8, 0x5220a8) // (NV_PGRAPH_PRI_GPC4_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC4_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5228a0, 0x5228a8) // (NV_PGRAPH_PRI_GPC4_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC4_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528384, 0x528384) // (NV_PGRAPH_PRI_GPC5_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC5_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5284a0, 0x5284a0) // (NV_PGRAPH_PRI_GPC5_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC5_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528604, 0x528604) // (NV_PGRAPH_PRI_GPC5_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC5_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528680, 0x528680) // (NV_PGRAPH_PRI_GPC5_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC5_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528714, 0x528714) // (NV_PGRAPH_PRI_GPC5_TC_PM_CTRL, NV_PGRAPH_PRI_GPC5_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x52881c, 0x52881c) // (NV_PGRAPH_PRI_GPC5_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC5_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528884, 0x528884) // (NV_PGRAPH_PRI_GPC5_MMU_PM, NV_PGRAPH_PRI_GPC5_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5288c8, 0x5288cc) // (NV_PGRAPH_PRI_GPC5_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC5_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528b04, 0x528b04) // (NV_PGRAPH_PRI_GPC5_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC5_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528c04, 0x528c04) // (NV_PGRAPH_PRI_GPC5_GPM_PD_PM, NV_PGRAPH_PRI_GPC5_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528c88, 0x528c88) // (NV_PGRAPH_PRI_GPC5_GPM_SD_PM, NV_PGRAPH_PRI_GPC5_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528d00, 0x528d00) // (NV_PGRAPH_PRI_GPC5_GPM_RPT_PM, NV_PGRAPH_PRI_GPC5_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528e08, 0x528e08) // (NV_PGRAPH_PRI_GPC5_SWDX_PM, NV_PGRAPH_PRI_GPC5_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x528f08, 0x528f08) // (NV_PGRAPH_PRI_GPC5_WDXPS_PM, NV_PGRAPH_PRI_GPC5_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x52900c, 0x52900c) // (NV_PGRAPH_PRI_GPC5_GCC_PERFMON, NV_PGRAPH_PRI_GPC5_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x52a0a8, 0x52a0a8) // (NV_PGRAPH_PRI_GPC5_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC5_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x52a8a0, 0x52a8a8) // (NV_PGRAPH_PRI_GPC5_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC5_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530384, 0x530384) // (NV_PGRAPH_PRI_GPC6_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC6_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5304a0, 0x5304a0) // (NV_PGRAPH_PRI_GPC6_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC6_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530604, 0x530604) // (NV_PGRAPH_PRI_GPC6_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC6_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530680, 0x530680) // (NV_PGRAPH_PRI_GPC6_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC6_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530714, 0x530714) // (NV_PGRAPH_PRI_GPC6_TC_PM_CTRL, NV_PGRAPH_PRI_GPC6_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x53081c, 0x53081c) // (NV_PGRAPH_PRI_GPC6_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC6_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530884, 0x530884) // (NV_PGRAPH_PRI_GPC6_MMU_PM, NV_PGRAPH_PRI_GPC6_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5308c8, 0x5308cc) // (NV_PGRAPH_PRI_GPC6_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC6_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530b04, 0x530b04) // (NV_PGRAPH_PRI_GPC6_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC6_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530c04, 0x530c04) // (NV_PGRAPH_PRI_GPC6_GPM_PD_PM, NV_PGRAPH_PRI_GPC6_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530c88, 0x530c88) // (NV_PGRAPH_PRI_GPC6_GPM_SD_PM, NV_PGRAPH_PRI_GPC6_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530d00, 0x530d00) // (NV_PGRAPH_PRI_GPC6_GPM_RPT_PM, NV_PGRAPH_PRI_GPC6_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530e08, 0x530e08) // (NV_PGRAPH_PRI_GPC6_SWDX_PM, NV_PGRAPH_PRI_GPC6_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x530f08, 0x530f08) // (NV_PGRAPH_PRI_GPC6_WDXPS_PM, NV_PGRAPH_PRI_GPC6_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x53100c, 0x53100c) // (NV_PGRAPH_PRI_GPC6_GCC_PERFMON, NV_PGRAPH_PRI_GPC6_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5320a8, 0x5320a8) // (NV_PGRAPH_PRI_GPC6_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC6_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5328a0, 0x5328a8) // (NV_PGRAPH_PRI_GPC6_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC6_GPCCS_PERFMON_PM)
|
||||
#endif
|
||||
#ifdef GPC_UNICAST_HALF
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500384, 0x500384) // (NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5004a0, 0x5004a0) // (NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500604, 0x500604) // (NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500680, 0x500680) // (NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500714, 0x500714) // (NV_PGRAPH_PRI_GPC0_TC_PM_CTRL, NV_PGRAPH_PRI_GPC0_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50081c, 0x50081c) // (NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500884, 0x500884) // (NV_PGRAPH_PRI_GPC0_MMU_PM, NV_PGRAPH_PRI_GPC0_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5008c8, 0x5008cc) // (NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500b04, 0x500b04) // (NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500c04, 0x500c04) // (NV_PGRAPH_PRI_GPC0_GPM_PD_PM, NV_PGRAPH_PRI_GPC0_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500c88, 0x500c88) // (NV_PGRAPH_PRI_GPC0_GPM_SD_PM, NV_PGRAPH_PRI_GPC0_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500d00, 0x500d00) // (NV_PGRAPH_PRI_GPC0_GPM_RPT_PM, NV_PGRAPH_PRI_GPC0_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500e08, 0x500e08) // (NV_PGRAPH_PRI_GPC0_SWDX_PM, NV_PGRAPH_PRI_GPC0_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500f08, 0x500f08) // (NV_PGRAPH_PRI_GPC0_WDXPS_PM, NV_PGRAPH_PRI_GPC0_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50100c, 0x50100c) // (NV_PGRAPH_PRI_GPC0_GCC_PERFMON, NV_PGRAPH_PRI_GPC0_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5020a8, 0x5020a8) // (NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5028a0, 0x5028a8) // (NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508384, 0x508384) // (NV_PGRAPH_PRI_GPC1_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC1_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5084a0, 0x5084a0) // (NV_PGRAPH_PRI_GPC1_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC1_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508604, 0x508604) // (NV_PGRAPH_PRI_GPC1_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC1_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508680, 0x508680) // (NV_PGRAPH_PRI_GPC1_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC1_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508714, 0x508714) // (NV_PGRAPH_PRI_GPC1_TC_PM_CTRL, NV_PGRAPH_PRI_GPC1_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50881c, 0x50881c) // (NV_PGRAPH_PRI_GPC1_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC1_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508884, 0x508884) // (NV_PGRAPH_PRI_GPC1_MMU_PM, NV_PGRAPH_PRI_GPC1_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5088c8, 0x5088cc) // (NV_PGRAPH_PRI_GPC1_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC1_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508b04, 0x508b04) // (NV_PGRAPH_PRI_GPC1_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC1_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508c04, 0x508c04) // (NV_PGRAPH_PRI_GPC1_GPM_PD_PM, NV_PGRAPH_PRI_GPC1_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508c88, 0x508c88) // (NV_PGRAPH_PRI_GPC1_GPM_SD_PM, NV_PGRAPH_PRI_GPC1_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508d00, 0x508d00) // (NV_PGRAPH_PRI_GPC1_GPM_RPT_PM, NV_PGRAPH_PRI_GPC1_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508e08, 0x508e08) // (NV_PGRAPH_PRI_GPC1_SWDX_PM, NV_PGRAPH_PRI_GPC1_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508f08, 0x508f08) // (NV_PGRAPH_PRI_GPC1_WDXPS_PM, NV_PGRAPH_PRI_GPC1_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50900c, 0x50900c) // (NV_PGRAPH_PRI_GPC1_GCC_PERFMON, NV_PGRAPH_PRI_GPC1_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50a0a8, 0x50a0a8) // (NV_PGRAPH_PRI_GPC1_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC1_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50a8a0, 0x50a8a8) // (NV_PGRAPH_PRI_GPC1_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC1_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510384, 0x510384) // (NV_PGRAPH_PRI_GPC2_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC2_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5104a0, 0x5104a0) // (NV_PGRAPH_PRI_GPC2_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC2_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510604, 0x510604) // (NV_PGRAPH_PRI_GPC2_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC2_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510680, 0x510680) // (NV_PGRAPH_PRI_GPC2_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC2_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510714, 0x510714) // (NV_PGRAPH_PRI_GPC2_TC_PM_CTRL, NV_PGRAPH_PRI_GPC2_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51081c, 0x51081c) // (NV_PGRAPH_PRI_GPC2_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC2_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510884, 0x510884) // (NV_PGRAPH_PRI_GPC2_MMU_PM, NV_PGRAPH_PRI_GPC2_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5108c8, 0x5108cc) // (NV_PGRAPH_PRI_GPC2_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC2_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510b04, 0x510b04) // (NV_PGRAPH_PRI_GPC2_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC2_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510c04, 0x510c04) // (NV_PGRAPH_PRI_GPC2_GPM_PD_PM, NV_PGRAPH_PRI_GPC2_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510c88, 0x510c88) // (NV_PGRAPH_PRI_GPC2_GPM_SD_PM, NV_PGRAPH_PRI_GPC2_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510d00, 0x510d00) // (NV_PGRAPH_PRI_GPC2_GPM_RPT_PM, NV_PGRAPH_PRI_GPC2_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510e08, 0x510e08) // (NV_PGRAPH_PRI_GPC2_SWDX_PM, NV_PGRAPH_PRI_GPC2_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x510f08, 0x510f08) // (NV_PGRAPH_PRI_GPC2_WDXPS_PM, NV_PGRAPH_PRI_GPC2_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51100c, 0x51100c) // (NV_PGRAPH_PRI_GPC2_GCC_PERFMON, NV_PGRAPH_PRI_GPC2_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5120a8, 0x5120a8) // (NV_PGRAPH_PRI_GPC2_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC2_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5128a0, 0x5128a8) // (NV_PGRAPH_PRI_GPC2_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC2_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518384, 0x518384) // (NV_PGRAPH_PRI_GPC3_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC3_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5184a0, 0x5184a0) // (NV_PGRAPH_PRI_GPC3_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC3_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518604, 0x518604) // (NV_PGRAPH_PRI_GPC3_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC3_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518680, 0x518680) // (NV_PGRAPH_PRI_GPC3_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC3_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518714, 0x518714) // (NV_PGRAPH_PRI_GPC3_TC_PM_CTRL, NV_PGRAPH_PRI_GPC3_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51881c, 0x51881c) // (NV_PGRAPH_PRI_GPC3_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC3_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518884, 0x518884) // (NV_PGRAPH_PRI_GPC3_MMU_PM, NV_PGRAPH_PRI_GPC3_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5188c8, 0x5188cc) // (NV_PGRAPH_PRI_GPC3_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC3_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518b04, 0x518b04) // (NV_PGRAPH_PRI_GPC3_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC3_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518c04, 0x518c04) // (NV_PGRAPH_PRI_GPC3_GPM_PD_PM, NV_PGRAPH_PRI_GPC3_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518c88, 0x518c88) // (NV_PGRAPH_PRI_GPC3_GPM_SD_PM, NV_PGRAPH_PRI_GPC3_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518d00, 0x518d00) // (NV_PGRAPH_PRI_GPC3_GPM_RPT_PM, NV_PGRAPH_PRI_GPC3_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518e08, 0x518e08) // (NV_PGRAPH_PRI_GPC3_SWDX_PM, NV_PGRAPH_PRI_GPC3_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x518f08, 0x518f08) // (NV_PGRAPH_PRI_GPC3_WDXPS_PM, NV_PGRAPH_PRI_GPC3_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51900c, 0x51900c) // (NV_PGRAPH_PRI_GPC3_GCC_PERFMON, NV_PGRAPH_PRI_GPC3_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51a0a8, 0x51a0a8) // (NV_PGRAPH_PRI_GPC3_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC3_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x51a8a0, 0x51a8a8) // (NV_PGRAPH_PRI_GPC3_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC3_GPCCS_PERFMON_PM)
|
||||
#endif
|
||||
#ifdef GPC_UNICAST_QUARTER
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500384, 0x500384) // (NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5004a0, 0x5004a0) // (NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500604, 0x500604) // (NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500680, 0x500680) // (NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500714, 0x500714) // (NV_PGRAPH_PRI_GPC0_TC_PM_CTRL, NV_PGRAPH_PRI_GPC0_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50081c, 0x50081c) // (NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500884, 0x500884) // (NV_PGRAPH_PRI_GPC0_MMU_PM, NV_PGRAPH_PRI_GPC0_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5008c8, 0x5008cc) // (NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500b04, 0x500b04) // (NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500c04, 0x500c04) // (NV_PGRAPH_PRI_GPC0_GPM_PD_PM, NV_PGRAPH_PRI_GPC0_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500c88, 0x500c88) // (NV_PGRAPH_PRI_GPC0_GPM_SD_PM, NV_PGRAPH_PRI_GPC0_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500d00, 0x500d00) // (NV_PGRAPH_PRI_GPC0_GPM_RPT_PM, NV_PGRAPH_PRI_GPC0_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500e08, 0x500e08) // (NV_PGRAPH_PRI_GPC0_SWDX_PM, NV_PGRAPH_PRI_GPC0_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500f08, 0x500f08) // (NV_PGRAPH_PRI_GPC0_WDXPS_PM, NV_PGRAPH_PRI_GPC0_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50100c, 0x50100c) // (NV_PGRAPH_PRI_GPC0_GCC_PERFMON, NV_PGRAPH_PRI_GPC0_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5020a8, 0x5020a8) // (NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5028a0, 0x5028a8) // (NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508384, 0x508384) // (NV_PGRAPH_PRI_GPC1_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC1_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5084a0, 0x5084a0) // (NV_PGRAPH_PRI_GPC1_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC1_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508604, 0x508604) // (NV_PGRAPH_PRI_GPC1_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC1_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508680, 0x508680) // (NV_PGRAPH_PRI_GPC1_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC1_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508714, 0x508714) // (NV_PGRAPH_PRI_GPC1_TC_PM_CTRL, NV_PGRAPH_PRI_GPC1_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50881c, 0x50881c) // (NV_PGRAPH_PRI_GPC1_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC1_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508884, 0x508884) // (NV_PGRAPH_PRI_GPC1_MMU_PM, NV_PGRAPH_PRI_GPC1_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5088c8, 0x5088cc) // (NV_PGRAPH_PRI_GPC1_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC1_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508b04, 0x508b04) // (NV_PGRAPH_PRI_GPC1_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC1_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508c04, 0x508c04) // (NV_PGRAPH_PRI_GPC1_GPM_PD_PM, NV_PGRAPH_PRI_GPC1_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508c88, 0x508c88) // (NV_PGRAPH_PRI_GPC1_GPM_SD_PM, NV_PGRAPH_PRI_GPC1_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508d00, 0x508d00) // (NV_PGRAPH_PRI_GPC1_GPM_RPT_PM, NV_PGRAPH_PRI_GPC1_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508e08, 0x508e08) // (NV_PGRAPH_PRI_GPC1_SWDX_PM, NV_PGRAPH_PRI_GPC1_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x508f08, 0x508f08) // (NV_PGRAPH_PRI_GPC1_WDXPS_PM, NV_PGRAPH_PRI_GPC1_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50900c, 0x50900c) // (NV_PGRAPH_PRI_GPC1_GCC_PERFMON, NV_PGRAPH_PRI_GPC1_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50a0a8, 0x50a0a8) // (NV_PGRAPH_PRI_GPC1_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC1_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50a8a0, 0x50a8a8) // (NV_PGRAPH_PRI_GPC1_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC1_GPCCS_PERFMON_PM)
|
||||
#endif
|
||||
#ifdef GPC_UNICAST_EIGHTH
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500384, 0x500384) // (NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPC0_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5004a0, 0x5004a0) // (NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL, NV_PGRAPH_PRI_GPC0_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500604, 0x500604) // (NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC0_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500680, 0x500680) // (NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPC0_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500714, 0x500714) // (NV_PGRAPH_PRI_GPC0_TC_PM_CTRL, NV_PGRAPH_PRI_GPC0_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50081c, 0x50081c) // (NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPC0_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500884, 0x500884) // (NV_PGRAPH_PRI_GPC0_MMU_PM, NV_PGRAPH_PRI_GPC0_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5008c8, 0x5008cc) // (NV_PGRAPH_PRI_GPC0_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPC0_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500b04, 0x500b04) // (NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPC0_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500c04, 0x500c04) // (NV_PGRAPH_PRI_GPC0_GPM_PD_PM, NV_PGRAPH_PRI_GPC0_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500c88, 0x500c88) // (NV_PGRAPH_PRI_GPC0_GPM_SD_PM, NV_PGRAPH_PRI_GPC0_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500d00, 0x500d00) // (NV_PGRAPH_PRI_GPC0_GPM_RPT_PM, NV_PGRAPH_PRI_GPC0_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500e08, 0x500e08) // (NV_PGRAPH_PRI_GPC0_SWDX_PM, NV_PGRAPH_PRI_GPC0_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x500f08, 0x500f08) // (NV_PGRAPH_PRI_GPC0_WDXPS_PM, NV_PGRAPH_PRI_GPC0_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x50100c, 0x50100c) // (NV_PGRAPH_PRI_GPC0_GCC_PERFMON, NV_PGRAPH_PRI_GPC0_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5020a8, 0x5020a8) // (NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPC0_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x5028a0, 0x5028a8) // (NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON, NV_PGRAPH_PRI_GPC0_GPCCS_PERFMON_PM)
|
||||
#endif
|
||||
|
||||
#ifdef GPC_BROADCAST_FULL
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418384, 0x418384) // (NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x4184a0, 0x4184a0) // (NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL, NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418604, 0x418604) // (NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418680, 0x418680) // (NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418714, 0x418714) // (NV_PGRAPH_PRI_GPCS_TC_PM_CTRL, NV_PGRAPH_PRI_GPCS_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41881c, 0x41881c) // (NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418884, 0x418884) // (NV_PGRAPH_PRI_GPCS_MMU_PM, NV_PGRAPH_PRI_GPCS_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x4188c8, 0x4188cc) // (NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418b04, 0x418b04) // (NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418c04, 0x418c04) // (NV_PGRAPH_PRI_GPCS_GPM_PD_PM, NV_PGRAPH_PRI_GPCS_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418c88, 0x418c88) // (NV_PGRAPH_PRI_GPCS_GPM_SD_PM, NV_PGRAPH_PRI_GPCS_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418d00, 0x418d00) // (NV_PGRAPH_PRI_GPCS_GPM_RPT_PM, NV_PGRAPH_PRI_GPCS_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418e08, 0x418e08) // (NV_PGRAPH_PRI_GPCS_SWDX_PM, NV_PGRAPH_PRI_GPCS_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418f08, 0x418f08) // (NV_PGRAPH_PRI_GPCS_WDXPS_PM, NV_PGRAPH_PRI_GPCS_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41900c, 0x41900c) // (NV_PGRAPH_PRI_GPCS_GCC_PERFMON, NV_PGRAPH_PRI_GPCS_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41a0a8, 0x41a0a8) // (NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41a8a0, 0x41a8a8) // (NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON, NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM)
|
||||
#endif
|
||||
#ifdef GPC_BROADCAST_HALF
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418384, 0x418384) // (NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x4184a0, 0x4184a0) // (NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL, NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418604, 0x418604) // (NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418680, 0x418680) // (NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418714, 0x418714) // (NV_PGRAPH_PRI_GPCS_TC_PM_CTRL, NV_PGRAPH_PRI_GPCS_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41881c, 0x41881c) // (NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418884, 0x418884) // (NV_PGRAPH_PRI_GPCS_MMU_PM, NV_PGRAPH_PRI_GPCS_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x4188c8, 0x4188cc) // (NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418b04, 0x418b04) // (NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418c04, 0x418c04) // (NV_PGRAPH_PRI_GPCS_GPM_PD_PM, NV_PGRAPH_PRI_GPCS_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418c88, 0x418c88) // (NV_PGRAPH_PRI_GPCS_GPM_SD_PM, NV_PGRAPH_PRI_GPCS_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418d00, 0x418d00) // (NV_PGRAPH_PRI_GPCS_GPM_RPT_PM, NV_PGRAPH_PRI_GPCS_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418e08, 0x418e08) // (NV_PGRAPH_PRI_GPCS_SWDX_PM, NV_PGRAPH_PRI_GPCS_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418f08, 0x418f08) // (NV_PGRAPH_PRI_GPCS_WDXPS_PM, NV_PGRAPH_PRI_GPCS_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41900c, 0x41900c) // (NV_PGRAPH_PRI_GPCS_GCC_PERFMON, NV_PGRAPH_PRI_GPCS_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41a0a8, 0x41a0a8) // (NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41a8a0, 0x41a8a8) // (NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON, NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM)
|
||||
#endif
|
||||
#ifdef GPC_BROADCAST_QUARTER
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418384, 0x418384) // (NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x4184a0, 0x4184a0) // (NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL, NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418604, 0x418604) // (NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418680, 0x418680) // (NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418714, 0x418714) // (NV_PGRAPH_PRI_GPCS_TC_PM_CTRL, NV_PGRAPH_PRI_GPCS_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41881c, 0x41881c) // (NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418884, 0x418884) // (NV_PGRAPH_PRI_GPCS_MMU_PM, NV_PGRAPH_PRI_GPCS_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x4188c8, 0x4188cc) // (NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418b04, 0x418b04) // (NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418c04, 0x418c04) // (NV_PGRAPH_PRI_GPCS_GPM_PD_PM, NV_PGRAPH_PRI_GPCS_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418c88, 0x418c88) // (NV_PGRAPH_PRI_GPCS_GPM_SD_PM, NV_PGRAPH_PRI_GPCS_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418d00, 0x418d00) // (NV_PGRAPH_PRI_GPCS_GPM_RPT_PM, NV_PGRAPH_PRI_GPCS_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418e08, 0x418e08) // (NV_PGRAPH_PRI_GPCS_SWDX_PM, NV_PGRAPH_PRI_GPCS_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418f08, 0x418f08) // (NV_PGRAPH_PRI_GPCS_WDXPS_PM, NV_PGRAPH_PRI_GPCS_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41900c, 0x41900c) // (NV_PGRAPH_PRI_GPCS_GCC_PERFMON, NV_PGRAPH_PRI_GPCS_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41a0a8, 0x41a0a8) // (NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41a8a0, 0x41a8a8) // (NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON, NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM)
|
||||
#endif
|
||||
#ifdef GPC_BROADCAST_EIGHTH
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418384, 0x418384) // (NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL, NV_PGRAPH_PRI_GPCS_RASTERARB_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x4184a0, 0x4184a0) // (NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL, NV_PGRAPH_PRI_GPCS_PROP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418604, 0x418604) // (NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL, NV_PGRAPH_PRI_GPCS_FRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418680, 0x418680) // (NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL, NV_PGRAPH_PRI_GPCS_WIDCLIP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418714, 0x418714) // (NV_PGRAPH_PRI_GPCS_TC_PM_CTRL, NV_PGRAPH_PRI_GPCS_TC_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41881c, 0x41881c) // (NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL, NV_PGRAPH_PRI_GPCS_SETUP_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418884, 0x418884) // (NV_PGRAPH_PRI_GPCS_MMU_PM, NV_PGRAPH_PRI_GPCS_MMU_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x4188c8, 0x4188cc) // (NV_PGRAPH_PRI_GPCS_ZCULL_PM_CTRL, NV_PGRAPH_PRI_GPCS_ZCULL_DEBUG_0)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418b04, 0x418b04) // (NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL, NV_PGRAPH_PRI_GPCS_CRSTR_PM_CTRL)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418c04, 0x418c04) // (NV_PGRAPH_PRI_GPCS_GPM_PD_PM, NV_PGRAPH_PRI_GPCS_GPM_PD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418c88, 0x418c88) // (NV_PGRAPH_PRI_GPCS_GPM_SD_PM, NV_PGRAPH_PRI_GPCS_GPM_SD_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418d00, 0x418d00) // (NV_PGRAPH_PRI_GPCS_GPM_RPT_PM, NV_PGRAPH_PRI_GPCS_GPM_RPT_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418e08, 0x418e08) // (NV_PGRAPH_PRI_GPCS_SWDX_PM, NV_PGRAPH_PRI_GPCS_SWDX_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x418f08, 0x418f08) // (NV_PGRAPH_PRI_GPCS_WDXPS_PM, NV_PGRAPH_PRI_GPCS_WDXPS_PM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41900c, 0x41900c) // (NV_PGRAPH_PRI_GPCS_GCC_PERFMON, NV_PGRAPH_PRI_GPCS_GCC_PERFMON)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41a0a8, 0x41a0a8) // (NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM, NV_PGRAPH_PRI_GPCS_GPCCS_FALCON_PMM)
|
||||
ACCESS_MAP_REGISTER_RANGE(0x41a8a0, 0x41a8a8) // (NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON, NV_PGRAPH_PRI_GPCS_GPCCS_PERFMON_PM)
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user