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398
include/ampere/ga102/priv_blocker_wl_bl_ranges_init.h
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398
include/ampere/ga102/priv_blocker_wl_bl_ranges_init.h
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/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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/* This file is autogenerated by ref2h.pl. Do not edit */
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/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
|
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* information contained herein is proprietary and confidential to NVIDIA
|
||||
* Corporation. Any use, reproduction, or disclosure without the written
|
||||
* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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/* This file is autogenerated by ref2h.pl. Do not edit */
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/* ------------------------- System Includes -------------------------------- */
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#ifdef LPWR_RM
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#include "ampere/ga102/dev_perf.h"
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#include "ampere/ga102/dev_nv_xve.h"
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#include "ampere/ga102/dev_master.h"
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#include "ampere/ga102/dev_therm.h"
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#include "ampere/ga102/dev_pbdma.h"
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#include "ampere/ga102/dev_nv_xve1.h"
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#include "ampere/ga102/dev_nv_xp.h"
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#include "ampere/ga102/dev_bus.h"
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#include "ampere/ga102/dev_ctrl.h"
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#include "ampere/ga102/dev_timer.h"
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#include "ampere/ga102/dev_top.h"
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#include "disp/v04_01/dev_disp.h"
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#include "ampere/ga102/dev_hdacodec.h"
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#include "ampere/ga102/dev_pwr_pri.h"
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#include "ampere/ga102/dev_fuse.h"
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#include "ampere/ga102/dev_pmgr.h"
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#include "ampere/ga102/dev_flush.h"
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#include "ampere/ga102/dev_ram.h"
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#include "ampere/ga102/dev_trim.h"
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#include "ampere/ga102/dev_xbar.h"
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#include "ampere/ga102/dev_graphics_nobundle.h"
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#include "ampere/ga102/dev_fifo.h"
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#include "ampere/ga102/dev_chiplet_pwr.h"
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#include "ampere/ga102/dev_runlist.h"
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#include "ampere/ga102/dev_chiplet_ism.h"
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#include "ampere/ga102/dev_pri_ringstation_gpc.h"
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#include "ampere/ga102/dev_smcarb.h"
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#else
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#include "dev_perf.h"
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#include "dev_nv_xve.h"
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#include "dev_master.h"
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#include "dev_therm.h"
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#include "dev_pbdma.h"
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#include "dev_nv_xve1.h"
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#include "dev_nv_xp.h"
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#include "dev_bus.h"
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#include "dev_ctrl.h"
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#include "dev_timer.h"
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#include "dev_top.h"
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#include "dev_disp.h"
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#include "dev_hdacodec.h"
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#include "dev_pwr_pri.h"
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#include "dev_fuse.h"
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#include "dev_pmgr.h"
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#include "dev_flush.h"
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#include "dev_ram.h"
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#include "dev_trim.h"
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#include "dev_xbar.h"
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#include "dev_graphics_nobundle.h"
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#include "dev_fifo.h"
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#include "dev_chiplet_pwr.h"
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#include "dev_runlist.h"
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#include "dev_chiplet_ism.h"
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#include "dev_pri_ringstation_gpc.h"
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#include "dev_smcarb.h"
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#endif
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/* ======================================================================================= */
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// Generic MS and GR Region BL/WL ranges which will be used by SEC2/GSP Priv Blocker
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/* ======================================================================================= */
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/* ============================================================== */
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// MS Region White List Ranges for SEC2/GSP Blockers
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/* ============================================================== */
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// XVE & XP Registers
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#define PRIV_BLOCKER_MS_WL_RANGE_START_0 DEVICE_BASE(NV_PCFG)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_0 DEVICE_EXTENT(NV_PCFG)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_1 DEVICE_BASE(NV_PCFG1)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_1 DEVICE_EXTENT(NV_PCFG1)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_2 DEVICE_BASE(NV_XP)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_2 DEVICE_EXTENT(NV_XP)
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// Host Registers
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#define PRIV_BLOCKER_MS_WL_RANGE_START_3 DEVICE_BASE(NV_PMC)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_3 DEVICE_EXTENT(NV_PMC)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_4 DEVICE_BASE(NV_PBUS)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_4 DEVICE_EXTENT(NV_PBUS)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_5 DEVICE_BASE(NV_PTIMER)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_5 DEVICE_EXTENT(NV_PTIMER)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_6 DEVICE_BASE(NV_PTOP)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_6 DEVICE_EXTENT(NV_PTOP)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_7 DEVICE_BASE(NV_CTRL)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_7 DEVICE_EXTENT(NV_CTRL)
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// Perf Registers
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#define PRIV_BLOCKER_MS_WL_RANGE_START_8 DEVICE_BASE(NV_PERF_PMMGPC)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_8 DEVICE_EXTENT(NV_PERF_PMMGPC)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_9 DEVICE_BASE(NV_PERF_PMMFBP)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_9 DEVICE_EXTENT(NV_PERF_PMMFBP)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_10 DEVICE_BASE(NV_PERF_PMMSYS)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_10 DEVICE_EXTENT(NV_PERF_PMMSYS)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_11 DEVICE_BASE(NV_PERF_PMMFBPROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_11 DEVICE_EXTENT(NV_PERF_PMMFBPROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_12 DEVICE_BASE(NV_PERF_PMMGPCROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_12 DEVICE_EXTENT(NV_PERF_PMMGPCROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_13 DEVICE_BASE(NV_PERF_PMMSYSROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_13 DEVICE_EXTENT(NV_PERF_PMMSYSROUTER)
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// Audio Registers
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#define PRIV_BLOCKER_MS_WL_RANGE_START_14 DEVICE_BASE(NV_HDACODEC)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_14 DEVICE_EXTENT(NV_HDACODEC)
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// PMU Registers
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#define PRIV_BLOCKER_MS_WL_RANGE_START_15 DEVICE_BASE(NV_PPWR)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_15 DEVICE_EXTENT(NV_PPWR)
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// FUSE Registers
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#define PRIV_BLOCKER_MS_WL_RANGE_START_16 DEVICE_BASE(NV_FUSE)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_16 DEVICE_EXTENT(NV_FUSE)
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// PMGR Registers
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#define PRIV_BLOCKER_MS_WL_RANGE_START_17 DEVICE_BASE(NV_PMGR)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_17 DEVICE_EXTENT(NV_PMGR)
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// SEC & GSP Registers
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#define PRIV_BLOCKER_MS_WL_RANGE_START_18 DEVICE_BASE(NV_PSEC)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_18 DEVICE_EXTENT(NV_PSEC)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_19 DEVICE_BASE(NV_PGSP)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_19 DEVICE_EXTENT(NV_PGSP)
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// Display Registers
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#define PRIV_BLOCKER_MS_WL_RANGE_START_20 DEVICE_BASE(NV_UDISP)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_20 DEVICE_EXTENT(NV_UDISP)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_21 DEVICE_BASE(NV_PDISP)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_21 DEVICE_EXTENT(NV_PDISP)
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/* #define PRIV_BLOCKER_MS_WL_RANGE_START(22-31) WHITE CYA START ADDRESS */
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/* #define PRIV_BLOCKER_MS_WL_RANGE_END(22-31) WHITE CYA END ADDRESS */
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/* ============================================================== */
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// Macro to init the MS Profile WL ranges in SW
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/* ============================================================== */
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#define PRIV_BLOCKER_MS_PROFILE_WL_RANGES_INIT(_op_) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_0, PRIV_BLOCKER_MS_WL_RANGE_END_0) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_1, PRIV_BLOCKER_MS_WL_RANGE_END_1) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_2, PRIV_BLOCKER_MS_WL_RANGE_END_2) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_3, PRIV_BLOCKER_MS_WL_RANGE_END_3) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_4, PRIV_BLOCKER_MS_WL_RANGE_END_4) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_5, PRIV_BLOCKER_MS_WL_RANGE_END_5) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_6, PRIV_BLOCKER_MS_WL_RANGE_END_6) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_7, PRIV_BLOCKER_MS_WL_RANGE_END_7) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_8, PRIV_BLOCKER_MS_WL_RANGE_END_8) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_9, PRIV_BLOCKER_MS_WL_RANGE_END_9) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_10, PRIV_BLOCKER_MS_WL_RANGE_END_10) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_11, PRIV_BLOCKER_MS_WL_RANGE_END_11) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_12, PRIV_BLOCKER_MS_WL_RANGE_END_12) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_13, PRIV_BLOCKER_MS_WL_RANGE_END_13) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_14, PRIV_BLOCKER_MS_WL_RANGE_END_14) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_15, PRIV_BLOCKER_MS_WL_RANGE_END_15) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_16, PRIV_BLOCKER_MS_WL_RANGE_END_16) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_17, PRIV_BLOCKER_MS_WL_RANGE_END_17) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_18, PRIV_BLOCKER_MS_WL_RANGE_END_18) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_19, PRIV_BLOCKER_MS_WL_RANGE_END_19) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_20, PRIV_BLOCKER_MS_WL_RANGE_END_20) \
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_op_(PRIV_BLOCKER_MS_WL_RANGE_START_21, PRIV_BLOCKER_MS_WL_RANGE_END_21)
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//_op_(PRIV_BLOCKER_MS_WL_RANGE_START_22, PRIV_BLOCKER_MS_WL_RANGE_END_22)
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/* ============================================================== */
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// MS Region Black List Ranges for SEC2/GSP Blockers
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/* ============================================================== */
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#define PRIV_BLOCKER_MS_BL_RANGE_START_0 NV_PBUS_BAR0_WINDOW
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#define PRIV_BLOCKER_MS_BL_RANGE_END_0 NV_PBUS_BAR0_WINDOW
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#define PRIV_BLOCKER_MS_BL_RANGE_START_1 NV_PBUS_BAR1_BLOCK
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#define PRIV_BLOCKER_MS_BL_RANGE_END_1 NV_PBUS_BAR1_BLOCK
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#define PRIV_BLOCKER_MS_BL_RANGE_START_2 NV_PBUS_BAR2_BLOCK
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#define PRIV_BLOCKER_MS_BL_RANGE_END_2 NV_PBUS_BAR2_BLOCK
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#define PRIV_BLOCKER_MS_BL_RANGE_START_3 NV_PBUS_FLUSH_BIND_CTL
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#define PRIV_BLOCKER_MS_BL_RANGE_END_3 NV_PBUS_FLUSH_BIND_CTL
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#define PRIV_BLOCKER_MS_BL_RANGE_START_4 DEVICE_BASE(NV_RUNLIST_GLOBAL_PRI_RANGE_0)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_4 DEVICE_EXTENT(NV_RUNLIST_GLOBAL_PRI_RANGE_0)
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#define PRIV_BLOCKER_MS_BL_RANGE_START_5 DEVICE_BASE(NV_CHRAM_GLOBAL_PRI_RANGE_0)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_5 DEVICE_EXTENT(NV_CHRAM_GLOBAL_PRI_RANGE_0)
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/* Note: NV_PPBDMA will need to be replaced with NV_PBDMA_GLOBAL_PRI_RANGE_0 */
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/* (this will need to happen when NV_PPBDMA is replaced with 0-based NV_PBDMA) */
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#define PRIV_BLOCKER_MS_BL_RANGE_START_6 DEVICE_BASE(NV_PPBDMA)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_6 DEVICE_EXTENT(NV_PPBDMA)
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#define PRIV_BLOCKER_MS_BL_RANGE_START_7 DEVICE_BASE(NV_UFLUSH)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_7 DEVICE_EXTENT(NV_UFLUSH)
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#define PRIV_BLOCKER_MS_BL_RANGE_START_8 DEVICE_BASE(NV_PRAMIN)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_8 DEVICE_EXTENT(NV_PRAMIN)
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#define PRIV_BLOCKER_MS_BL_RANGE_START_9 DEVICE_BASE(NV_PDISP_VGA)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_9 DEVICE_EXTENT(NV_PDISP_VGA)
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/* #define PRIV_BLOCKER_MS_BL_RANGE_START(10-31) BLACKLIST CYA START ADDRESS */
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/* #define PRIV_BLOCKER_MS_BL_RANGE_END(10-31) BLACKLIST CYA END ADDRESS */
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/* SW needs code to program NV_PPWR_PMU_MUTEX(RM_PMU_MUTEX_ID_GPIO) to PRIV_BLOCKER_MS_BL_RANGE_END(24) if PSI enabled */
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/* ============================================================== */
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// Macro to init the MS Profile BL ranges in SW
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/* ============================================================== */
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#define PRIV_BLOCKER_MS_PROFILE_BL_RANGES_INIT(_op_) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_0, PRIV_BLOCKER_MS_BL_RANGE_END_0) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_1, PRIV_BLOCKER_MS_BL_RANGE_END_1) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_2, PRIV_BLOCKER_MS_BL_RANGE_END_2) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_3, PRIV_BLOCKER_MS_BL_RANGE_END_3) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_4, PRIV_BLOCKER_MS_BL_RANGE_END_4) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_5, PRIV_BLOCKER_MS_BL_RANGE_END_5) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_6, PRIV_BLOCKER_MS_BL_RANGE_END_6) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_7, PRIV_BLOCKER_MS_BL_RANGE_END_7) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_8, PRIV_BLOCKER_MS_BL_RANGE_END_8) \
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_op_(PRIV_BLOCKER_MS_BL_RANGE_START_9, PRIV_BLOCKER_MS_BL_RANGE_END_9)
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/* ============================================================== */
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// GR Region White List Ranges for SEC2/GSP Blockers
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/* ============================================================== */
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#define PRIV_BLOCKER_GR_WL_RANGE_START_0 0x00000000
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#define PRIV_BLOCKER_GR_WL_RANGE_END_0 0xffffffff
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/* ============================================================== */
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// Macro to init the GR Profile WL ranges in SW
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/* ============================================================== */
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#define PRIV_BLOCKER_GR_PROFILE_WL_RANGES_INIT(_op_) \
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_op_(PRIV_BLOCKER_GR_WL_RANGE_START_0, PRIV_BLOCKER_GR_WL_RANGE_END_0)
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/* ============================================================== */
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// GR Region Black List Ranges for SEC2/GSP Blockers
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/* ============================================================== */
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#define PRIV_BLOCKER_GR_BL_RANGE_START_0 DEVICE_BASE(NV_PGRAPH)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_0 DEVICE_EXTENT(NV_PGRAPH)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_1 DEVICE_BASE(NV_PTRIM_GPC)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_1 DEVICE_EXTENT(NV_PTRIM_GPC)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_2 DEVICE_BASE(NV_PTRIM_GPC_BCAST)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_2 DEVICE_EXTENT(NV_PTRIM_GPC_BCAST)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_3 DEVICE_BASE(NV_PCHIPLET_PWR)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_3 DEVICE_EXTENT(NV_PCHIPLET_PWR)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_4 DEVICE_BASE(NV_PERF_PMMGPC)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_4 DEVICE_EXTENT(NV_PERF_PMMGPC) //Repeated
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#define PRIV_BLOCKER_GR_BL_RANGE_START_5 DEVICE_BASE(NV_PERF_PMMGPC)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_5 DEVICE_EXTENT(NV_PERF_PMMGPC)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_6 DEVICE_BASE(NV_XBAR_MXBAR_PRI_GPCS_GNIC)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_6 DEVICE_EXTENT(NV_XBAR_MXBAR_PRI_GPCS_GNIC)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_7 DEVICE_BASE(NV_XBAR_MXBAR_PRI_GPC0_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_7 DEVICE_EXTENT(NV_XBAR_MXBAR_PRI_GPC0_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_8 DEVICE_BASE(NV_XBAR_MXBAR_PRI_GPC1_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_8 DEVICE_EXTENT(NV_XBAR_MXBAR_PRI_GPC1_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_9 DEVICE_BASE(NV_XBAR_MXBAR_PRI_GPC2_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_9 DEVICE_EXTENT(NV_XBAR_MXBAR_PRI_GPC2_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_10 DEVICE_BASE(NV_XBAR_MXBAR_PRI_GPC3_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_10 DEVICE_EXTENT(NV_XBAR_MXBAR_PRI_GPC3_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_11 DEVICE_BASE(NV_XBAR_MXBAR_PRI_GPC4_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_11 DEVICE_EXTENT(NV_XBAR_MXBAR_PRI_GPC4_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_12 DEVICE_BASE(NV_XBAR_MXBAR_PRI_GPC5_GNIC0)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_12 DEVICE_EXTENT(NV_XBAR_MXBAR_PRI_GPC5_GNIC0)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_13 DEVICE_BASE(NV_XBAR_MXBAR_PRI_GPC6_GNIC0)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_13 DEVICE_EXTENT(NV_XBAR_MXBAR_PRI_GPC6_GNIC0)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_14 DEVICE_BASE(NV_PCHIPLET_ISM_GPC)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_14 DEVICE_EXTENT(NV_PCHIPLET_ISM_GPC)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_15 DEVICE_BASE(NV_PCHIPLET_ISM_GPCS)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_15 DEVICE_EXTENT(NV_PCHIPLET_ISM_GPCS)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_16 DEVICE_BASE(NV_PPRIV_GPC_GPC)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_16 DEVICE_EXTENT(NV_PPRIV_GPC_GPC)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_17 DEVICE_BASE(NV_PPRIV_GPC_GPCS)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_17 DEVICE_EXTENT(NV_PPRIV_GPC_GPCS)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_18 DEVICE_BASE(NV_PERF_PMMGPC_GPC0)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_18 DEVICE_EXTENT(NV_PERF_PMMGPC_GPC0)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_19 DEVICE_BASE(NV_PERF_PMMGPC_GPC0) //Repeated
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_19 DEVICE_EXTENT(NV_PERF_PMMGPC_GPC0)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_20 DEVICE_BASE(NV_PERF_PMMGPC_GPC1)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_20 DEVICE_EXTENT(NV_PERF_PMMGPC_GPC1)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_21 DEVICE_BASE(NV_PERF_PMMGPC_GPC2)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_21 DEVICE_EXTENT(NV_PERF_PMMGPC_GPC2)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_22 DEVICE_BASE(NV_PERF_PMMGPC_GPC3)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_22 DEVICE_EXTENT(NV_PERF_PMMGPC_GPC3)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_23 DEVICE_BASE(NV_PERF_PMMGPC_GPC4)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_23 DEVICE_EXTENT(NV_PERF_PMMGPC_GPC4)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_24 DEVICE_BASE(NV_PERF_PMMGPC_GPC5)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_24 DEVICE_EXTENT(NV_PERF_PMMGPC_GPC5)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_25 DEVICE_BASE(NV_PERF_PMMGPC_GPC6)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_25 DEVICE_EXTENT(NV_PERF_PMMGPC_GPC6)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_26 DEVICE_BASE(NV_PERF_PMMGPC_GPCS)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_26 DEVICE_EXTENT(NV_PERF_PMMGPC_GPCS)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_START_27 NV_PSMCARB_SMC_PARTITION_GPC_MAP(0)
|
||||
#define PRIV_BLOCKER_GR_BL_RANGE_END_27 NV_PSMCARB_SMC_PARTITION_GPC_MAP(6)
|
||||
|
||||
/* ============================================================== */
|
||||
// Macro to init the GR Profile BL ranges in SW
|
||||
/* ============================================================== */
|
||||
#define PRIV_BLOCKER_GR_PROFILE_BL_RANGES_INIT(_op_) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_0, PRIV_BLOCKER_GR_BL_RANGE_END_0) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_1, PRIV_BLOCKER_GR_BL_RANGE_END_1) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_2, PRIV_BLOCKER_GR_BL_RANGE_END_2) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_3, PRIV_BLOCKER_GR_BL_RANGE_END_3) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_4, PRIV_BLOCKER_GR_BL_RANGE_END_4) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_5, PRIV_BLOCKER_GR_BL_RANGE_END_5) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_6, PRIV_BLOCKER_GR_BL_RANGE_END_6) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_7, PRIV_BLOCKER_GR_BL_RANGE_END_7) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_8, PRIV_BLOCKER_GR_BL_RANGE_END_8) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_9, PRIV_BLOCKER_GR_BL_RANGE_END_9) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_10, PRIV_BLOCKER_GR_BL_RANGE_END_10) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_11, PRIV_BLOCKER_GR_BL_RANGE_END_11) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_12, PRIV_BLOCKER_GR_BL_RANGE_END_12) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_13, PRIV_BLOCKER_GR_BL_RANGE_END_13) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_14, PRIV_BLOCKER_GR_BL_RANGE_END_14) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_15, PRIV_BLOCKER_GR_BL_RANGE_END_15) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_16, PRIV_BLOCKER_GR_BL_RANGE_END_16) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_17, PRIV_BLOCKER_GR_BL_RANGE_END_17) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_18, PRIV_BLOCKER_GR_BL_RANGE_END_18) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_19, PRIV_BLOCKER_GR_BL_RANGE_END_19) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_20, PRIV_BLOCKER_GR_BL_RANGE_END_20) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_21, PRIV_BLOCKER_GR_BL_RANGE_END_21) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_22, PRIV_BLOCKER_GR_BL_RANGE_END_22) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_23, PRIV_BLOCKER_GR_BL_RANGE_END_23) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_24, PRIV_BLOCKER_GR_BL_RANGE_END_24) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_25, PRIV_BLOCKER_GR_BL_RANGE_END_25) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_26, PRIV_BLOCKER_GR_BL_RANGE_END_26) \
|
||||
_op_(PRIV_BLOCKER_GR_BL_RANGE_START_27, PRIV_BLOCKER_GR_BL_RANGE_END_27)
|
||||
|
||||
|
||||
/* ======================================================================================= */
|
||||
// MS and GR Region BL/WL ranges which will be used by XVE BAR Blocker
|
||||
/* ======================================================================================= */
|
||||
|
||||
/* ============================================================== */
|
||||
// MS Region White List Ranges for XVE BAR Blocker
|
||||
/* ============================================================== */
|
||||
/* #define PRIV_BLOCKER_XVE_MS_WL_RANGE_START(9-31) WHITELIST CYA START ADDRESS */
|
||||
/* #define PRIV_BLOCKER_XVE_MS_WL_RANGE_END(9-31) WHITELIST CYA END ADDRESS */
|
||||
|
||||
/* ============================================================== */
|
||||
// Macro to init the MS Profile WL ranges in SW for XVE BAR Blocker
|
||||
/* ============================================================== */
|
||||
#define PRIV_BLOCKER_XVE_MS_PROFILE_WL_RANGES_INIT(_op_) \
|
||||
_op_(PRIV_BLOCKER_XVE_MS_WL_RANGE_START_0, PRIV_BLOCKER_XVE_MS_WL_RANGE_END_0)
|
||||
|
||||
/* ============================================================== */
|
||||
// MS Region Black List Ranges for XVE Bar Blocker
|
||||
/* ============================================================== */
|
||||
#define PRIV_BLOCKER_XVE_MS_BL_RANGE_START_0 NV_PPWR_PMU_MUTEX(MUTEX_LOG_TO_PHY_ID(NV_MUTEX_ID_GPIO))
|
||||
#define PRIV_BLOCKER_XVE_MS_BL_RANGE_END_0 NV_PPWR_PMU_MUTEX(MUTEX_LOG_TO_PHY_ID(NV_MUTEX_ID_GPIO))
|
||||
|
||||
/* ============================================================== */
|
||||
// Macro to init the MS Profile BL ranges in SW for XVE BAR Blocker
|
||||
/* ============================================================== */
|
||||
#define PRIV_BLOCKER_XVE_MS_PROFILE_BL_RANGES_INIT(_op_) \
|
||||
_op_(PRIV_BLOCKER_XVE_MS_BL_RANGE_START_0, PRIV_BLOCKER_XVE_MS_BL_RANGE_END_0)
|
||||
|
||||
/* ============================================================== */
|
||||
// GR Region Black List Ranges for XVE Bar Blocker
|
||||
/* ============================================================== */
|
||||
#define PRIV_BLOCKER_XVE_GR_BL_RANGE_START_0 NV_PSMCARB_SMC_PARTITION_GPC_MAP(0)
|
||||
#define PRIV_BLOCKER_XVE_GR_BL_RANGE_END_0 NV_PSMCARB_SMC_PARTITION_GPC_MAP(6)
|
||||
|
||||
/* ============================================================== */
|
||||
// Macro to init the GR Profile BL ranges in SW for XVE BAR Blocker
|
||||
/* ============================================================== */
|
||||
#define PRIV_BLOCKER_XVE_GR_PROFILE_BL_RANGES_INIT(_op_) \
|
||||
_op_(PRIV_BLOCKER_XVE_GR_BL_RANGE_START_0, PRIV_BLOCKER_XVE_GR_BL_RANGE_END_0)
|
||||
|
||||
|
||||
/* ============================================================== */
|
||||
// PRIV BLOCKER RANGES for SW BLOCKER - Bug 2500177
|
||||
/* ============================================================== */
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_START_0 DEVICE_BASE(NV_PCHIPLET_PWR_GPC) //1. 0x0010C000
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_END_0 DEVICE_EXTENT(NV_PCHIPLET_PWR_GPCS) //1. 0x0010e0ff
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_START_1 DEVICE_BASE(NV_PPRIV_GPC_GPCS) //2. 0x00120800
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_END_1 DEVICE_EXTENT(NV_PPRIV_GPC) //2. 0x00127fff
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_START_2 DEVICE_BASE(NV_PTRIM_GPC_BCAST) //3. 0x00132800
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_END_2 DEVICE_EXTENT(NV_PCHIPLET_ISM_GPCS) //3. 0x001ff1ff
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_START_3 DEVICE_BASE(NV_PERF_PMMGPC_GPC0ROUTER) //4. 0x00244000
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_END_3 DEVICE_EXTENT(NV_PERF_PMMGPC_GPCS) //4. 0x0027BFFF
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_START_4 DEVICE_BASE(NV_PGRAPH) //5. 0x00400000
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_END_4 DEVICE_EXTENT(NV_PGRAPH) //5. 0x005FFFFF
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_START_5 0x01018300 //6. Placeholder for 0x01018300
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_END_5 0x011BEFFF //6. Placeholder for 0x011BEFFF
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_START_6 NV_PSMCARB_SMC_PARTITION_GPC_MAP(0) //7. bug 200673478
|
||||
#define PRIV_SW_BLOCKER_GR_BL_RANGE_END_6 NV_PSMCARB_SMC_PARTITION_GPC_MAP(6)
|
||||
|
||||
|
||||
/* ============================================================== */
|
||||
// Macro to init PRIV BLOCKER RANGES for SW BLOCKER - Bug 2500177
|
||||
/* ============================================================== */
|
||||
#define PRIV_SW_BLOCKER_GR_PROFILE_BL_RANGES_INIT(_op_) \
|
||||
_op_(PRIV_SW_BLOCKER_GR_BL_RANGE_START_0, PRIV_SW_BLOCKER_GR_BL_RANGE_END_0) \
|
||||
_op_(PRIV_SW_BLOCKER_GR_BL_RANGE_START_1, PRIV_SW_BLOCKER_GR_BL_RANGE_END_1) \
|
||||
_op_(PRIV_SW_BLOCKER_GR_BL_RANGE_START_2, PRIV_SW_BLOCKER_GR_BL_RANGE_END_2) \
|
||||
_op_(PRIV_SW_BLOCKER_GR_BL_RANGE_START_3, PRIV_SW_BLOCKER_GR_BL_RANGE_END_3) \
|
||||
_op_(PRIV_SW_BLOCKER_GR_BL_RANGE_START_4, PRIV_SW_BLOCKER_GR_BL_RANGE_END_4) \
|
||||
_op_(PRIV_SW_BLOCKER_GR_BL_RANGE_START_5, PRIV_SW_BLOCKER_GR_BL_RANGE_END_5) \
|
||||
_op_(PRIV_SW_BLOCKER_GR_BL_RANGE_START_6, PRIV_SW_BLOCKER_GR_BL_RANGE_END_6)
|
||||
Reference in New Issue
Block a user