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Ole Algoritme
2022-09-05 21:52:22 +02:00
commit 698a8f7487
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include/ampere/ga102/dev_pri_ringstation_control_sys.h Normal file
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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_pri_ringstation_control_sys_h__
#define __ga102_dev_pri_ringstation_control_sys_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_RS_CTRL_SYS 0x1220ff:0x122000 /* RW--D */
#define NV_PPRIV_RS_CTRL_SYS_RING_STATION_SUBSTRATE 0x00122000 /* R--4R */
#define NV_PPRIV_RS_CTRL_SYS_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION 4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK 0x0012205c /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST 0x00122004 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK 0x0012205c /* */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET 3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_0 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_1 0x00000001 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_2 0x00000002 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_3 0x00000003 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_4 0x00000004 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_5 0x00000005 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_6 0x00000006 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_7 0x00000007 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_8 0x00000008 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_9 0x00000009 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_10 0x0000000a /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_11 0x0000000b /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_12 0x0000000c /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_13 0x0000000d /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_14 0x0000000e /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_15 0x0000000f /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_FORCE 4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_FORCE_ENABLE 0x00000001 /* RW--T */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_FORCE_DISABLE 0x00000000 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG(i) (0x00122008+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG__SIZE_1 16 /* */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK 0x0012205c /* */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG_TIMER 7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG_TIMER_RESET 0x0000000a /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG_MAX_UPDATES 15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_CG1 0x00122048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG 1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG_ENABLED 0x00000000 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG_DISABLED 0x00000003 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS 0x0012204c /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS__PRIV_LEVEL_MASK 0x0012205c /* */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_NO_WAKEUP 0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_MAX_UPDATES 1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED 0x00000000 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED 0x00000001 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK 0x00122050 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION 0x00122054 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION__PRIV_LEVEL_MASK 0x00122050 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_TAG (5-1):0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_TAG_INIT 0x00000000 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO(i) (0x001220c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO__SIZE_1 7 /* */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENABLE 31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE 0x00000001 /* R---V */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE 0x00000000 /* R-B-V */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENGINE_ID (8+1-1):8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT 0x00000000 /* R-B-V */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID (3-1):0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT 0x00000000 /* R-B-V */
#endif // __ga102_dev_pri_ringstation_control_sys_h__